diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
| commit | e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb (patch) | |
| tree | 553bace58f742b4c98ac52d600a1103901011b8b /tests/long/se | |
| parent | 0d8d6e44419e2c5464012b66abc62aaad433026b (diff) | |
| download | gem5-e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb.tar.xz | |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/se')
25 files changed, 1954 insertions, 1350 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index 04ace1eeb..e8166ece0 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -132,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -591,6 +592,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +653,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -700,6 +703,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -749,6 +753,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr @@ -757,6 +762,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -830,6 +836,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 52746e018..4f1cfb81e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.061494 # Nu sim_ticks 61493732000 # Number of ticks simulated final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271090 # Simulator instruction rate (inst/s) -host_op_rate 272440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 183993432 # Simulator tick rate (ticks/s) -host_mem_usage 445016 # Number of bytes of host memory used -host_seconds 334.22 # Real time elapsed on the host +host_inst_rate 144123 # Simulator instruction rate (inst/s) +host_op_rate 144840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 97818525 # Simulator tick rate (ticks/s) +host_mem_usage 433504 # Number of bytes of host memory used +host_seconds 628.65 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory system.physmem.bytes_read::total 996800 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 16209782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -390,8 +394,8 @@ system.cpu.dcache.tags.total_refs 26267660 # To system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3616.604238 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id @@ -400,61 +404,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 21598813 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 4661073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 26259886 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26259886 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits system.cpu.dcache.overall_hits::total 26259886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14256024494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 27248752 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 27248752 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -466,45 +470,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11523 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 38663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 38663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements @@ -599,9 +603,11 @@ system.cpu.l2cache.tags.sampled_refs 15558 # Sa system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885294 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id @@ -612,57 +618,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 903199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 32224 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 935423 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 935423 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits system.cpu.l2cache.overall_hits::total 935423 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1029788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52344250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 977444250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1029788500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52344250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 977444250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -672,43 +696,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 8fe365c4e..3203f61e7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 93f93a6a3..9abbba24f 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.410940 # Nu sim_ticks 410940483000 # Number of ticks simulated final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339016 # Simulator instruction rate (inst/s) -host_op_rate 339016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 227676015 # Simulator tick rate (ticks/s) -host_mem_usage 297088 # Number of bytes of host memory used -host_seconds 1804.94 # Real time elapsed on the host +host_inst_rate 207244 # Simulator instruction rate (inst/s) +host_op_rate 207244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139181064 # Simulator tick rate (ticks/s) +host_mem_usage 283892 # Number of bytes of host memory used +host_seconds 2952.56 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24149568 # Number of bytes read from this memory system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377337 # Number of read requests responded to by this memory system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 416138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58766583 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59182721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 416138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58766583 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 380009 # Number of read requests accepted system.physmem.writeReqs 292569 # Number of write requests accepted @@ -339,8 +343,8 @@ system.cpu.dcache.tags.total_refs 202631199 # To system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.778260 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.778260 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id @@ -350,53 +354,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146964985 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 146964985 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666214 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202631199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 202631199 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202631199 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 202631199 # number of overall hits system.cpu.dcache.overall_hits::total 202631199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1908330 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543820 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3452150 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 3452150 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3452150 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 3452150 # number of overall misses system.cpu.dcache.overall_misses::total 3452150 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36414832750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 44905898000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81320730750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81320730750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81320730750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 148873315 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 206083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206083349 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 206083349 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206083349 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016751 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19082.041759 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19082.041759 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29087.521861 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29087.521861 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -408,45 +412,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks system.cpu.dcache.writebacks::total 2340060 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143560 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769044 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769044 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912604 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912604 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912604 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912604 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764770 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764770 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774776 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774776 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539546 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539546 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539546 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539546 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222614500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30222614500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21167535500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21167535500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51390150000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51390150000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51390150000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51390150000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17125.525989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17125.525989 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27320.845638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27320.845638 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3192 # number of replacements @@ -543,9 +547,11 @@ system.cpu.l2cache.tags.sampled_refs 379722 # Sa system.cpu.l2cache.tags.avg_refs 9.773324 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 188676425000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 21419.098483 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8079.778788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 178.648433 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7901.130355 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.653659 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005452 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.241123 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.900234 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id @@ -556,57 +562,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18831 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 40234870 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 40234870 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1593052 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2349 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1590703 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1593052 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2340060 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2340060 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 571506 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 571506 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 571506 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2164558 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2349 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2162209 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2164558 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2164558 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2349 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2162209 # number of overall hits system.cpu.l2cache.overall_hits::total 2164558 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 173383 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 2672 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 170711 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 173383 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 206626 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206626 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206626 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 380009 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2672 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 377337 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 380009 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 380009 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 2672 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 377337 # number of overall misses system.cpu.l2cache.overall_misses::total 380009 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12672404250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189570250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12482834000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 12672404250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14718134000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14718134000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 14718134000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27390538250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 189570250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27200968000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 27390538250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27390538250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 189570250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27200968000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 27390538250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766435 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1761414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1766435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2340060 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2340060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778132 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 778132 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 778132 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2544567 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5021 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2539546 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2544567 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2544567 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5021 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2539546 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2544567 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098154 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.532165 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.096917 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.098154 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265541 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265541 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.265541 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149341 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.532165 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148584 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.149341 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149341 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.532165 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.149341 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73089.081686 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70946.949850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73122.610728 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 73089.081686 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71230.793801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71230.793801 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71230.793801 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70946.949850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72086.670536 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 72078.656690 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70946.949850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72086.670536 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 72078.656690 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -618,37 +642,49 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 292569 # number of writebacks system.cpu.l2cache.writebacks::total 292569 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2672 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170711 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 173383 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206626 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206626 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206626 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2672 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377337 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 380009 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 380009 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2672 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377337 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 380009 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460839250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155967750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10304871500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460839250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12089060000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12089060000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12089060000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22549899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 155967750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22393931500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 22549899250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22549899250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 155967750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22393931500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 22549899250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096917 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265541 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265541 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.149341 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.149341 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60333.707745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58371.163922 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60364.425843 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58506.964274 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58506.964274 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index 2fe2a523a..452217687 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -132,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -591,6 +592,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +653,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -700,6 +703,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -749,6 +753,7 @@ eventq_index=0 type=LiveProcess cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr @@ -757,6 +762,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -830,6 +836,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index a1fa65b86..441853c88 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.365317 # Nu sim_ticks 365317233000 # Number of ticks simulated final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 241300 # Simulator instruction rate (inst/s) -host_op_rate 261360 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174011250 # Simulator tick rate (ticks/s) -host_mem_usage 315696 # Number of bytes of host memory used -host_seconds 2099.39 # Real time elapsed on the host +host_inst_rate 157262 # Simulator instruction rate (inst/s) +host_op_rate 170335 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113407877 # Simulator tick rate (ticks/s) +host_mem_usage 304680 # Number of bytes of host memory used +host_seconds 3221.27 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9226048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 222144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9003904 # Number of bytes read from this memory system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140686 # Number of read requests responded to by this memory system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 608085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24646809 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25254894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 608085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24646809 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 144157 # Number of read requests accepted system.physmem.writeReqs 96561 # Number of write requests accepted @@ -428,8 +432,8 @@ system.cpu.dcache.tags.total_refs 171281876 # To system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.074819 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4071.074819 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id @@ -439,61 +443,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 114766084 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 114766084 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538710 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538710 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 168304794 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 168304794 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168304794 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 168304794 # number of overall hits system.cpu.dcache.overall_hits::total 168304794 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854755 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 854755 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 700596 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700596 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1555351 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1555351 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1555351 # number of overall misses system.cpu.dcache.overall_misses::total 1555351 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13707430482 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13707430482 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20521575250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20521575250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 34229005732 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34229005732 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 34229005732 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34229005732 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 115620839 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 115620839 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 169860145 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169860145 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 169860145 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169860145 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.009157 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.009157 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16036.677740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16036.677740 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29291.596369 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29291.596369 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -505,45 +509,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1068525 # number of writebacks system.cpu.dcache.writebacks::total 1068525 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66991 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66991 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 66991 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344452 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 344452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411443 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411443 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 411443 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411443 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411443 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 411443 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787764 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787764 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 787764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356144 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 356144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1143908 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143908 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1143908 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1143908 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143908 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1143908 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11252029015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11252029015 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252029015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10073374750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10073374750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21325403765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21325403765 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21325403765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21325403765 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006734 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006734 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14283.502439 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14283.502439 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28284.555545 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28284.555545 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17690 # number of replacements @@ -640,9 +644,11 @@ system.cpu.l2cache.tags.sampled_refs 142590 # Sa system.cpu.l2cache.tags.avg_refs 11.815113 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 163177408500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 23523.224801 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4125.233493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.561382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3735.672111 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.717872 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125892 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011888 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.114004 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.843764 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31187 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id @@ -652,57 +658,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951752 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18354956 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18354956 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 763767 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 16090 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 747677 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 763767 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1068525 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1068525 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255530 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255530 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 255530 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1019297 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 16090 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1003207 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1019297 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1019297 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 16090 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1003207 # number of overall hits system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 43306 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3473 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 39833 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 43306 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 100868 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 100868 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 100868 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 144174 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3473 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140701 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 144174 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 144174 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3473 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140701 # number of overall misses system.cpu.l2cache.overall_misses::total 144174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3229271000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 248520000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980751000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 3229271000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7164307250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7164307250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 7164307250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10393578250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 248520000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10145058250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 10393578250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10393578250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 248520000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10145058250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 10393578250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 807073 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 19563 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 787510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 807073 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1068525 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1068525 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356398 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356398 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 356398 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1163471 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 19563 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1143908 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 1163471 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1163471 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 19563 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1143908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1163471 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053658 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177529 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050581 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.053658 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283021 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283021 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.283021 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123917 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177529 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123000 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.123917 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123917 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177529 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123000 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123917 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74568.674087 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71557.731068 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74831.195240 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 74568.674087 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71026.561942 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71026.561942 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 72090.517361 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -714,43 +738,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks system.cpu.l2cache.writebacks::total 96561 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3471 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100868 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100868 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3471 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140686 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3471 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140686 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 204743500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2475547000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5883442250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204743500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8358989250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204743500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8358989250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050562 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283021 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58986.891386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62171.555578 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58328.134294 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 8a55cdea8..537f6d0ab 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index fd544a1a5..688c5f811 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.226819 # Nu sim_ticks 226818771000 # Number of ticks simulated final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333141 # Simulator instruction rate (inst/s) -host_op_rate 333141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189539219 # Simulator tick rate (ticks/s) -host_mem_usage 300760 # Number of bytes of host memory used -host_seconds 1196.69 # Real time elapsed on the host +host_inst_rate 207340 # Simulator instruction rate (inst/s) +host_op_rate 207340 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 117965343 # Simulator tick rate (ticks/s) +host_mem_usage 287544 # Number of bytes of host memory used +host_seconds 1922.76 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 503872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 7873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2221474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1122447 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2221474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs 168028615 # To system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id @@ -318,53 +322,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 94513823 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 94513823 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 73514792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514792 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 168028615 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 168028615 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168028615 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 168028615 # number of overall hits system.cpu.dcache.overall_hits::total 168028615 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1181 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5938 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5938 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 7119 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81009750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 81009750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391587500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 391587500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 472597250 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 472597250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 472597250 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168035734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168035734 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168035734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168035734 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68594.199831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68594.199831 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65946.025598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65946.025598 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -376,45 +380,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2743 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2743 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2954 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2954 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 970 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64296000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 214342750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278638750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278638750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66284.536082 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67086.932707 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements @@ -510,9 +514,11 @@ system.cpu.l2cache.tags.sampled_refs 5273 # Sa system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786392 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.752394 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 642.033998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019593 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id @@ -522,57 +528,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 88415 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 88415 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1405 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1466 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1279 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1466 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1466 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1279 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits system.cpu.l2cache.overall_hits::total 1466 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4736 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3895 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 841 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4736 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 3137 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7873 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7873 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263088750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61866750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210698500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 210698500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 535654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 263088750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 272565250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 535654000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 263088750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 272565250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6141 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5174 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9339 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9339 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5174 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9339 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.771210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843024 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843024 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67545.250321 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73563.317479 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67165.604080 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -582,37 +606,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4736 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3895 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 4736 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3137 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214177750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51424250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 171025500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214177750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 222449750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214177750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 222449750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54987.869063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61146.551724 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54518.807778 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index c0739097e..de709e95a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index d0b9d8c3b..dd174365b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.216828 # Nu sim_ticks 216828260500 # Number of ticks simulated final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175239 # Simulator instruction rate (inst/s) -host_op_rate 210394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139163086 # Simulator tick rate (ticks/s) -host_mem_usage 320864 # Number of bytes of host memory used -host_seconds 1558.09 # Real time elapsed on the host +host_inst_rate 113548 # Simulator instruction rate (inst/s) +host_op_rate 136327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90171945 # Simulator tick rate (ticks/s) +host_mem_usage 309844 # Number of bytes of host memory used +host_seconds 2404.61 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 485440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory system.physmem.bytes_read::total 485440 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 7585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2238823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2238823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7585 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -390,8 +394,8 @@ system.cpu.dcache.tags.total_refs 168783807 # To system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009488 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id @@ -402,61 +406,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 86714567 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 82047450 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 168762017 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168762017 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits system.cpu.dcache.overall_hits::total 168762017 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5227 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7290 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126489706 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360451750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486941456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168769307 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168769307 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61313.478429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68959.584848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -468,45 +472,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 422 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2870 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36927 # number of replacements @@ -603,9 +607,11 @@ system.cpu.l2cache.tags.sampled_refs 5647 # Sa system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798959 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.451697 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.347263 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096632 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020702 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id @@ -616,57 +622,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 35730 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 35439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35746 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 35439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35746 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 35439 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits system.cpu.l2cache.overall_hits::total 35746 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4776 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1350 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 2854 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7630 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326530500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 230834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95696250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 194789750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 230834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 290486000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 521320250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 230834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 290486000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 38865 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2870 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 43376 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 38865 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 43376 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 38865 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117908 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088151 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994425 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088151 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088151 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67377.189142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70886.111111 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68251.489138 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -676,43 +700,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 45 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 45 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3423 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423305000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index a21e90645..05b955543 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 896e43907..7bcf4595f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.559962 # Nu sim_ticks 559961514500 # Number of ticks simulated final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 343254 # Simulator instruction rate (inst/s) -host_op_rate 343254 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206945650 # Simulator tick rate (ticks/s) -host_mem_usage 305268 # Number of bytes of host memory used -host_seconds 2705.84 # Real time elapsed on the host +host_inst_rate 216839 # Simulator instruction rate (inst/s) +host_op_rate 216839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 130731039 # Simulator tick rate (ticks/s) +host_mem_usage 291560 # Number of bytes of host memory used +host_seconds 4283.31 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18657216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 291519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33318747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 32985124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted @@ -331,8 +335,8 @@ system.cpu.dcache.tags.total_refs 323503178 # To system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.890165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id @@ -343,53 +347,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 225339131 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 225339131 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 323503178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 323503178 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 323503178 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 323503178 # number of overall hits system.cpu.dcache.overall_hits::total 323503178 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 711929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 849082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23417135750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9028767000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32445902750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32445902750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32445902750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 324352260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 324352260 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 324352260 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 324352260 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32892.515616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32892.515616 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65829.890706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65829.890706 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -401,45 +405,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks system.cpu.dcache.writebacks::total 91489 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 312 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68142 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 68454 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68454 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 68454 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68454 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69011 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 780628 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 780628 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21915650000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4445743250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26361393250 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26361393250 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30796.973653 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64420.791613 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10606 # number of replacements @@ -536,9 +540,11 @@ system.cpu.l2cache.tags.sampled_refs 291476 # Sa system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.517639 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 83.731537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29651.786103 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002555 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.904901 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id @@ -549,57 +555,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7436223 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 499092 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 9430 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 499092 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 501458 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 9430 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 501458 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 501458 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 9430 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits system.cpu.l2cache.overall_hits::total 501458 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 224875 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 2920 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 221955 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66645 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 291520 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2920 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288600 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 291520 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 2920 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288600 # number of overall misses system.cpu.l2cache.overall_misses::total 291520 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201319000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16307399500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4353044250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 201319000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20660443750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20861762750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 201319000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20660443750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 723967 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12350 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 792978 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 12350 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 780628 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 792978 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792978 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12350 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 792978 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.310615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236437 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.310615 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.965716 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367627 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236437 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367627 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236437 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68944.863014 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73471.647406 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65316.891740 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -611,37 +635,49 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2920 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221955 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66645 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 291520 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2920 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288600 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 291520 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164600500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13505684500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519774750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164600500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17025459250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17190059750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164600500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17025459250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56370.034247 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60848.750873 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52813.785730 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 11060cf95..7a6d5db32 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.541786 # Nu sim_ticks 541786101000 # Number of ticks simulated final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183531 # Simulator instruction rate (inst/s) -host_op_rate 225950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155207340 # Simulator tick rate (ticks/s) -host_mem_usage 320704 # Number of bytes of host memory used -host_seconds 3490.72 # Real time elapsed on the host +host_inst_rate 115987 # Simulator instruction rate (inst/s) +host_op_rate 142796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98087491 # Simulator tick rate (ticks/s) +host_mem_usage 309428 # Number of bytes of host memory used +host_seconds 5523.50 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18593856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34319552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted @@ -415,8 +419,8 @@ system.cpu.dcache.tags.total_refs 378457747 # To system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.645412 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id @@ -427,61 +431,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 249632505 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 128813764 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 378446269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 378446269 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits system.cpu.dcache.overall_hits::total 378446269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 713747 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 851460 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32255064217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 379297729 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 379297729 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -493,45 +497,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 752 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68391 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 69143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 69143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23590 # number of replacements @@ -626,9 +630,11 @@ system.cpu.l2cache.tags.sampled_refs 290493 # Sa system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.519731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29632.926805 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.904325 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id @@ -639,57 +645,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 513866 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 491102 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 517097 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 22764 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 494333 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 517097 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 22764 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 494333 # number of overall hits system.cpu.l2cache.overall_hits::total 517097 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 224471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 2578 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 221893 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66091 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 290562 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2578 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses system.cpu.l2cache.overall_misses::total 290562 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175909750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15921496500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4429448000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 175909750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20350944500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20526854250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 175909750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20350944500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25342 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712995 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69322 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 807659 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 25342 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782317 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 807659 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25342 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782317 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.304022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101728 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311213 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101728 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368117 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68234.968968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71753.036373 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67020.441512 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -701,43 +725,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 32 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 32 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 32 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16862626750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 1993a40dc..47efecce5 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.058585 # Nu sim_ticks 58584661500 # Number of ticks simulated final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 346754 # Simulator instruction rate (inst/s) -host_op_rate 346754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 229702503 # Simulator tick rate (ticks/s) -host_mem_usage 303900 # Number of bytes of host memory used -host_seconds 255.05 # Real time elapsed on the host +host_inst_rate 201524 # Simulator instruction rate (inst/s) +host_op_rate 201524 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 133496887 # Simulator tick rate (ticks/s) +host_mem_usage 290684 # Number of bytes of host memory used +host_seconds 438.85 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 10664384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 516608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 166631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 182033722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8818144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 173215578 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 182033722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8818144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 173215578 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 166631 # Number of read requests accepted system.physmem.writeReqs 114048 # Number of write requests accepted @@ -335,8 +339,8 @@ system.cpu.dcache.tags.total_refs 34616515 # To system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.523211 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994024 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4071.523211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994024 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id @@ -345,53 +349,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20283193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 20283193 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 14333322 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333322 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 34616515 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 34616515 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 34616515 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 34616515 # number of overall hits system.cpu.dcache.overall_hits::total 34616515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 89440 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 89440 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 280055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280055 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 369495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 369495 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 369495 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 369495 # number of overall misses system.cpu.dcache.overall_misses::total 369495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4407640500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4407640500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 19996177500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19996177500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 24403818000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24403818000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 24403818000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24403818000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 24403818000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20372633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 20372633 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20372633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 34986010 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34986010 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 34986010 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 34986010 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34986010 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34986010 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019164 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.010561 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010561 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.010561 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010561 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49280.417039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49280.417039 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71400.894467 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71400.894467 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66046.409288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66046.409288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66046.409288 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -403,45 +407,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks system.cpu.dcache.writebacks::total 168546 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28125 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28125 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 28125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136498 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136498 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 136498 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 164623 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164623 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 164623 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164623 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 164623 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61315 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61315 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143557 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143557 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204872 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204872 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204872 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204872 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204872 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2422248250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2422248250 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9931035500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9931035500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12353283750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12353283750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12353283750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12353283750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12353283750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005856 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005856 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39504.986545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39504.986545 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39504.986545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69178.343794 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69178.343794 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69178.343794 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60297.569946 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60297.569946 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 153786 # number of replacements @@ -537,9 +541,11 @@ system.cpu.l2cache.tags.sampled_refs 164780 # Sa system.cpu.l2cache.tags.avg_refs 1.339076 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26240.320965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4237.109970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2376.783596 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1860.326375 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.800791 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129306 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.056773 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.930097 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id @@ -550,57 +556,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4542362 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4542362 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 181399 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 147762 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 181399 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 168546 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 168546 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 12676 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12676 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12676 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 194075 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 147762 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46313 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 194075 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 194075 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 147762 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46313 # number of overall hits system.cpu.l2cache.overall_hits::total 194075 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 35750 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 8073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27677 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 35750 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 130882 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 166632 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 8073 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158559 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 166632 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 166632 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 8073 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158559 # number of overall misses system.cpu.l2cache.overall_misses::total 166632 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2603729750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 579593000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2024136750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2603729750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9660681500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9660681500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 9660681500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12264411250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 579593000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11684818250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 12264411250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12264411250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 579593000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11684818250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 12264411250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 217149 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 155835 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 61314 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 217149 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 168546 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168546 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143558 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143558 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143558 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 360707 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 155835 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204872 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 360707 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 360707 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 155835 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204872 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 360707 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.164634 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.051805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.451398 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.164634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911701 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911701 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.911701 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461959 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.051805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773942 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.461959 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461959 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.051805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.461959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72831.601399 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71794.004707 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73134.254074 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 72831.601399 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73812.147583 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73812.147583 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73812.147583 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73601.776670 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71794.004707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73693.819020 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 73601.776670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73601.776670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71794.004707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73693.819020 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 73601.776670 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -612,37 +636,49 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 114048 # number of writebacks system.cpu.l2cache.writebacks::total 114048 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35750 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8073 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27677 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 35750 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130882 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 166632 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8073 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158559 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 166632 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 166632 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8073 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158559 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 166632 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2149088750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 478164000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1670924750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2149088750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7975554000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975554000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975554000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10124642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 478164000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9646478750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 10124642750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10124642750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 478164000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9646478750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 10124642750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.164634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.451398 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911701 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773942 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.461959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.461959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60114.370629 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59230.026013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60372.321783 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60114.370629 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60936.981403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60936.981403 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60936.981403 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59230.026013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60838.418191 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59230.026013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60838.418191 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 217149 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 72bc50e35..532524c0d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=vortex lendian.raw cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index e5a2f02e5..b9814d1e2 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.057816 # Nu sim_ticks 57815555000 # Number of ticks simulated final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199176 # Simulator instruction rate (inst/s) -host_op_rate 254717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162383906 # Simulator tick rate (ticks/s) -host_mem_usage 320240 # Number of bytes of host memory used -host_seconds 356.04 # Real time elapsed on the host +host_inst_rate 131971 # Simulator instruction rate (inst/s) +host_op_rate 168772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 107593052 # Simulator tick rate (ticks/s) +host_mem_usage 309228 # Number of bytes of host memory used +host_seconds 537.35 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8247808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 142657249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128872 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted @@ -419,8 +423,8 @@ system.cpu.dcache.tags.total_refs 42664902 # To system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.581764 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id @@ -429,61 +433,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 22989229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19643835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 42633064 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 42633064 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits system.cpu.dcache.overall_hits::total 42633064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 206066 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 262131 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 262131 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses system.cpu.dcache.overall_misses::total 262131 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17343763437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42895195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42895195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.006111 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.006111 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38299.160564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73745.892093 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -495,45 +499,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks system.cpu.dcache.writebacks::total 128441 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2577 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99030 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 101607 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 101607 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53488 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107036 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160524 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160524 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1987609313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7609976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9597585313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37159.910877 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71097.350424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59789.098907 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59789.098907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42682 # number of replacements @@ -629,9 +633,11 @@ system.cpu.l2cache.tags.sampled_refs 126852 # Sa system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3229.441462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098555 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047701 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id @@ -642,57 +648,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 71548 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 39644 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31904 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4755 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4755 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 76303 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 39644 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 76303 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 76303 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 39644 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits system.cpu.l2cache.overall_hits::total 76303 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 26665 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 5081 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 26665 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 102281 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 128946 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 5081 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123865 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 128946 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 128946 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 5081 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123865 # number of overall misses system.cpu.l2cache.overall_misses::total 128946 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978063750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 363309000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614754750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1978063750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7455355000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7455355000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 7455355000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9433418750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 363309000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9070109750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 9433418750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9433418750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 363309000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9070109750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 9433418750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 98213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 44725 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53488 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 98213 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 128441 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128441 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107036 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 205249 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 44725 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160524 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 205249 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44725 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160524 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 205249 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113605 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403530 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.271502 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955576 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955576 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955576 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628242 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113605 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771629 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.628242 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628242 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113605 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771629 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.628242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74182.027002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71503.444204 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74812.581079 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72890.908380 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.908380 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -704,43 +728,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks system.cpu.l2cache.writebacks::total 83951 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26592 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5071 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123802 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 128873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 298810000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1336295500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6164329000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 298810000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7500624500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 298810000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7500624500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402352 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955576 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955576 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955576 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.627886 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.627886 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61488.624398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58925.261290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62092.630454 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60268.564054 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60268.564054 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 6bff9ac08..969dafec8 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=vortex lendian.raw cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index e7cd333d6..0dacf1436 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 1.199774 # Nu sim_ticks 1199774280000 # Number of ticks simulated final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 344306 # Simulator instruction rate (inst/s) -host_op_rate 344306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 226179780 # Simulator tick rate (ticks/s) -host_mem_usage 294788 # Number of bytes of host memory used -host_seconds 5304.52 # Real time elapsed on the host +host_inst_rate 216625 # Simulator instruction rate (inst/s) +host_op_rate 216625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 142303871 # Simulator tick rate (ticks/s) +host_mem_usage 282608 # Number of bytes of host memory used +host_seconds 8431.08 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125505984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125444608 # Number of bytes read from this memory system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960072 # Number of read requests responded to by this memory system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 51156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 104556840 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 104607997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 51156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 104556840 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1961031 # Number of read requests accepted system.physmem.writeReqs 1018242 # Number of write requests accepted @@ -342,8 +346,8 @@ system.cpu.dcache.tags.total_refs 601828569 # To system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.675710 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.675710 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id @@ -353,53 +357,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 443338834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 443338834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158489735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158489735 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 601828569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 601828569 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 601828569 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 601828569 # number of overall hits system.cpu.dcache.overall_hits::total 601828569 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289569 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 7289569 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2238767 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9528336 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 9528336 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9528336 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 9528336 # number of overall misses system.cpu.dcache.overall_misses::total 9528336 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 178039686000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 100958450500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 278998136500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 278998136500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 278998136500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 450628403 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 611356905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 611356905 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 611356905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611356905 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013929 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013929 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015586 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015586 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015586 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015586 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24423.897490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24423.897490 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45095.559520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45095.559520 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -411,45 +415,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks system.cpu.dcache.writebacks::total 3700624 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50811 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351432 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 351432 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 402243 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 402243 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 402243 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238758 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887335 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126093 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126093 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162083992000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75948494500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 238032486500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 238032486500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22391.132844 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40241.130748 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements @@ -543,9 +547,11 @@ system.cpu.l2cache.tags.sampled_refs 1958100 # Sa system.cpu.l2cache.tags.avg_refs 4.586953 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 89009074750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14951.890642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15804.919969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 43.293989 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15761.625979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.456295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482328 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001321 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.481007 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id @@ -556,57 +562,72 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15531 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106466843 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 106466843 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6058136 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6058136 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6058136 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3700624 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3700624 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107885 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107885 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7166021 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7166021 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7166021 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7166021 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7166021 # number of overall hits system.cpu.l2cache.overall_hits::total 7166021 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1180622 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1181581 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 779450 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 779450 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 779450 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1961031 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1960072 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 1961031 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1961031 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 959 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1960072 # number of overall misses system.cpu.l2cache.overall_misses::total 1961031 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94315348250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 67755750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94247592500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 94315348250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62933867000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 62933867000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 62933867000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 157249215250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 67755750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157181459500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 157249215250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 157249215250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 67755750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157181459500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 157249215250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239717 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 959 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7238758 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7239717 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3700624 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3700624 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887335 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887335 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1887335 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9127052 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9126093 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9127052 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9127052 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 959 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9126093 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9127052 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163097 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163208 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412990 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214859 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214777 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.214859 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214859 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214777 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70652.502607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79828.761873 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80741.377895 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -618,37 +639,49 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks system.cpu.l2cache.writebacks::total 1018242 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1180622 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 779450 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960072 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961031 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960072 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55699750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79417889000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53122771000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55699750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132540660000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55699750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132540660000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163097 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412990 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58081.074035 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67267.837631 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68154.174097 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index cfff7eb6d..deabb9ce1 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 1d6a1c5a9..1df40303a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 1.108725 # Nu sim_ticks 1108725388000 # Number of ticks simulated final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243193 # Simulator instruction rate (inst/s) -host_op_rate 262004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174570169 # Simulator tick rate (ticks/s) -host_mem_usage 311428 # Number of bytes of host memory used -host_seconds 6351.17 # Real time elapsed on the host +host_inst_rate 160331 # Simulator instruction rate (inst/s) +host_op_rate 172733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115089854 # Simulator tick rate (ticks/s) +host_mem_usage 301444 # Number of bytes of host memory used +host_seconds 9633.56 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131558336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2055599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 118657277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 2055599 # Number of read requests accepted system.physmem.writeReqs 1046417 # Number of write requests accepted @@ -423,8 +427,8 @@ system.cpu.dcache.tags.total_refs 624087400 # To system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.606596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id @@ -434,61 +438,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453740634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170346644 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 624087278 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 624087278 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits system.cpu.dcache.overall_hits::total 624087278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7337122 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2239403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9576525 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9576525 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses system.cpu.dcache.overall_misses::total 9576525 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183400270746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101399706750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 284799977496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 284799977496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633663803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633663803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24996.213876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45279.794101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -500,45 +504,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks system.cpu.dcache.writebacks::total 3701129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 221 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348484 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 348705 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9227820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77322111500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22940.075279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40891.286988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements @@ -633,9 +637,11 @@ system.cpu.l2cache.tags.sampled_refs 2052670 # Sa system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16254.854737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.862616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16227.992121 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.495239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id @@ -646,57 +652,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6082213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6082181 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090823 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1090823 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7173036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7173004 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7173036 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7173004 # number of overall hits system.cpu.l2cache.overall_hits::total 7173036 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1255508 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 788 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1254720 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1255508 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 800096 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 800096 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 800096 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2055604 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2054816 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 2055604 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2055604 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2054816 # number of overall misses system.cpu.l2cache.overall_misses::total 2055604 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100200408000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55257250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 100145150750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 100200408000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64467346000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64467346000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 64467346000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 164667754000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55257250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164612496750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 164667754000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 164667754000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 55257250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164612496750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 164667754000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337721 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7336901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7337721 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3701129 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3701129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890919 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890919 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1890919 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9228640 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9227820 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9228640 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9228640 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9227820 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9228640 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960976 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171015 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.171103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423125 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423125 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.423125 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222676 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222676 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79808.657531 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70123.413706 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79814.740141 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80574.513558 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80574.513558 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -708,43 +732,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks system.cpu.l2cache.writebacks::total 1046417 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254716 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800096 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2054812 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2054812 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45360250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84287306750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54391877500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45360250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138679184250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45360250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171014 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423125 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index d573e8898..67aea2f65 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 3a5076b7f..ae03186ae 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.052167 # Nu sim_ticks 52167245000 # Number of ticks simulated final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 368966 # Simulator instruction rate (inst/s) -host_op_rate 368966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209437459 # Simulator tick rate (ticks/s) -host_mem_usage 299464 # Number of bytes of host memory used -host_seconds 249.08 # Real time elapsed on the host +host_inst_rate 211928 # Simulator instruction rate (inst/s) +host_op_rate 211928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120297341 # Simulator tick rate (ticks/s) +host_mem_usage 286252 # Number of bytes of host memory used +host_seconds 433.65 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 340352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory system.physmem.bytes_read::total 340352 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 5318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6524247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs 26568138 # To system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700214 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.700214 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id @@ -318,53 +322,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20069946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 26568138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 26568138 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26568138 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 26568138 # number of overall hits system.cpu.dcache.overall_hits::total 26568138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2911 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37684500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37684500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 195045500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195045500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 232730000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 232730000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 232730000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 232730000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20070465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 26571568 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26571568 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 26571568 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26571568 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72609.826590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67002.919959 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67002.919959 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -376,45 +380,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 34 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1166 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1166 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1166 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 1200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1745 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34103500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34103500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117640500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117640500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151744000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151744000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151744000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70316.494845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70316.494845 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67415.759312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67415.759312 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements @@ -511,9 +515,11 @@ system.cpu.l2cache.tags.sampled_refs 3665 # Sa system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.053168 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 361.036043 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075136 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011018 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id @@ -524,57 +530,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111847 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 150786 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 150786 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12721 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 12668 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 12721 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12747 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 12668 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 12747 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12747 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 12668 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits system.cpu.l2cache.overall_hits::total 12747 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3599 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3167 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 432 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3599 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5318 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3167 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 5318 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5318 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3167 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 243859250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210776750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33082500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115635000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115635000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 359494250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210776750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 148717500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 359494250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210776750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 148717500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16320 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 18065 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15835 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 18065 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 18065 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15835 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 18065 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.220527 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890722 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.220527 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.294381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.294381 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67757.502084 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66554.073255 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76579.861111 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67268.760908 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67268.760908 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -584,37 +608,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 432 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 3599 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 170928750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27694500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93817500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170928750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121512000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170928750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121512000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.220527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53971.818756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64107.638889 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54576.788831 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 168018c03..ca02b53f3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index b930735f4..fa4a217dd 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -82,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -122,6 +123,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -171,6 +173,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -220,6 +223,7 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +drivers= egid=100 env= errout=cerr @@ -228,6 +232,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 75d7eb795..c2d632546 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.131746 # Nu sim_ticks 131745950000 # Number of ticks simulated final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246838 # Simulator instruction rate (inst/s) -host_op_rate 260207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188720644 # Simulator tick rate (ticks/s) -host_mem_usage 315756 # Number of bytes of host memory used -host_seconds 698.10 # Real time elapsed on the host +host_inst_rate 165378 # Simulator instruction rate (inst/s) +host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 126440065 # Simulator tick rate (ticks/s) +host_mem_usage 304748 # Number of bytes of host memory used +host_seconds 1041.96 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 247488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247488 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3867 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1878525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1878525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3867 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -390,8 +394,8 @@ system.cpu.dcache.tags.total_refs 40762987 # To system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772724 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id @@ -402,61 +406,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 28355530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 40718173 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 40718173 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits system.cpu.dcache.overall_hits::total 40718173 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 2436 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 2436 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115610250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 169622234 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 28356322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 40720609 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 40720609 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70322.536496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -468,45 +472,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 626 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 626 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1810 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47293264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76508500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123801764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69679.872495 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2909 # number of replacements @@ -603,9 +607,11 @@ system.cpu.l2cache.tags.sampled_refs 2785 # Sa system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491287 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id @@ -616,57 +622,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2631 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2543 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2631 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2543 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits system.cpu.l2cache.overall_hits::total 2631 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2795 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 2163 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3885 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2163 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 2163 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191684250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145907500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45776750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 75329000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 267013250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 145907500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 121105750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 267013250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 145907500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 121105750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4706 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6516 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6516 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4706 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.515873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459626 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68581.127013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69109.174312 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -676,43 +700,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155790000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61501500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217291500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217291500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution |