stats: arm: updates

22 files changed, 8807 insertions, 8803 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index bce6e86b0..4eaa033e0 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061589                       # Number of seconds simulated
-sim_ticks                                 61589191500                       # Number of ticks simulated
-final_tick                                61589191500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061594                       # Number of seconds simulated
+sim_ticks                                 61594138500                       # Number of ticks simulated
+final_tick                                61594138500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 169101                       # Simulator instruction rate (inst/s)
-host_op_rate                                   169943                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              114949938                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 374724                       # Number of bytes of host memory used
-host_seconds                                   535.79                       # Real time elapsed on the host
-sim_insts                                    90602849                       # Number of instructions simulated
-sim_ops                                      91054080                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 196979                       # Simulator instruction rate (inst/s)
+host_op_rate                                   197960                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              133911114                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 438496                       # Number of bytes of host memory used
+host_seconds                                   459.96                       # Real time elapsed on the host
+sim_insts                                    90602850                       # Number of instructions simulated
+sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             49600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             49536                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947200                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               996800                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        49600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           49600                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                775                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        49536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           49536                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                774                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14800                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15575                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               805336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             15379322                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16184658                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          805336                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             805336                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              805336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            15379322                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               16184658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15575                       # Number of read requests accepted
+system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst               804232                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             15378087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16182319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          804232                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             804232                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              804232                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            15378087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               16182319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15574                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       15575                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   996800                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   996736                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    996800                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    996736                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -47,7 +47,7 @@ system.physmem.perBankRdBursts::2                 949                       # Pe
 system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1113                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1088                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1087                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1088                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61589097000                       # Total gap between requests
+system.physmem.totGap                     61594044000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15575                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15574                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,7 +90,7 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     15454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     15453                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       111                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1548                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      642.728682                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     437.613794                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     401.141843                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            250     16.15%     16.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          184     11.89%     28.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           91      5.88%     33.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           69      4.46%     38.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           77      4.97%     43.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           93      6.01%     49.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           43      2.78%     52.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           36      2.33%     54.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          705     45.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1548                       # Bytes accessed per row activation
-system.physmem.totQLat                       76265750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 368297000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     77875000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4896.68                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1540                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      646.025974                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     441.784218                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     399.527843                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            247     16.04%     16.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          180     11.69%     27.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           88      5.71%     33.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           68      4.42%     37.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           78      5.06%     42.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           95      6.17%     49.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           49      3.18%     52.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           35      2.27%     54.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          700     45.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1540                       # Bytes accessed per row activation
+system.physmem.totQLat                       76216750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 368229250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4893.85                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23646.68                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23643.85                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          16.18                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       16.18                       # Average system read bandwidth in MiByte/s
@@ -216,48 +216,48 @@ system.physmem.busUtilRead                       0.13                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14017                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14024                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.00                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   90.05                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3954356.15                       # Average gap between requests
-system.physmem.pageHitRate                      90.00                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6365520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3473250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  63663600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      3954927.70                       # Average gap between requests
+system.physmem.pageHitRate                      90.05                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6327720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3452625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  63655800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4022201040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2552305815                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34710162000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41358171225                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.598278                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57736612750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2056340000                       # Time in different power states
+system.physmem_0.refreshEnergy             4022709600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2561139675                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34707076500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41364361920                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.614039                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57728641000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2056600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1792195250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1804854500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5322240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2904000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                    5299560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2891625                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                  57462600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4022201040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2572075980                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34692811500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41352777360                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.510839                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57709022500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2056340000                       # Time in different power states
+system.physmem_1.refreshEnergy             4022709600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2570808870                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34698594750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41357767005                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.506960                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57715756250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2056600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1820633500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1818578750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20789992                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17092121                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            765794                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8976081                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 8866607                       # Number of BTB hits
+system.cpu.branchPred.lookups                20791997                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17093861                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            766355                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8982065                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8866075                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.780381                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   62695                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             98.708649                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   62635                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,67 +377,67 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        123178383                       # number of cpu cycles simulated
+system.cpu.numCycles                        123188277                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    90602849                       # Number of instructions committed
-system.cpu.committedOps                      91054080                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2068275                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                    90602850                       # Number of instructions committed
+system.cpu.committedOps                      91054081                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2070154                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.359542                       # CPI: cycles per instruction
-system.cpu.ipc                               0.735542                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109824698                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        13353685                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            946107                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3616.117477                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26267654                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            950203                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.644255                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20661192250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3616.117477                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.882841                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.882841                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.359651                       # CPI: cycles per instruction
+system.cpu.ipc                               0.735483                       # IPC: instructions per cycle
+system.cpu.tickCycles                       109833647                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13354630                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            946088                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3616.165317                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26267708                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            950184                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             27.644865                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20660513250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3616.165317                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.882853                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.882853                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          260                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1         2243                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         1593                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55463725                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55463725                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21598560                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21598560                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4660812                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4660812                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          55463792                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55463792                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21598607                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21598607                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4660819                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4660819                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          508                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           508                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26259372                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26259372                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26259880                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26259880                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       914934                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        914934                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        74169                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        74169                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      26259426                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26259426                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26259934                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26259934                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       914930                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        914930                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        74162                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        74162                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            4                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            4                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       989103                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         989103                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       989107                       # number of overall misses
-system.cpu.dcache.overall_misses::total        989107                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11918328994                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11918328994                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2566867500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2566867500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14485196494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14485196494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14485196494                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14485196494                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22513494                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22513494                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       989092                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         989092                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       989096                       # number of overall misses
+system.cpu.dcache.overall_misses::total        989096                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11918229494                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11918229494                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2567046500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2567046500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14485275994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14485275994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14485275994                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14485275994                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22513537                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22513537                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          512                       # number of SoftPFReq accesses(hits+misses)
@@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27248475                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27248475                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27248987                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27248987                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     27248518                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27248518                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27249030                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27249030                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040639                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.040639                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015664                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015664                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015663                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015663                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.036299                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.036299                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036299                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036299                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.435780                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.435780                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34608.360636                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34608.360636                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.780669                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14644.780669                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.721445                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14644.721445                       # average overall miss latency
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036298                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036298                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14645.023915                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14644.964689                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       943285                       # number of writebacks
-system.cpu.dcache.writebacks::total            943285                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11501                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        11501                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27402                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27402                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        38903                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        38903                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        38903                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        38903                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903433                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903433                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46767                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46767                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       943266                       # number of writebacks
+system.cpu.dcache.writebacks::total            943266                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11513                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        11513                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27398                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27398                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        38911                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        38911                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        38911                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        38911                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903417                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903417                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46764                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46764                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       950200                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       950200                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       950203                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       950203                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10413180006                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10413180006                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1463830500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1463830500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       950181                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       950181                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       950184                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       950184                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10412913006                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10412913006                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1464006500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1464006500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       155500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       155500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11877010506                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11877010506                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11877166006                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11877166006                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040129                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040129                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009877                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009877                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11876919506                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11876919506                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11877075006                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11877075006                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040128                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040128                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009876                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005859                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005859                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034872                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034872                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034871                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034871                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.233828                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.233828                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31300.500353                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31300.500353                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034871                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034871                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034870                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034870                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.484852                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.484852                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.609037                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.609037                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.tagsinuse           690.367878                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27855563                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               803                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          34689.368618                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                 4                       # number of replacements
+system.cpu.icache.tags.tagsinuse           690.351832                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27857021                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34734.440150                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   690.367878                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.337094                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.337094                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   690.351832                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.337086                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.337086                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          798                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          741                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.389648                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55713535                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55713535                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27855563                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27855563                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27855563                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27855563                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27855563                       # number of overall hits
-system.cpu.icache.overall_hits::total        27855563                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          803                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           803                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          803                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            803                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          803                       # number of overall misses
-system.cpu.icache.overall_misses::total           803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     60778747                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     60778747                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     60778747                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     60778747                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     60778747                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     60778747                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27856366                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27856366                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27856366                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27856366                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27856366                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27856366                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          55716448                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55716448                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27857021                       # number of ReadReq hits
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
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 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75689.597758                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75689.597758                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75689.597758                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75689.597758                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75689.597758                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75689.597758                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75457.602244                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75457.602244                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -587,123 +587,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          803                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73771.797011                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73771.797011                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73771.797011                       # average overall mshr miss latency
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73771.797011                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10238.331530                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1831333                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15558                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           117.710053                       # Average number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs           117.715369                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9347.552494                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   675.372759                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74772.814910                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73994.191544                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74033.062757                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.016386                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -721,104 +721,104 @@ system.cpu.l2cache.demand_mshr_hits::total            9                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            6                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            9                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          775                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          774                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          256                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1031                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1030                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14544                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14544                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          775                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          774                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        14800                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15575                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          775                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15574                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          774                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14800                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15575                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     48299750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     18668000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     66967750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    891481000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    891481000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     48299750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    910149000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    958448750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     48299750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    910149000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    958448750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965131                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     48052500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     18582500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     66635000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    891707750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    891707750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     48052500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    910290250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    958342750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     48052500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    910290250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    958342750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000283                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001140                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.310989                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.310989                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965131                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001139                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965131                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62322.258065                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72921.875000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64954.170708                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61295.448295                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61295.448295                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62322.258065                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61496.554054                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61537.640449                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62322.258065                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61496.554054                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61537.640449                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         904239                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        904239                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       943285                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46767                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46767                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1606                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843691                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2845297                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121183232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          121234624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq         904222                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        904222                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       943266                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        46764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        46764                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1604                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843634                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2845238                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121180800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          121232128                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1894291                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      1894252                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            1894291    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            1894252    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1894291                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1890430500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1894252                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1890392000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1372247                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1371497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1428681994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1428656494                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                1031                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1031                       # Transaction distribution
+system.membus.trans_dist::ReadReq                1030                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31150                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31150                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  996800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31148                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31148                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  996736                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             15575                       # Request fanout histogram
+system.membus.snoop_fanout::samples             15574                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   15575    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   15574    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               15575                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21630500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               15574                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            21629000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           82148250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           82142750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 7cd5a5ef6..a297b8e5d 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,111 +1,111 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.058203                       # Number of seconds simulated
-sim_ticks                                 58202727500                       # Number of ticks simulated
-final_tick                                58202727500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                 58203290500                       # Number of ticks simulated
+final_tick                                58203290500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 129301                       # Simulator instruction rate (inst/s)
-host_op_rate                                   129945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               83074382                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 373768                       # Number of bytes of host memory used
-host_seconds                                   700.61                       # Real time elapsed on the host
-sim_insts                                    90589798                       # Number of instructions simulated
-sim_ops                                      91041029                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  98982                       # Simulator instruction rate (inst/s)
+host_op_rate                                    99475                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63595388                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 438244                       # Number of bytes of host memory used
+host_seconds                                   915.21                       # Real time elapsed on the host
+sim_insts                                    90589799                       # Number of instructions simulated
+sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             44480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             45376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       930112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1019968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        44480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           44480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        22912                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             22912                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                695                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                709                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        14533                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15937                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             358                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  358                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               764225                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               779620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     15980557                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17524402                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          764225                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             764225                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            393659                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 393659                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            393659                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              764225                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              779620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     15980557                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17918061                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15937                       # Number of read requests accepted
-system.physmem.writeReqs                          358                       # Number of write requests accepted
-system.physmem.readBursts                       15937                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        358                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1010432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9536                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     21184                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1019968                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  22912                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      149                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             44544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             48256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       930624                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1023424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        25536                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             25536                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                696                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                754                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        14541                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15991                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             399                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  399                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               765318                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               829094                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     15989199                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                17583611                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          765318                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             765318                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            438738                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 438738                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            438738                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              765318                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              829094                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     15989199                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18022349                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15991                       # Number of read requests accepted
+system.physmem.writeReqs                          399                       # Number of write requests accepted
+system.physmem.readBursts                       15991                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        399                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1010944                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12480                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     24064                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1023424                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  25536                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      195                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       3                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1009                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1015                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 876                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 958                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1024                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1064                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1132                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1124                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1103                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1046                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 963                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1023                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1065                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1139                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1118                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1101                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1044                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                937                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                939                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                909                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                889                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                926                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                930                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  30                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                905                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                898                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                928                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                921                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  32                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   8                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   1                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                  29                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  69                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                  31                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                  16                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   9                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                  45                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  72                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                  35                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                  36                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  7                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  7                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                 27                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                 45                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                 31                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                 13                       # Per bank write bursts
+system.physmem.perBankWrBursts::11                  2                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  5                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                 37                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                 47                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                 27                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58202569500                       # Total gap between requests
+system.physmem.totGap                     58203132500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15937                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15991                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    358                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10945                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2405                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       522                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       349                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       310                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    399                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     10953                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2399                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       519                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       359                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       309                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                       297                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                       305                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                       289                       # What read queue length does an incoming req see
@@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                       21                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -197,93 +197,93 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1871                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      551.268840                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     315.885566                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     433.770323                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            552     29.50%     29.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          218     11.65%     41.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           92      4.92%     46.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           57      3.05%     49.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           63      3.37%     52.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           44      2.35%     54.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           55      2.94%     57.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           42      2.24%     60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          748     39.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1871                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples            18                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       874.777778                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       39.760140                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     3541.219224                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511              17     94.44%     94.44% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      5.56%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total              18                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples            18                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.388889                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.356746                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.195033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 15     83.33%     83.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  2     11.11%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      5.56%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total              18                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      172783990                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 468808990                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     78940000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10944.01                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1905                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      542.975328                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     308.892213                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     434.261771                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            566     29.71%     29.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          241     12.65%     42.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           93      4.88%     47.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           55      2.89%     50.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           58      3.04%     53.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           46      2.41%     55.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           56      2.94%     58.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           43      2.26%     60.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          747     39.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1905                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples            21                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       751.047619                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       33.268614                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     3285.704681                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511              20     95.24%     95.24% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            1      4.76%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total              21                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples            21                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.904762                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.888741                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.768424                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  2      9.52%      9.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 18     85.71%     95.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      4.76%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total              21                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      171453784                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 467628784                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     78980000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10854.25                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29694.01                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          17.36                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.36                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       17.52                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.39                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29604.25                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          17.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.41                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       17.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.44                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        16.15                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14154                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        93                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.65                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  26.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3571805.43                       # Average gap between requests
-system.physmem.pageHitRate                      88.25                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    7658280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    4178625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  64638600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                  1153440                       # Energy for write commands per rank (pJ)
+system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        19.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      14158                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       107                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.63                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  27.02                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3551136.82                       # Average gap between requests
+system.physmem.pageHitRate                      88.10                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    7854840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    4285875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  64662000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                  1354320                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             3801486000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2451888630                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            32770707750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              39101711325                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.822097                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    54506616189                       # Time in different power states
+system.physmem_0.actBackEnergy             2465906355                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            32758411500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              39103960890                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.860748                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    54486158959                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      1943500000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1752376311                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1772833541                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6486480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3539250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  58484400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                   991440                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                    6546960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3572250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  58468800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                  1082160                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             3801486000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2431326735                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            32788744500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              39091058805                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.639072                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    54537138662                       # Time in different power states
+system.physmem_1.actBackEnergy             2423272635                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            32795809500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              39090238305                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.624974                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    54548877915                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      1943500000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1721853838                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1710114585                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                28259323                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23281308                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                28259243                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23281231                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            837964                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11850778                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11785443                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             11853879                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11785418                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.448686                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   75758                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             99.422459                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   75772                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 89                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -403,83 +403,83 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        116405456                       # number of cpu cycles simulated
+system.cpu.numCycles                        116406582                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles             749294                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      134993998                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28259323                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11861201                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     114761716                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1679249                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1000                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          840                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  32304088                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   579                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116352474                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.165469                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.319047                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles             748963                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      134993544                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28259243                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11861190                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     114762985                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1679231                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  934                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          807                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  32304048                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   578                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          116353304                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.165458                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.319046                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58780581     50.52%     50.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 13944559     11.98%     62.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9221403      7.93%     70.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34405931     29.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58781536     50.52%     50.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13944543     11.98%     62.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9221339      7.93%     70.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34405886     29.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116352474                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.242766                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.159688                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8844184                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64087377                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  33032699                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9560836                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 827378                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4101289                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12349                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              114434840                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               1995518                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 827378                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15306554                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                49837632                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         110028                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35408205                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14862677                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110902804                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1415247                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              11133046                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1143083                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1515709                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 570063                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           129962368                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483290389                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        119478713                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               424                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            116353304                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.242763                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.159673                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8844047                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64088450                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  33032847                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9560591                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 827369                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4101287                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12347                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              114434695                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               1995559                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 827369                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15306268                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                49839660                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         109196                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35408210                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14862601                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110902627                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1415209                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              11132813                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1143128                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1515839                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 570040                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           129962079                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             483289738                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        119478423                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               422                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22649449                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 22649160                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts               4363                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           4358                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  21572068                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26814283                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5349560                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads            615072                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           351208                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  109694902                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  21571738                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26814245                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5349583                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            611820                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           348925                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  109694682                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                8246                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 101389982                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1073881                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18662119                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41703174                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 101389793                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1073874                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18661898                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41702987                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             28                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116352474                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.871404                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.988585                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     116353304                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.871396                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.988581                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            54656656     46.98%     46.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            31447896     27.03%     74.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            21997479     18.91%     92.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7054961      6.06%     98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1195165      1.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54657362     46.98%     46.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            31448211     27.03%     74.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            21997386     18.91%     92.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7054887      6.06%     98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1195141      1.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                 317      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -487,9 +487,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116352474                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116353304                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9796147     48.71%     48.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9796132     48.71%     48.71% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     50      0.00%     48.71% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.71% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.71% # attempts to use FU when none available
@@ -518,12 +518,12 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.71% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.71% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.71% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9605529     47.77%     96.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                708223      3.52%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9605412     47.76%     96.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                708293      3.52%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              71985557     71.00%     71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              71985396     71.00%     71.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                10710      0.01%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
@@ -546,102 +546,102 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              58      0.00%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              56      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc            123      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24344215     24.01%     95.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5049315      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24344165     24.01%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5049339      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              101389982                       # Type of FU issued
-system.cpu.iq.rate                           0.871007                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20109961                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.198343                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          340315821                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128365920                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     99626078                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 459                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                614                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          115                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              121499704                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     239                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           282708                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              101389793                       # Type of FU issued
+system.cpu.iq.rate                           0.870997                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    20109899                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.198342                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          340316208                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128365476                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     99625945                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 455                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                608                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          113                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              121499455                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     237                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           282715                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4338372                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1511                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         1302                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       604716                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4338334                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1512                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         1293                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       604739                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7561                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        130367                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         7563                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        130432                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 827378                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8117043                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                661508                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           109715814                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 827369                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8116840                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                661308                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           109715594                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26814283                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5349560                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts              26814245                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5349583                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts               4358                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 178487                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                319637                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           1302                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         436579                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       412967                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               849546                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             100128293                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23807365                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1261689                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                 178503                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                319361                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           1293                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         436568                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412973                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               849541                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             100128175                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23807340                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1261618                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                         12666                       # number of nop insts executed
-system.cpu.iew.exec_refs                     28725194                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 20624883                       # Number of branches executed
-system.cpu.iew.exec_stores                    4917829                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.860168                       # Inst execution rate
-system.cpu.iew.wb_sent                       99711182                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      99626193                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  59706016                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95562461                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     28725211                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 20624854                       # Number of branches executed
+system.cpu.iew.exec_stores                    4917871                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.860159                       # Inst execution rate
+system.cpu.iew.wb_sent                       99711063                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99626058                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59706030                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95562635                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.855855                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.624785                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.855846                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.624784                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        17390136                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        17389920                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            825718                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    113659456                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.801109                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.737097                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    113660326                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.801103                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.737104                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     77211009     67.93%     67.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18641585     16.40%     84.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      7152887      6.29%     90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3463018      3.05%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1652627      1.45%     95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       524640      0.46%     95.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       723684      0.64%     96.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       178635      0.16%     96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4111371      3.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     77212273     67.93%     67.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18641375     16.40%     84.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      7152706      6.29%     90.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3462873      3.05%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1652643      1.45%     95.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       524647      0.46%     95.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       723706      0.64%     96.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       178634      0.16%     96.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4111469      3.62%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    113659456                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             90602407                       # Number of instructions committed
-system.cpu.commit.committedOps               91053638                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    113660326                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
+system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       27220755                       # Number of memory references committed
 system.cpu.commit.loads                      22475911                       # Number of loads committed
 system.cpu.commit.membars                        3888                       # Number of memory barriers committed
-system.cpu.commit.branches                   18732304                       # Number of branches committed
+system.cpu.commit.branches                   18732305                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  72326352                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                56148                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         63822386     70.09%     70.09% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         63822387     70.09%     70.09% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult           10474      0.01%     70.10% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.10% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     70.10% # Class of committed instruction
@@ -674,79 +674,79 @@ system.cpu.commit.op_class_0::MemRead        22475911     24.68%     94.79% # Cl
 system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          91053638                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               4111371                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    217986125                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219581178                       # The number of ROB writes
-system.cpu.timesIdled                             584                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           52982                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    90589798                       # Number of Instructions Simulated
-system.cpu.committedOps                      91041029                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.284973                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.284973                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.778226                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.778226                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108112973                       # number of integer regfile reads
-system.cpu.int_regfile_writes                58701982                       # number of integer regfile writes
+system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               4111469                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    217986682                       # The number of ROB reads
+system.cpu.rob.rob_writes                   219580711                       # The number of ROB writes
+system.cpu.timesIdled                             588                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           53278                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
+system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.284986                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.284986                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.778219                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.778219                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                108112805                       # number of integer regfile reads
+system.cpu.int_regfile_writes                58701882                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       95                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 369069288                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 58692619                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28415446                       # number of misc regfile reads
+system.cpu.fp_regfile_writes                       93                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 369068913                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 58692415                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                28415527                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           5469543                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.788616                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18297454                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           5470055                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              3.345022                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          35157000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.788616                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999587                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999587                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           5469565                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.787779                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18297385                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           5470077                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              3.344996                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          35255000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.787779                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999586                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999586                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          342                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          341                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          61924995                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         61924995                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13934183                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13934183                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4354974                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4354974                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          61924887                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         61924887                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13934133                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13934133                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4354955                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4354955                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      18289157                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18289157                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18289679                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18289679                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9550003                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9550003                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       380007                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       380007                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      18289088                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18289088                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18289610                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18289610                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9549988                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9549988                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       380026                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       380026                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      9930010                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9930010                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9930017                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9930017                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  88443276736                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  88443276736                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3962066244                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3962066244                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      9930014                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9930014                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9930021                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9930021                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  88444420972                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  88444420972                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3962617493                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3962617493                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       297000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       297000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92405342980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92405342980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92405342980                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92405342980                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23484186                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23484186                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  92407038465                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  92407038465                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  92407038465                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  92407038465                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23484121                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23484121                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
@@ -755,302 +755,302 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28219167                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28219167                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28219696                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28219696                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     28219102                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28219102                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28219631                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28219631                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.406657                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.406657                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080255                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080255                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080259                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080259                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.351889                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.351889                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.351882                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.351882                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9261.073189                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9261.073189                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.351890                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.351890                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.351883                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.351883                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9261.207550                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9261.207550                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10427.227329                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10427.227329                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        19800                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        19800                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9305.664645                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9305.664645                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9305.658085                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9305.658085                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       306020                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        36082                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            120709                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9305.831640                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9305.831640                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9305.825080                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9305.825080                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       306116                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        36058                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            120736                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets            2278                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.535188                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    15.839333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.535416                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    15.828797                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      5439051                       # number of writebacks
-system.cpu.dcache.writebacks::total           5439051                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4313021                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4313021                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       146936                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       146936                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      5437967                       # number of writebacks
+system.cpu.dcache.writebacks::total           5437967                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4312992                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4312992                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       146947                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       146947                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4459957                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4459957                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4459957                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4459957                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5236982                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5236982                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       233071                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       233071                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4459939                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4459939                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4459939                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4459939                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5236996                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5236996                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       233079                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       233079                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      5470053                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      5470053                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      5470057                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      5470057                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  40519086258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  40519086258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2295163471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2295163471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      5470075                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      5470075                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      5470079                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      5470079                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  40520727758                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  40520727758                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2294964437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2294964437                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       213000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       213000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  42814249729                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  42814249729                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  42814462729                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  42814462729                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223000                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223000                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049223                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049223                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  42815692195                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  42815692195                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  42815905195                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  42815905195                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223002                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223002                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049225                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049225                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193842                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.193842                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193838                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.193838                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7737.106268                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7737.106268                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9847.486264                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9847.486264                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193843                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.193843                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193839                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.193839                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7737.399028                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7737.399028                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9846.294334                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9846.294334                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53250                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53250                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7827.026489                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  7827.026489                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7827.059705                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  7827.059705                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7827.258711                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  7827.258711                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7827.291927                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  7827.291927                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               451                       # number of replacements
-system.cpu.icache.tags.tagsinuse           428.263511                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            32302915                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               910                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          35497.708791                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               449                       # number of replacements
+system.cpu.icache.tags.tagsinuse           428.262881                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            32302878                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               908                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          35575.856828                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   428.263511                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.836452                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.836452                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   428.262881                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.836451                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.836451                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           21                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          332                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.896484                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          64609056                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         64609056                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     32302915                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        32302915                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      32302915                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         32302915                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     32302915                       # number of overall hits
-system.cpu.icache.overall_hits::total        32302915                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1158                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1158                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1158                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1158                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1158                       # number of overall misses
-system.cpu.icache.overall_misses::total          1158                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62669987                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62669987                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62669987                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62669987                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62669987                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62669987                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     32304073                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     32304073                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     32304073                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     32304073                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     32304073                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     32304073                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          64608978                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         64608978                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     32302878                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        32302878                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      32302878                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         32302878                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     32302878                       # number of overall hits
+system.cpu.icache.overall_hits::total        32302878                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1157                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1157                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1157                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1157                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1157                       # number of overall misses
+system.cpu.icache.overall_misses::total          1157                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62067238                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62067238                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62067238                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62067238                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62067238                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62067238                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     32304035                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     32304035                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     32304035                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     32304035                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     32304035                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     32304035                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54119.159758                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54119.159758                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54119.159758                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54119.159758                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54119.159758                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        19414                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53644.976664                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53644.976664                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53644.976664                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53644.976664                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53644.976664                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53644.976664                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        18268                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets          134                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               238                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               226                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    81.571429                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    80.831858                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    26.800000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          248                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          248                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          248                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          248                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          248                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          248                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          910                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          910                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          910                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50368733                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50368733                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50368733                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50368733                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50368733                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50368733                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          249                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          249                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          249                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          249                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          249                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          249                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          908                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          908                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          908                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          908                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     49773732                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     49773732                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     49773732                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     49773732                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     49773732                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     49773732                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55350.256044                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55350.256044                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55350.256044                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 55350.256044                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55350.256044                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 55350.256044                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54816.885463                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54816.885463                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54816.885463                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54816.885463                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54816.885463                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54816.885463                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      4495585                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      5292074                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       687825                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      4492873                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      5289387                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       687833                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage     14072766                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements              493                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        12074.856330                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           10653372                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15934                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           668.593699                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage     14073797                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements              562                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        12069.997275                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           10652240                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15999                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           665.806613                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11119.543661                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   571.365929                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   202.646634                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   181.300106                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.678683                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.034873                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.012369                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.011066                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.736991                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          216                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15225                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           13                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          191                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          974                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1048                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13130                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.013184                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.929260                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        174809424                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       174809424                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst          213                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      5236439                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        5236652                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      5439051                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      5439051                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       232688                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       232688                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          213                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      5469127                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         5469340                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          213                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      5469127                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        5469340                       # number of overall hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 11108.777118                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   571.857159                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   208.039641                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   181.323358                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.678026                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.034903                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.012698                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.011067                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15200                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3            6                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          190                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          976                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1058                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13088                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.014465                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.927734                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        174792474                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       174792474                       # Number of data accesses
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+system.cpu.l2cache.ReadReq_hits::total        5236612                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      5437967                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      5437967                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       232700                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       232700                       # number of ReadExReq hits
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+system.cpu.l2cache.demand_hits::cpu.data      5469101                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.inst          211                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      5469101                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        5469312                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst          697                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          416                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1113                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          467                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1164                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          512                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          512                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          509                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          509                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          697                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          928                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          1625                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          976                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.inst          697                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          928                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         1625                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     48506493                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     26932750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     75439243                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     29111250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     77037243                       # number of ReadReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        46498                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total        46498                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     37042063                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     37042063                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     48506493                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     63974813                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    112481306                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     48506493                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     63974813                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    112481306                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          910                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      5236855                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      5237765                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      5439051                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      5439051                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     36405063                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     36405063                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data     65516313                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    113442306                       # number of overall miss cycles
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+system.cpu.l2cache.ReadReq_accesses::cpu.data      5236868                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      5237776                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      5437967                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      5437967                       # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.inst          910                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      5470055                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      5470965                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          910                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      5470055                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      5470965                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.765934                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000079                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000212                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.demand_accesses::cpu.data      5470077                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.inst          908                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      5470077                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      5470985                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.767621                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000089                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000222                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002196                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.002196                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.765934                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.000170                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.000297                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.765934                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.000170                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.000297                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69593.246772                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64742.187500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67780.092543                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002183                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.002183                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.767621                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.000178                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.000306                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.767621                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.000178                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.000306                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68760.391679                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62336.723769                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 66183.198454                       # average ReadReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        23249                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        23249                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72347.779297                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72347.779297                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69593.246772                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68938.376078                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69219.265231                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69593.246772                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68938.376078                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69219.265231                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71522.717092                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71522.717092                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68760.391679                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67127.369877                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67807.714286                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68760.391679                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67127.369877                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67807.714286                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1059,146 +1059,146 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          358                       # number of writebacks
-system.cpu.l2cache.writebacks::total              358                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           48                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           50                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          171                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total          171                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          219                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          221                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          219                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          221                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          695                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          368                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1063                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        20246                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        20246                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks          399                       # number of writebacks
+system.cpu.l2cache.writebacks::total              399                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           52                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           53                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          170                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total          170                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          222                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          223                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          222                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          223                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          696                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          415                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1111                       # number of ReadReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        20227                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        20227                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          341                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          341                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          695                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          709                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         1404                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          695                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          709                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        20246                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        21650                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     42518507                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     21103750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     63622257                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    830590289                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    830590289                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          339                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          339                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          696                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          754                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         1450                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          696                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          754                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        20227                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        21677                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     41955257                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     23172750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     65128007                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    829862007                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    829862007                       # number of HardPFReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        27502                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        27502                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     25988008                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     25988008                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     42518507                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     47091758                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     89610265                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     42518507                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     47091758                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    830590289                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    920200554                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000070                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000203                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     25379758                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     25379758                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     41955257                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     48552508                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     90507765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     41955257                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     48552508                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    829862007                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    920369772                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.766520                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000079                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000212                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001462                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001462                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000130                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.000257                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000130                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001454                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001454                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.766520                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000138                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.000265                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.766520                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000138                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.003957                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.003962                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60280.541667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55837.951807                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58621.068407                       # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41027.438918                       # average HardPFReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        13751                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        13751                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74866.542773                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74866.542773                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60280.541667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64393.246684                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62419.148276                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60280.541667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64393.246684                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42458.355492                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        5237765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       5237765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      5439051                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        22132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        5237776                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       5237776                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      5437967                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        22114                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       233200                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       233200                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1820                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16379167                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16380987                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    698182912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          698241152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       22134                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     10932150                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.002024                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.044949                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       233209                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       233209                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1816                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16378127                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16379943                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    698114944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          698173056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       22116                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     10931068                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.002023                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.044933                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3           10910018     99.80%     99.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              22132      0.20%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3           10908954     99.80%     99.80% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              22114      0.20%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       10932150                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10894060998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       10931068                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10892444998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization         18.7                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy         3000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1497004                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1495005                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    8205133181                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    8205165681                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               15596                       # Transaction distribution
-system.membus.trans_dist::ReadResp              15596                       # Transaction distribution
-system.membus.trans_dist::Writeback               358                       # Transaction distribution
+system.membus.trans_dist::ReadReq               15652                       # Transaction distribution
+system.membus.trans_dist::ReadResp              15652                       # Transaction distribution
+system.membus.trans_dist::Writeback               399                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               341                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              341                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32236                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  32236                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1042880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1042880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               339                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              339                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32385                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  32385                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1048960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1048960                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             16297                       # Request fanout histogram
+system.membus.snoop_fanout::samples             16392                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   16297    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   16392    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               16297                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            26854780                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               16392                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            27168735                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           83365318                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           83645045                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 409fcf8a5..e29c8c27b 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.366358                       # Number of seconds simulated
-sim_ticks                                366358475500                       # Number of ticks simulated
-final_tick                               366358475500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.366340                       # Number of seconds simulated
+sim_ticks                                366339500500                       # Number of ticks simulated
+final_tick                               366339500500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 156500                       # Simulator instruction rate (inst/s)
-host_op_rate                                   169511                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              113180486                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245616                       # Number of bytes of host memory used
-host_seconds                                  3236.94                       # Real time elapsed on the host
-sim_insts                                   506582155                       # Number of instructions simulated
-sim_ops                                     548695378                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 174606                       # Simulator instruction rate (inst/s)
+host_op_rate                                   189122                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              126268215                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309684                       # Number of bytes of host memory used
+host_seconds                                  2901.28                       # Real time elapsed on the host
+sim_insts                                   506582156                       # Number of instructions simulated
+sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9004224                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9225920                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6180352                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6180352                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3464                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140691                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                144155                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96568                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                96568                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               605134                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24577633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25182767                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          605134                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             605134                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          16869685                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               16869685                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          16869685                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              605134                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24577633                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42052451                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        144155                       # Number of read requests accepted
-system.physmem.writeReqs                        96568                       # Number of write requests accepted
-system.physmem.readBursts                      144155                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      96568                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9218240                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6178944                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9225920                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6180352                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            222208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9004736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9226944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       222208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          222208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6180224                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6180224                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3472                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140699                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                144171                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96566                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                96566                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               606563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24580303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25186866                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          606563                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             606563                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          16870209                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               16870209                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          16870209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              606563                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24580303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42057075                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        144171                       # Number of read requests accepted
+system.physmem.writeReqs                        96566                       # Number of write requests accepted
+system.physmem.readBursts                      144171                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      96566                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9220288                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6179072                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9226944                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6180224                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9365                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8967                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8978                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8700                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9448                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9342                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8938                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9343                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8971                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8989                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8699                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9456                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9348                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8947                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                8105                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                8575                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8679                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8682                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               8775                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9474                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9378                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9522                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8708                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9081                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6205                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6092                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9479                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9376                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9525                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8707                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9090                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6188                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6094                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                6005                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5814                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6161                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6174                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6162                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6175                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6015                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                5497                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5724                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5730                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                5822                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5961                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6444                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6310                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6277                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5996                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6049                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5962                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6449                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6307                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6278                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5993                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6057                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    366358446500                       # Total gap between requests
+system.physmem.totGap                    366339471500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  144155                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  144171                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  96568                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143662                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       351                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  96566                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143694                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       352                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5660                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
@@ -193,112 +193,113 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65262                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.919953                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.506308                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.385533                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24794     37.99%     37.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18171     27.84%     65.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7030     10.77%     76.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7953     12.19%     88.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2052      3.14%     91.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1171      1.79%     93.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          739      1.13%     94.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          589      0.90%     95.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2763      4.23%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65262                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5572                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.848887                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      382.035418                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5569     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65255                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.982530                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     156.409511                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.771416                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24814     38.03%     38.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18186     27.87%     65.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6968     10.68%     76.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7930     12.15%     88.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2060      3.16%     91.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1157      1.77%     93.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          782      1.20%     94.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          601      0.92%     95.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2757      4.22%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65255                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5574                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.846071                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      382.003663                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5571     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.04%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5572                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5572                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.326992                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.223724                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.446858                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2657     47.68%     47.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            2761     49.55%     97.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              56      1.01%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              29      0.52%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              20      0.36%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              10      0.18%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               6      0.11%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               7      0.13%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               5      0.09%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               2      0.04%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               5      0.09%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39               2      0.04%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41               2      0.04%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               2      0.04%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47               1      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               2      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5574                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5574                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.321134                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.221070                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.354740                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2655     47.63%     47.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            2759     49.50%     97.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              73      1.31%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              16      0.29%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              14      0.25%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              15      0.27%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               8      0.14%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               5      0.09%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               9      0.16%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               6      0.11%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39               2      0.04%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               1      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43               1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               2      0.04%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47               1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               1      0.02%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::58-59               1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73               1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::78-79               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5572                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1537104750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4237761000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    720175000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10671.74                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::64-65               1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::70-71               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5574                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1547962750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4249219000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    720335000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10744.74                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29421.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.16                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29494.74                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.17                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          16.87                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.18                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.19                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                       16.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     110916                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64397                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.01                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.69                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1521908.78                       # Average gap between requests
-system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  248466960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135572250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 560157000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                310566960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            23928256560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47486087820                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           178156194000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             250825301550                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              684.658255                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   296072654000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12233260000                       # Time in different power states
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        20.02                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110904                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64452                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.98                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.74                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1521741.45                       # Average gap between requests
+system.physmem.pageHitRate                      72.87                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  247983120                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135308250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 560305200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                310528080                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            23927239440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            47721013605                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           177940783500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             250843161195                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              684.736086                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   295712636000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12232740000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     58046909500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     58390260500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  244634040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133480875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 562879200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                314740080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            23928256560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            47146698135                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           178453904250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             250784593140                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              684.547137                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   296568978750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12233260000                       # Time in different power states
+system.physmem_1.actEnergy                  245095200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  133732500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 563066400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                314791920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            23927239440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            47027452140                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           178549170750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             250760548350                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              684.510574                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   296727601000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12232740000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     57550826250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     57375209000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               132589371                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98514041                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6557944                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68842060                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                64854431                       # Number of BTB hits
+system.cpu.branchPred.lookups               132583064                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98508784                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6555218                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             69071756                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                64847878                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.207569                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                10017867                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              17926                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.884797                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                10016520                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              18156                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -417,98 +418,98 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        732716951                       # number of cpu cycles simulated
+system.cpu.numCycles                        732679001                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   506582155                       # Number of instructions committed
-system.cpu.committedOps                     548695378                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13466923                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   506582156                       # Number of instructions committed
+system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      13461102                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.446393                       # CPI: cycles per instruction
-system.cpu.ipc                               0.691375                       # IPC: instructions per cycle
-system.cpu.tickCycles                       695825303                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        36891648                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1139854                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.954710                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171283379                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1143950                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.729778                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.446318                       # CPI: cycles per instruction
+system.cpu.ipc                               0.691411                       # IPC: instructions per cycle
+system.cpu.tickCycles                       695769824                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        36909177                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1139845                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.953673                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           171282385                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1143941                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.730087                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        4900143250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.954710                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.953673                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993885                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993885                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          545                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          544                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         3507                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346821558                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346821558                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114764882                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114764882                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53538642                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53538642                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2773                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2773                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         346819443                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346819443                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114763887                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114763887                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53538651                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53538651                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2765                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2765                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168303524                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168303524                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168306297                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168306297                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       854741                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        854741                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       700664                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       700664                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           20                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           20                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1555405                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1555405                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1555425                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1555425                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14025846982                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14025846982                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  22027401500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  22027401500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  36053248482                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  36053248482                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  36053248482                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  36053248482                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115619623                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115619623                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     168302538                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168302538                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168305303                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168305303                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       854696                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        854696                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       700655                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       700655                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1555351                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1555351                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1555366                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1555366                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14025171732                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14025171732                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  22048092000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  22048092000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  36073263732                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  36073263732                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  36073263732                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  36073263732                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    115618583                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115618583                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2793                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2793                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2780                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2780                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169858929                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169858929                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169861722                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169861722                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007393                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.007393                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    169857889                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169857889                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169860669                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169860669                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007392                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007392                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012918                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.012918                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007161                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.007161                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005396                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.005396                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.009157                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.009157                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.009157                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.009157                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.470216                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.470216                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31437.895339                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31437.895339                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23179.331738                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23179.331738                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23179.033693                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23179.033693                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.544133                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.544133                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31467.829388                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31467.829388                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23193.005136                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23193.005136                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23192.781462                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23192.781462                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -517,111 +518,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1068578                       # number of writebacks
-system.cpu.dcache.writebacks::total           1068578                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66974                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        66974                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344497                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344497                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       411471                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       411471                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       411471                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       411471                       # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks      1068547                       # number of writebacks
+system.cpu.dcache.writebacks::total           1068547                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66929                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        66929                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344493                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       344493                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       411422                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       411422                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       411422                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       411422                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787767                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       787767                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356167                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356167                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           16                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total           16                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1143934                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1143934                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1143950                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1143950                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11930687015                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  11930687015                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10965407750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10965407750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1449000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1449000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22896094765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  22896094765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22897543765                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  22897543765                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356162                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356162                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1143929                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1143929                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1143941                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1143941                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11930909015                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  11930909015                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10976099750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10976099750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       986500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       986500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22907008765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  22907008765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22907995265                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  22907995265                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006813                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006567                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006567                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005729                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005729                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004317                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004317                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006735                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006735                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15144.943892                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15144.943892                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30787.264822                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30787.264822                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 90562.500000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 90562.500000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20015.223575                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20015.223575                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.210293                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.210293                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15145.225701                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15145.225701                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30817.717078                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30817.717078                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 82208.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 82208.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20024.851861                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20024.851861                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.504169                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.504169                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             17681                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1190.210021                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           200953825                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19553                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10277.390937                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             17672                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1190.163457                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           200929857                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             19544                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          10280.897309                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1190.210021                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.581157                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.581157                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1190.163457                       # Average occupied blocks per requestor
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-system.cpu.icache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
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-system.cpu.icache.tags.age_task_id_blocks_1024::4         1410                       # Occupied blocks per task id
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+system.cpu.icache.overall_avg_miss_latency::total 25319.688702                       # average overall miss latency
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 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -630,122 +631,122 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
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 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.177262                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.123000                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123912                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79109.203693                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82527.382298                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 82253.713243                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78593.374867                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78593.374867                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79109.203693                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79706.844413                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79692.476695                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79109.203693                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79706.844413                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79692.476695                       # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst         3474                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       140714                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        144188                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3474                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       140714                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       144188                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    275801500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3286544500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3562346000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7939327250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7939327250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    275801500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11225871750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11501673250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    275801500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11225871750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11501673250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        19544                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       787526                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       807070                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1068547                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1068547                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       356415                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       356415                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        19544                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1143941                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1163485                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        19544                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1143941                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1163485                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.177753                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.050580                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.053660                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283044                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.283044                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.177753                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.123008                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123928                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.177753                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.123008                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123928                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79390.184226                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82508.083750                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 82257.972152                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78699.926151                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78699.926151                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79390.184226                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79777.930767                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79768.588579                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79390.184226                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79777.930767                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79768.588579                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -754,8 +755,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        96568                       # number of writebacks
-system.cpu.l2cache.writebacks::total            96568                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        96566                       # number of writebacks
+system.cpu.l2cache.writebacks::total            96566                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           15                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
@@ -765,105 +766,105 @@ system.cpu.l2cache.demand_mshr_hits::total           17                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           15                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3464                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39810                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        43274                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3472                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39818                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        43290                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100881                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       100881                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3464                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       140691                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       144155                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3464                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       140691                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       144155                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    230478500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2786732250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3017210750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6666945750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6666945750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    230478500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9453678000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9684156500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    230478500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9453678000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9684156500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.177160                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.050550                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053618                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283042                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283042                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.177160                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122987                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123897                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.177160                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122987                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123897                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66535.363741                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70000.810098                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69723.407820                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66087.229012                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66087.229012                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66535.363741                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.617993                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67178.776317                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66535.363741                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.617993                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67178.776317                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3472                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       140699                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       144171                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3472                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       140699                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       144171                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    232222500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2786510500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3018733000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6677694250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6677694250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    232222500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9464204750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9696427250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    232222500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9464204750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9696427250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.177650                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.050561                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053638                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283044                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283044                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.177650                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122995                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123913                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.177650                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122995                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123913                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66884.360599                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69981.176855                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69732.802033                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66193.775339                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66193.775339                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66884.360599                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67265.614894                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67256.433333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66884.360599                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67265.614894                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67256.433333                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         807086                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        807086                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1068578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356417                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356417                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39106                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356478                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3395584                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1251392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141601792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          142853184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq         807070                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        807070                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1068547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356415                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356415                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39088                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356429                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3395517                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1250816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141599232                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          142850048                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2232081                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      2232032                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            2232081    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            2232032    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2232081                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2184618500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2232032                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2184563000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      30027495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      30009996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1744688735                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1744692235                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               43274                       # Transaction distribution
-system.membus.trans_dist::ReadResp              43274                       # Transaction distribution
-system.membus.trans_dist::Writeback             96568                       # Transaction distribution
+system.membus.trans_dist::ReadReq               43290                       # Transaction distribution
+system.membus.trans_dist::ReadResp              43290                       # Transaction distribution
+system.membus.trans_dist::Writeback             96566                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            100881                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           100881                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384878                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 384878                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15406272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15406272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384908                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 384908                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15407168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15407168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            240723                       # Request fanout histogram
+system.membus.snoop_fanout::samples            240737                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  240723    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  240737    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              240723                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           679184500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              240737                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           679133000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          765222500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          765318250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 2bb46ae0a..f6e4f2ecd 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.233382                       # Number of seconds simulated
-sim_ticks                                233381523500                       # Number of ticks simulated
-final_tick                               233381523500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.233457                       # Number of seconds simulated
+sim_ticks                                233457400500                       # Number of ticks simulated
+final_tick                               233457400500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 138194                       # Simulator instruction rate (inst/s)
-host_op_rate                                   149713                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63835070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 248488                       # Number of bytes of host memory used
-host_seconds                                  3656.01                       # Real time elapsed on the host
-sim_insts                                   505237723                       # Number of instructions simulated
-sim_ops                                     547350944                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 105147                       # Simulator instruction rate (inst/s)
+host_op_rate                                   113911                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48585649                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312624                       # Number of bytes of host memory used
+host_seconds                                  4805.07                       # Real time elapsed on the host
+sim_insts                                   505237724                       # Number of instructions simulated
+sim_ops                                     547350945                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            689856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9181056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     16498240                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26369152                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       689856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          689856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18710272                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18710272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              10779                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       257785                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                412018                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292348                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292348                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2955915                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39339258                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     70692143                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               112987316                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2955915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2955915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          80170322                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               80170322                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          80170322                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2955915                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39339258                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     70692143                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              193157639                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        412018                       # Number of read requests accepted
-system.physmem.writeReqs                       292348                       # Number of write requests accepted
-system.physmem.readBursts                      412018                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     292348                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26233536                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    135616                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18708736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26369152                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18710272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2119                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst            691264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9218304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     16465984                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             26375552                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       691264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          691264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18705216                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18705216                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              10801                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144036                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       257281                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                412118                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292269                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292269                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2960986                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39486022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     70531000                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               112978008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2960986                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2960986                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          80122609                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               80122609                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          80122609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2960986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39486022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     70531000                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              193100617                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        412118                       # Number of read requests accepted
+system.physmem.writeReqs                       292269                       # Number of write requests accepted
+system.physmem.readBursts                      412118                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292269                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26236672                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    138880                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18703040                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26375552                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18705216                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2170                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              3                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26413                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25441                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25280                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24861                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               26943                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               26409                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25350                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24226                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25719                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24800                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25359                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              26216                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26433                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25856                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25009                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25584                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18684                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               18331                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18001                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18053                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18581                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18287                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18028                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               17667                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18026                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17689                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18246                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18799                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18831                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18312                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              18349                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              18440                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26483                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25520                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25375                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24791                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27157                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               26569                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25228                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24398                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25772                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               24727                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25014                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25991                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26422                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25825                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25184                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25492                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18766                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               18282                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18016                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18022                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18772                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18348                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               17902                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               17779                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18029                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17785                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18061                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18677                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18741                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18309                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              18406                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              18340                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    233381437000                       # Total gap between requests
+system.physmem.totGap                    233457328000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  412018                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  412118                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292348                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    312437                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47937                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13197                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9328                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7381                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5333                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3421                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292269                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    312558                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     47724                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9298                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7441                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6251                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5340                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4463                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3424                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    13233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    15344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16904                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    18042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    18396                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    18527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    18799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    19969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    18456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    13223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    15385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16921                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    19851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    18588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
@@ -197,103 +197,101 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       307121                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      146.330964                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     102.916756                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     182.072957                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         184589     60.10%     60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        81854     26.65%     86.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        16654      5.42%     92.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7226      2.35%     94.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4782      1.56%     96.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2270      0.74%     96.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1753      0.57%     97.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1588      0.52%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6405      2.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         307121                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17353                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.620930                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      116.705820                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           17352     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       306919                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      146.415804                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     102.989110                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     182.052610                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         184181     60.01%     60.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        81968     26.71%     86.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        16622      5.42%     92.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7343      2.39%     94.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4784      1.56%     96.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2292      0.75%     96.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1776      0.58%     97.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1536      0.50%     97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6417      2.09%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         306919                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17350                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.626628                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      116.525366                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           17349     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17353                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17353                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.845733                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.805125                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.212117                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              10719     61.77%     61.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                285      1.64%     63.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               5449     31.40%     94.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                585      3.37%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                128      0.74%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 65      0.37%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 37      0.21%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 35      0.20%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 29      0.17%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 15      0.09%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  4      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17353                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9387910450                       # Total ticks spent queuing
-system.physmem.totMemAccLat               17073516700                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2049495000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22902.98                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17350                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17350                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.843516                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.802727                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.214220                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              10753     61.98%     61.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                289      1.67%     63.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               5387     31.05%     94.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                614      3.54%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                106      0.61%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 63      0.36%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 46      0.27%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 45      0.26%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 29      0.17%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 12      0.07%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  6      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17350                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9548241731                       # Total ticks spent queuing
+system.physmem.totMemAccLat               17234766731                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2049740000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       23291.35                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41652.98                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         112.41                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          80.16                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      112.99                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       80.17                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  42041.35                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         112.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          80.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      112.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       80.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.50                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.88                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        21.73                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     299659                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95432                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.11                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  32.64                       # Row buffer hit rate for writes
-system.physmem.avgGap                       331335.47                       # Average gap between requests
-system.physmem.pageHitRate                      56.26                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1156453200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  631001250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1598134200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                943500960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15243068880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            74948893020                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            74281875750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             168802927260                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              723.304109                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   123045424463                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7792980000                       # Time in different power states
+system.physmem.readRowHits                     299652                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95604                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   73.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  32.71                       # Row buffer hit rate for writes
+system.physmem.avgGap                       331433.33                       # Average gap between requests
+system.physmem.pageHitRate                      56.29                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1157927400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  631805625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1602907800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                945308880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            15248154480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            75190255245                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            74116872000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             168893231430                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              723.449687                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   122769601530                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7795580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    102539140537                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    102890225970                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1165048920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  635691375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1598610000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                950447520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15243068880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            74482095510                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            74691339000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             168766301205                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              723.147212                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   123736015873                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7792980000                       # Time in different power states
+system.physmem_1.actEnergy                 1162259280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  634169250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1594382400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                948263760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            15248154480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            74130386985                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75046581000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             168764197155                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              722.896972                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   124323822632                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7795580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    101848756127                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    101336607368                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               175093442                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         131339013                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7445255                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90524838                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83882931                       # Number of BTB hits
+system.cpu.branchPred.lookups               175097732                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         131341907                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7444118                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90491460                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83879546                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.662890                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12110656                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104163                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.693328                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12111412                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104155                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -412,129 +410,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        466763048                       # number of cpu cycles simulated
+system.cpu.numCycles                        466914802                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            7833738                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      731827371                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   175093442                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           95993587                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     450556948                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14942959                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 6375                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           162                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        12684                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 236728618                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 34396                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          465881386                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.701216                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.179605                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            7831702                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      731836126                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   175097732                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           95990958                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     450721779                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14940955                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 5640                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           179                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        13551                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 236729658                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 34605                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          466043328                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.700638                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.179812                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 93942381     20.16%     20.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                132696529     28.48%     48.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 57859169     12.42%     61.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                181383307     38.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 94098707     20.19%     20.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                132700679     28.47%     48.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 57861600     12.42%     61.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                181382342     38.92%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            465881386                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.375123                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.567878                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32362328                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             117422213                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 287082190                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              22031979                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6982676                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24051776                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                496598                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              715820836                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              30011268                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6982676                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 63423410                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                54356901                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       40333857                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276674345                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24110197                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              686603373                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13342977                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               9430232                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2385222                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1668168                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1866322                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           831029947                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3019214336                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        723928049                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            466043328                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.375010                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.567387                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32400238                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             117626282                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 286962359                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22072426                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6982023                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             24050963                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                496269                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              715816443                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29997814                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6982023                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 63475472                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                54498348                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       40339589                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 276580199                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24167697                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              686605984                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13334781                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               9429797                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2386503                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1670701                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1903283                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           831017415                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3019232506                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        723934620                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654123751                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                176906196                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1544708                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1534779                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  42310456                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            143529227                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            67980457                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12876117                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11223865                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  668168633                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.UndoneMaps                176893664                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1544707                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1534925                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  42378773                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            143528821                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            67986057                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12870746                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11400164                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  668175203                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded             2978333                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 610244720                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5860928                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       123796022                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    319249921                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 610240343                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5850286                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       123802591                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    319329527                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            701                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     465881386                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.309871                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.101485                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     466043328                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.309407                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.101734                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           148726725     31.92%     31.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           101219272     21.73%     53.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           145704053     31.27%     84.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            63308472     13.59%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6922394      1.49%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 470      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           148928880     31.96%     31.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           101192205     21.71%     53.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           145640431     31.25%     84.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            63360456     13.60%     98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6920872      1.49%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 484      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       465881386                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       466043328                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                71926892     52.97%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     30      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44548808     32.81%     85.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              19308609     14.22%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                71964986     53.01%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     30      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44551194     32.82%     85.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              19229314     14.17%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             413151205     67.70%     67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               351762      0.06%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             413153889     67.70%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               351748      0.06%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
@@ -562,96 +560,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            134213175     21.99%     89.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            62528575     10.25%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            134217118     21.99%     89.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            62517585     10.24%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              610244720                       # Type of FU issued
-system.cpu.iq.rate                           1.307397                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   135784339                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.222508                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1828015800                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         794971084                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    594984495                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              610240343                       # Type of FU issued
+system.cpu.iq.rate                           1.306963                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   135745524                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.222446                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1828119531                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         794984388                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    594979068                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 293                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                316                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              746028882                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              745985690                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     177                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          7272735                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          7282878                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27644471                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        25523                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        28862                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11119980                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     27644065                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        25657                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        28996                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     11125580                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       225173                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         19543                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       225352                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         19393                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6982676                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                23041794                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                922625                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           672634659                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                6982023                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                23078591                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                913703                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           672641346                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             143529227                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             67980457                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts             143528821                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             67986057                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts            1489791                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 257738                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                528673                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          28862                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3822612                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3731799                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7554411                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             599400407                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             129575642                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10844313                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                 257861                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                519542                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          28996                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3822175                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3731272                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7553447                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             599393385                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             129576774                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10846958                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1487693                       # number of nop insts executed
-system.cpu.iew.exec_refs                    190530493                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                131374378                       # Number of branches executed
-system.cpu.iew.exec_stores                   60954851                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.284164                       # Inst execution rate
-system.cpu.iew.wb_sent                      596279757                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     594984511                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 349915362                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 570660996                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       1487810                       # number of nop insts executed
+system.cpu.iew.exec_refs                    190521112                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                131377011                       # Number of branches executed
+system.cpu.iew.exec_stores                   60944338                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.283732                       # Inst execution rate
+system.cpu.iew.wb_sent                      596274130                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     594979084                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 349911288                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 570684699                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.274704                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.613176                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.274278                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.613143                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       110032490                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       110037784                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6956452                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    448764802                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.222678                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.888107                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6955664                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    448925828                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.222239                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.888253                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    219732753     48.96%     48.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    116339584     25.92%     74.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43745322      9.75%     84.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     23276938      5.19%     89.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11568250      2.58%     92.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7761637      1.73%     94.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8261110      1.84%     95.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4247723      0.95%     96.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13831485      3.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    219983984     49.00%     49.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116251312     25.90%     74.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43736792      9.74%     84.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     23204110      5.17%     89.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11645207      2.59%     92.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7768175      1.73%     94.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8255090      1.84%     95.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4243904      0.95%     96.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13837254      3.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    448764802                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
-system.cpu.commit.committedOps              548694828                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    448925828                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            506581608                       # Number of instructions committed
+system.cpu.commit.committedOps              548694829                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      172745233                       # Number of memory references committed
 system.cpu.commit.loads                     115884756                       # Number of loads committed
 system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
-system.cpu.commit.branches                  121548301                       # Number of branches committed
+system.cpu.commit.branches                  121548302                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 448454354                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        375610373     68.46%     68.46% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        375610374     68.46%     68.46% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          339219      0.06%     68.52% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     68.52% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     68.52% # Class of committed instruction
@@ -684,381 +682,381 @@ system.cpu.commit.op_class_0::MemRead       115884756     21.12%     89.64% # Cl
 system.cpu.commit.op_class_0::MemWrite       56860477     10.36%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         548694828                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              13831485                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1093653497                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1334601058                       # The number of ROB writes
-system.cpu.timesIdled                           13925                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          881662                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
-system.cpu.committedOps                     547350944                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.923848                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.923848                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.082429                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.082429                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                611089137                       # number of integer regfile reads
-system.cpu.int_regfile_writes               328121807                       # number of integer regfile writes
+system.cpu.commit.op_class_0::total         548694829                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              13837254                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1093814049                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1334612597                       # The number of ROB writes
+system.cpu.timesIdled                           13893                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          871474                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   505237724                       # Number of Instructions Simulated
+system.cpu.committedOps                     547350945                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.924149                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.924149                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.082077                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.082077                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                611066187                       # number of integer regfile reads
+system.cpu.int_regfile_writes               328122868                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                2170187431                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                376547848                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217970630                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2170174557                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                376546263                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               217961585                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2821443                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.630682                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           169417803                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2821955                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             60.035615                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         498977500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.630682                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999279                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999279                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2821455                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.631544                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           169406374                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2821967                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             60.031309                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         498452500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.631544                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999280                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999280                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         356251797                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        356251797                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114676407                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114676407                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     51761464                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       51761464                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2782                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2782                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         356233951                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        356233951                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114665404                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114665404                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     51761034                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       51761034                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2783                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2783                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488559                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488559                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     166437871                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        166437871                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    166440653                       # number of overall hits
-system.cpu.dcache.overall_hits::total       166440653                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4819248                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4819248                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2477842                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2477842                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     166426438                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        166426438                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    166429221                       # number of overall hits
+system.cpu.dcache.overall_hits::total       166429221                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4821321                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4821321                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2478272                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2478272                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      7297090                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7297090                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7297102                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7297102                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  56184151983                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  56184151983                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18816988488                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18816988488                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1349500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      1349500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  75001140471                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  75001140471                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  75001140471                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  75001140471                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    119495655                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    119495655                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      7299593                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7299593                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7299605                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7299605                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  56428314397                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  56428314397                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18848897160                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18848897160                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1043750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      1043750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  75277211557                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  75277211557                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  75277211557                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  75277211557                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    119486725                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    119486725                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2794                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2794                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2795                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2795                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    173734961                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    173734961                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    173737755                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    173737755                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040330                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040330                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.045684                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.045684                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004295                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.004295                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    173726031                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    173726031                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    173728826                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    173728826                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040350                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040350                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.045691                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.045691                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004293                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.004293                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.042001                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.042001                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.042001                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.042001                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7594.103453                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  7594.103453                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10278.226042                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10278.209140                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            2                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       705176                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          220270                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs            2                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     3.201416                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.042018                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.042018                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042017                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042017                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11703.911521                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11703.911521                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7605.661187                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  7605.661187                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15814.393939                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15814.393939                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10312.521747                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10312.521747                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10312.504794                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10312.504794                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           28                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       711137                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          220355                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     3.227233                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2356074                       # number of writebacks
-system.cpu.dcache.writebacks::total           2356074                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2516883                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2516883                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1958234                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1958234                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2352760                       # number of writebacks
+system.cpu.dcache.writebacks::total           2352760                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2518936                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2518936                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1958671                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1958671                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4475117                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4475117                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4475117                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4475117                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2302365                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2302365                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519608                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       519608                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4477607                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4477607                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4477607                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4477607                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2302385                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2302385                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519601                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       519601                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2821973                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2821973                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2821983                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2821983                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27555148045                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27555148045                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4324407514                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4324407514                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       652250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       652250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31879555559                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  31879555559                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31880207809                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31880207809                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019267                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019267                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2821986                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2821986                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2821996                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2821996                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27643726875                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27643726875                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4325979851                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4325979851                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       667500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       667500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31969706726                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  31969706726                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31970374226                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31970374226                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019269                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019269                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009580                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009580                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003579                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003579                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016243                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016243                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016243                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.016243                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11968.192726                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11968.192726                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8322.442137                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8322.442137                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        65225                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        65225                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11296.903110                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11296.903110                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11297.094210                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11297.094210                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003578                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003578                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016244                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016244                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016244                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.016244                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12006.561403                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12006.561403                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8325.580303                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8325.580303                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        66750                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        66750                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11328.797069                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11328.797069                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11328.993459                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11328.993459                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             73466                       # number of replacements
-system.cpu.icache.tags.tagsinuse           466.200525                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           236646541                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             73978                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3198.877247                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      115003506250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   466.200525                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910548                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910548                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             73478                       # number of replacements
+system.cpu.icache.tags.tagsinuse           466.210203                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           236647479                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             73990                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3198.371118                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      115019212250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   466.210203                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.910567                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.910567                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          119                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4           15                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4           16                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         473531001                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        473531001                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    236646541                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       236646541                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     236646541                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        236646541                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    236646541                       # number of overall hits
-system.cpu.icache.overall_hits::total       236646541                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        81956                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         81956                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        81956                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          81956                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        81956                       # number of overall misses
-system.cpu.icache.overall_misses::total         81956                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1579166787                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1579166787                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1579166787                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1579166787                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1579166787                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1579166787                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    236728497                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    236728497                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    236728497                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    236728497                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    236728497                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    236728497                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000346                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000346                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000346                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000346                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000346                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000346                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19268.470728                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19268.470728                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       192617                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           91                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              6539                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         473533098                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        473533098                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    236647479                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       236647479                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     236647479                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        236647479                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    236647479                       # number of overall hits
+system.cpu.icache.overall_hits::total       236647479                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        82060                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         82060                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        82060                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          82060                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        82060                       # number of overall misses
+system.cpu.icache.overall_misses::total         82060                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1575366023                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1575366023                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1575366023                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1575366023                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1575366023                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1575366023                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    236729539                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    236729539                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    236729539                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    236729539                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    236729539                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    236729539                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000347                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000347                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000347                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000347                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000347                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000347                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19197.733646                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19197.733646                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19197.733646                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19197.733646                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19197.733646                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19197.733646                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       189178                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           92                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              6697                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    29.456645                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    22.750000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    28.248171                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           23                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7948                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         7948                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         7948                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         7948                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         7948                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         7948                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74008                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        74008                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        74008                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        74008                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        74008                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        74008                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1251050514                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1251050514                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1251050514                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1251050514                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1251050514                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1251050514                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8039                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         8039                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         8039                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74021                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        74021                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000313                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16904.260539                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16904.260539                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16904.260539                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16904.260539                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16904.260539                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16904.260539                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16833.638508                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16833.638508                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      8510841                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      8513336                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         1033                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      8513000                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      8515433                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          981                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage       743496                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           401010                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15417.841274                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4560227                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           417347                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.926704                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      34597011000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8457.509015                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   475.097428                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4918.264697                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1566.970133                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.516205                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.028998                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.300187                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.095640                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.941030                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         1096                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15241                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.replacements           401084                       # number of replacements
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+system.cpu.l2cache.tags.avg_refs            10.917462                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      34596581000                       # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst   474.072074                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4920.608759                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          254                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9927                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.066895                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.930237                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.Writeback_hits::total      2356074                       # number of Writeback hits
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 system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
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+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           29                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           29                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       521901                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       521901                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        73987                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2821967                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2895954                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        73987                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2821967                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2895954                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.146107                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.062843                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.065438                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.068966                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.068966                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009862                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.009862                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.146107                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.053045                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.055422                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.146107                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.053045                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.055422                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73750.825994                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77702.821196                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 77427.829448                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91466.506509                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91466.506509                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73750.825994                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78176.074019                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77878.026461                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73750.825994                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78176.074019                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77878.026461                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1067,143 +1065,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292348                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292348                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         4205                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total         4209                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1534                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1534                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         5739                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         5743                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         5739                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         5743                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10780                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       139789                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       150569                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       275622                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       275622                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       292269                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292269                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         4161                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total         4169                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1493                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1493                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         5654                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         5662                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         5654                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         5662                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10802                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       140383                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       151185                       # number of ReadReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       275132                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       275132                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3666                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3666                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10780                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143455                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154235                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10780                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143455                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       275622                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       429857                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    710057825                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   9596193047                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10306250872                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18910984010                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18910984010                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        27502                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        27502                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    283384780                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    283384780                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    710057825                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9879577827                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10589635652                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    710057825                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9879577827                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18910984010                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  29500619662                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.145725                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.060777                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.063424                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3654                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3654                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10802                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       144037                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       154839                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10802                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       144037                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       275132                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       429971                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    704756821                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   9683951989                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10388708810                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18994026058                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18994026058                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        28002                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        28002                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    285290758                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    285290758                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    704756821                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9969242747                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10673999568                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    704756821                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9969242747                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18994026058                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  29668025626                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.061034                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.063682                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.071429                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.071429                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007024                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007024                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.145725                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.050835                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.053259                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.145725                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.050835                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.068966                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.068966                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007001                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007001                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.051041                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.053467                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.051041                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.148435                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        13751                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        13751                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.148473                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68982.369582                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68715.208586                       # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69036.048362                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78076.288451                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78076.288451                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69213.068496                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68936.117955                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69213.068496                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69000.061925                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2374050                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2374049                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2356074                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       317604                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           28                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           28                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       521913                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       521913                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       147982                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8000040                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8148022                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4734336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331393856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          336128192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      317637                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5569669                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.057024                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.231888                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        2374087                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2374086                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2352760                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       317092                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           29                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           29                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       521901                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       521901                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       148007                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7996752                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8144759                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4735104                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331182528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          335917632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      317126                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5565869                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.056971                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.231787                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            5252065     94.30%     94.30% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4             317604      5.70%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            5248777     94.30%     94.30% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4             317092      5.70%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5569669                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4982106500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5565869                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4977148500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     112829788                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     112866029                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4256050685                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4256213768                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              408353                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408353                       # Transaction distribution
-system.membus.trans_dist::Writeback            292348                       # Transaction distribution
+system.membus.trans_dist::ReadReq              408465                       # Transaction distribution
+system.membus.trans_dist::ReadResp             408465                       # Transaction distribution
+system.membus.trans_dist::Writeback            292269                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3665                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3665                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1116390                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1116390                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45079424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                45079424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq              3653                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3653                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1116511                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1116511                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45080768                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                45080768                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            704369                       # Request fanout histogram
+system.membus.snoop_fanout::samples            704390                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  704369    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  704390    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              704369                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2100254662                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              704390                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2099926272                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2178151058                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2178828981                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index ac9d5a522..7518311dc 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,40 +1,40 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.279362                       # Number of seconds simulated
-sim_ticks                                279362297500                       # Number of ticks simulated
-final_tick                               279362297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                279362298000                       # Number of ticks simulated
+final_tick                               279362298000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1941586                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2102994                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1070717412                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304560                       # Number of bytes of host memory used
-host_seconds                                   260.91                       # Real time elapsed on the host
-sim_insts                                   506581607                       # Number of instructions simulated
-sim_ops                                     548694828                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1382525                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1497457                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              762414599                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298924                       # Number of bytes of host memory used
+host_seconds                                   366.42                       # Real time elapsed on the host
+sim_insts                                   506581608                       # Number of instructions simulated
+sim_ops                                     548694829                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        2066445500                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst        2066445504                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         422852701                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           2489298201                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   2066445500                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      2066445500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total           2489298205                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   2066445504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      2066445504                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      216067624                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         216067624                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          516611375                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          516611376                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data          115591527                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             632202902                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             632202903                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          55727847                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             55727847                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7397009255                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1513635536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              8910644791                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7397009255                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7397009255                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           773431583                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              773431583                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7397009255                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2287067119                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9684076374                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           7397009256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1513635534                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              8910644789                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7397009256                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7397009256                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           773431582                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              773431582                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7397009256                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2287067115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9684076371                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -153,11 +153,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        558724596                       # number of cpu cycles simulated
+system.cpu.numCycles                        558724597                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   506581607                       # Number of instructions committed
-system.cpu.committedOps                     548694828                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                   506581608                       # Number of instructions committed
+system.cpu.committedOps                     548694829                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             448454356                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                    19311615                       # number of times a function call or return occured
@@ -168,18 +168,18 @@ system.cpu.num_int_register_reads           749039746                       # nu
 system.cpu.num_int_register_writes          290003067                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads           1634230247                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads           1634230250                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes           344080722                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     172745235                       # number of memory refs
 system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               558724595.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               558724596.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                         121548301                       # Number of branches fetched
+system.cpu.Branches                         121548302                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 375610921     68.46%     68.46% # Class of executed instruction
+system.cpu.op_class::IntAlu                 375610922     68.46%     68.46% # Class of executed instruction
 system.cpu.op_class::IntMult                   339219      0.06%     68.52% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     68.52% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     68.52% # Class of executed instruction
@@ -212,9 +212,9 @@ system.cpu.op_class::MemRead                115884756     21.12%     89.64% # Cl
 system.cpu.op_class::MemWrite                56860479     10.36%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  548695378                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           630711790                       # Transaction distribution
-system.membus.trans_dist::ReadResp          632200331                       # Transaction distribution
+system.cpu.op_class::total                  548695379                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           630711791                       # Transaction distribution
+system.membus.trans_dist::ReadResp          632200332                       # Transaction distribution
 system.membus.trans_dist::WriteReq           54239306                       # Transaction distribution
 system.membus.trans_dist::WriteResp          54239306                       # Transaction distribution
 system.membus.trans_dist::SoftPFReq              2571                       # Transaction distribution
@@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp             2571                       # Tr
 system.membus.trans_dist::LoadLockedReq       1488541                       # Transaction distribution
 system.membus.trans_dist::StoreCondReq        1488541                       # Transaction distribution
 system.membus.trans_dist::StoreCondResp       1488541                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1033222750                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1033222752                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    342638748                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             1375861498                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2066445500                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total             1375861500                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2066445504                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    638920325                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              2705365825                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              2705365829                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         687930749                       # Request fanout histogram
+system.membus.snoop_fanout::samples         687930750                       # Request fanout histogram
 system.membus.snoop_fanout::mean             2.750964                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.432455                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::2               171319374     24.90%     24.90% # Request fanout histogram
-system.membus.snoop_fanout::3               516611375     75.10%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::3               516611376     75.10%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               2                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               3                       # Request fanout histogram
-system.membus.snoop_fanout::total           687930749                       # Request fanout histogram
+system.membus.snoop_fanout::total           687930750                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index f53112701..93937d49d 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,40 +1,40 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.707538                       # Number of seconds simulated
-sim_ticks                                707538046500                       # Number of ticks simulated
-final_tick                               707538046500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                707538047500                       # Number of ticks simulated
+final_tick                               707538047500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1058036                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1145805                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1482416058                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313032                       # Number of bytes of host memory used
-host_seconds                                   477.29                       # Real time elapsed on the host
-sim_insts                                   504986853                       # Number of instructions simulated
-sim_ops                                     546878104                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 813114                       # Simulator instruction rate (inst/s)
+host_op_rate                                   880566                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1139256199                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308656                       # Number of bytes of host memory used
+host_seconds                                   621.05                       # Real time elapsed on the host
+sim_insts                                   504986854                       # Number of instructions simulated
+sim_ops                                     546878105                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            177280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8952256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            177216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8952320                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              9129536                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       177280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          177280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       177216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          177216                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      6140992                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           6140992                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2770                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             139879                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2769                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             139880                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                142649                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           95953                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                95953                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               250559                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12652685                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               250469                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12652775                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total                12903244                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          250559                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             250559                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          250469                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             250469                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks           8679381                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total                8679381                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks           8679381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              250559                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12652685                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              250469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12652775                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               21582625                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -154,11 +154,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                       1415076093                       # number of cpu cycles simulated
+system.cpu.numCycles                       1415076095                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   504986853                       # Number of instructions committed
-system.cpu.committedOps                     546878104                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                   504986854                       # Number of instructions committed
+system.cpu.committedOps                     546878105                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             448454356                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                    19311615                       # number of times a function call or return occured
@@ -169,18 +169,18 @@ system.cpu.num_int_register_reads           748355652                       # nu
 system.cpu.num_int_register_writes          290003067                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads           1984297856                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads           1984297859                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes           344080722                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     172745235                       # number of memory refs
 system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1415076092.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1415076094.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                         121548301                       # Number of branches fetched
+system.cpu.Branches                         121548302                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 375610921     68.46%     68.46% # Class of executed instruction
+system.cpu.op_class::IntAlu                 375610922     68.46%     68.46% # Class of executed instruction
 system.cpu.op_class::IntMult                   339219      0.06%     68.52% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     68.52% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     68.52% # Class of executed instruction
@@ -213,14 +213,14 @@ system.cpu.op_class::MemRead                115884756     21.12%     89.64% # Cl
 system.cpu.op_class::MemWrite                56860479     10.36%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  548695378                       # Class of executed instruction
+system.cpu.op_class::total                  548695379                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           1134822                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4065.318390                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4065.318385                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           170180456                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1138918                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            149.422922                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       11716393000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318390                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle       11716394000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318385                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.992509                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.992509                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data      1138917                       # n
 system.cpu.dcache.demand_misses::total        1138917                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11818657500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11818657500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11818699500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11818699500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data   8868772000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total   8868772000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  20687429500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  20687429500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  20687429500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  20687429500                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  20687471500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  20687471500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  20687471500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  20687471500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    114100415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    114100415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
@@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.006766
 system.cpu.dcache.demand_miss_rate::total     0.006766                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.006765                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.006765                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18164.123900                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18164.107952                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18164.160777                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18164.144829                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1138917
 system.cpu.dcache.demand_mshr_misses::total      1138917                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10644672000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10644672000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10644714000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10644714000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8334382000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total   8334382000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18979054000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18979054000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18979107500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18979107500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18979096000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18979096000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18979149500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18979149500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
@@ -336,24 +336,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006766
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006766                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006765                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006765                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.739532                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.739532                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53500                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.160777                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.160777                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.193120                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9788                       # number of replacements
-system.cpu.icache.tags.tagsinuse           983.372132                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           516599855                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           983.372130                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           516599856                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             11521                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          44839.845066                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          44839.845152                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   983.372132                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   983.372130                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.480162                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.480162                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1733                       # Occupied blocks per task id
@@ -363,44 +363,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2           24
 system.cpu.icache.tags.age_task_id_blocks_1024::3          256                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1402                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.846191                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1033234273                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1033234273                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    516599855                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       516599855                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     516599855                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        516599855                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    516599855                       # number of overall hits
-system.cpu.icache.overall_hits::total       516599855                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        1033234275                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1033234275                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    516599856                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       516599856                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     516599856                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        516599856                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    516599856                       # number of overall hits
+system.cpu.icache.overall_hits::total       516599856                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        11521                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         11521                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        11521                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
 system.cpu.icache.overall_misses::total         11521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    266293500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    266293500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    266293500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    266293500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    266293500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    266293500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    516611376                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    516611376                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    516611376                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    516611376                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    516611376                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    516611376                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    266251500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    266251500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    266251500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    266251500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    266251500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    266251500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    516611377                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    516611377                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    516611377                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    516611377                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    516611377                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    516611377                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23113.748807                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23113.748807                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23113.748807                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23113.748807                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23110.103290                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23110.103290                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23110.103290                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23110.103290                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23110.103290                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23110.103290                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -415,37 +415,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        11521
 system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    249012000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    249012000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    249012000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    249012000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    249012000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    249012000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    248970000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    248970000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    248970000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    248970000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    248970000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    248970000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21613.748807                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21613.748807                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21613.748807                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21613.748807                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21613.748807                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21610.103290                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21610.103290                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21610.103290                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21610.103290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21610.103290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21610.103290                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           109895                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27249.388139                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        27249.388101                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1668833                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           141072                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs            11.829654                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     338494304500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989190                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   287.904965                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3574.493984                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.warmup_cycle     338494305500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989157                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   287.672992                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3574.725951                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.713714                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008786                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.109085                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008779                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.109092                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.831585                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31177                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
@@ -455,40 +455,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27181
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951447                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         18220084                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        18220084                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8751                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       743573                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8752                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       743572                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         752324                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      1064905                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total      1064905                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data       255466                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total       255466                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8751                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       999039                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         8752                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       999038                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total         1007790                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8751                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       999039                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst         8752                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       999038                       # number of overall hits
 system.cpu.l2cache.overall_hits::total        1007790                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2770                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        39085                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2769                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        39086                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        41855                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data       100794                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       100794                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2770                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       139879                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         2769                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       139880                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        142649                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2770                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       139879                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst         2769                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       139880                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       142649                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    145605500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2054496500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    145553000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2054549000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total   2200102000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5295729000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total   5295729000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    145605500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   7350225500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    145553000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   7350278000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total   7495831000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    145605500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   7350225500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    145553000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   7350278000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total   7495831000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        11521                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data       782658                       # number of ReadReq accesses(hits+misses)
@@ -503,27 +503,27 @@ system.cpu.l2cache.demand_accesses::total      1150439                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst        11521                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1138918                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      1150439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.240431                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.049939                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.240344                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.049940                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.052702                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282923                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.282923                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.240431                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.122817                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.240344                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.122818                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.123995                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.240431                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.122817                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.240344                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.122818                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.123995                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.162455                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.833056                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.185988                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.831397                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.162455                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026358                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.185988                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026022                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.162455                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026358                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.185988                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026022                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -535,49 +535,49 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        95953                       # number of writebacks
 system.cpu.l2cache.writebacks::total            95953                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2770                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39085                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2769                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39086                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total        41855                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100794                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       100794                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2770                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       139879                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2769                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       139880                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       142649                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2770                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       139879                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2769                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       139880                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       142649                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    112218500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1583343000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    112178000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1583383500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1695561500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4082164000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4082164000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    112218500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5665507000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    112178000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5665547500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total   5777725500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    112218500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5665507000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    112178000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5665547500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total   5777725500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.240431                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.049939                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.240344                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.049940                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.052702                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282923                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282923                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.240431                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122817                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.240344                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122818                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.123995                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.240431                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122817                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.240344                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122818                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.123995                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         794179                       # Transaction distribution
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 048a31a06..5070249ec 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.216865                       # Number of seconds simulated
-sim_ticks                                216864820000                       # Number of ticks simulated
-final_tick                               216864820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.216744                       # Number of seconds simulated
+sim_ticks                                216744260000                       # Number of ticks simulated
+final_tick                               216744260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 114758                       # Simulator instruction rate (inst/s)
-host_op_rate                                   137779                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               91148248                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250616                       # Number of bytes of host memory used
-host_seconds                                  2379.25                       # Real time elapsed on the host
-sim_insts                                   273037856                       # Number of instructions simulated
-sim_ops                                     327812213                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 123383                       # Simulator instruction rate (inst/s)
+host_op_rate                                   148134                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               97944157                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314844                       # Number of bytes of host memory used
+host_seconds                                  2212.94                       # Real time elapsed on the host
+sim_insts                                   273037857                       # Number of instructions simulated
+sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            219008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            218944                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            266368                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               485376                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219008                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3422                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               485312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       218944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          218944                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3421                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7584                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1009883                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1228267                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2238150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1009883                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1009883                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1009883                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1228267                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2238150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7584                       # Number of read requests accepted
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1010149                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1228951                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2239100                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1010149                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1010149                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1010149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1228951                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2239100                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7583                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7584                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7583                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   485376                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   485312                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    485376                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    485312                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -46,8 +46,8 @@ system.physmem.perBankRdBursts::1                 843                       # Pe
 system.physmem.perBankRdBursts::2                 628                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 172                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 348                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 173                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 311                       # Per bank write bursts
@@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11                428                       # Pe
 system.physmem.perBankRdBursts::12                553                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                706                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                637                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                541                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                540                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    216864583500                       # Total gap between requests
+system.physmem.totGap                    216744023500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7584                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7583                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6625                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       899                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6627                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1521                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      318.190664                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.796192                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.520878                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            546     35.90%     35.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          355     23.34%     59.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          175     11.51%     70.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           75      4.93%     75.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           71      4.67%     80.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           52      3.42%     83.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           37      2.43%     86.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           29      1.91%     88.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          181     11.90%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1521                       # Bytes accessed per row activation
-system.physmem.totQLat                       53624000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 195824000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37920000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7070.68                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1519                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      318.314681                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     188.160813                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     331.826555                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            551     36.27%     36.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          356     23.44%     59.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          165     10.86%     70.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           80      5.27%     75.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           68      4.48%     80.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           50      3.29%     83.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           36      2.37%     85.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           26      1.71%     87.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          187     12.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1519                       # Bytes accessed per row activation
+system.physmem.totQLat                       54921500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 197102750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37915000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7242.71                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25820.68                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25992.71                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.24                       # Average system read bandwidth in MiByte/s
@@ -216,48 +216,48 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6058                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6057                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   79.88                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28595013.65                       # Average gap between requests
+system.physmem.avgGap                     28582885.86                       # Average gap between requests
 system.physmem.pageHitRate                      79.88                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5012280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2734875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  29952000                       # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy                    5027400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2743125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  29905200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14164413120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5663385765                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           125149854750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             145015352790                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.696011                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   208196147750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7241520000                       # Time in different power states
+system.physmem_0.refreshEnergy            14156276160                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5639665500                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           125095914000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             144929531385                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.684406                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   208108813000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7237360000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1425508750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1394961500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6486480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3539250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  29031600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6433560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3510375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28984800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14164413120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5827279860                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           125006088000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             145036838310                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.795085                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   207953796500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7241520000                       # Time in different power states
+system.physmem_1.refreshEnergy            14156276160                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5856004440                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           124906143000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             144957352335                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.812768                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   207790968250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7237360000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1667592250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1713539250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                33219593                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17177082                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1581285                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17974979                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                15661112                       # Number of BTB hits
+system.cpu.branchPred.lookups                33185861                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17151464                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1557357                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17401044                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                15621725                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.127290                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6612086                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             89.774642                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6610647                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,26 +377,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        433729640                       # number of cpu cycles simulated
+system.cpu.numCycles                        433488520                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   273037856                       # Number of instructions committed
-system.cpu.committedOps                     327812213                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4054236                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   273037857                       # Number of instructions committed
+system.cpu.committedOps                     327812214                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       4013329                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.588533                       # CPI: cycles per instruction
-system.cpu.ipc                               0.629512                       # IPC: instructions per cycle
-system.cpu.tickCycles                       430193126                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3536514                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.587650                       # CPI: cycles per instruction
+system.cpu.ipc                               0.629862                       # IPC: instructions per cycle
+system.cpu.tickCycles                       429966989                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3521531                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements              1354                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.769078                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168782221                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3085.753926                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168769445                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37415.699623                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37412.867435                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3085.769078                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.753362                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753362                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.753926                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.753358                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753358                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
@@ -404,54 +404,54 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           12
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         337583521                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        337583521                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86649433                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86649433                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82047458                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82047458                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        63540                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         63540                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         337557971                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337557971                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86636657                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86636657                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82047457                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82047457                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        63541                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         63541                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168696891                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168696891                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168760431                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168760431                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     168684114                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168684114                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168747655                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168747655                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         2059                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          2059                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5219                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5219                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         5220                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5220                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            6                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            6                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         7278                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7278                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7284                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7284                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    136977706                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    136977706                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    400661500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    400661500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    537639206                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    537639206                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    537639206                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    537639206                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86651492                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86651492                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         7279                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7279                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7285                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7285                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    137443456                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    137443456                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    400907250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    400907250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    538350706                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    538350706                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    538350706                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    538350706                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86638716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86638716                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        63546                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        63546                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        63547                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        63547                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168704169                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168704169                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168767715                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168767715                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    168691393                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168691393                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168754940                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168754940                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
@@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73871.833746                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73810.983800                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73959.432065                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73898.518325                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks         1010                       # nu
 system.cpu.dcache.writebacks::total              1010                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          422                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          422                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2349                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2349                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2771                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2771                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2771                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2771                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2350                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2350                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2772                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2772                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2772                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2772                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1637                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total         1637                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
@@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4507
 system.cpu.dcache.demand_mshr_misses::total         4507                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109140792                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    109140792                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    220213500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    220213500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109995542                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    109995542                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    220772750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    220772750                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       320750                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       320750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329354292                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    329354292                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    329675042                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    329675042                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    330768292                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    330768292                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    331089042                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    331089042                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             36897                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1924.852858                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            73252007                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             38834                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1886.285394                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             36918                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1924.846019                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            73120141                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             38855                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1881.872114                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1924.852858                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939870                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939870                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1924.846019                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939866                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939866                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1487                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          274                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1490                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146620518                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146620518                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     73252007                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        73252007                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      73252007                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         73252007                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     73252007                       # number of overall hits
-system.cpu.icache.overall_hits::total        73252007                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38835                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38835                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38835                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38835                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38835                       # number of overall misses
-system.cpu.icache.overall_misses::total         38835                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    728387498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    728387498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    728387498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    728387498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    728387498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    728387498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     73290842                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     73290842                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     73290842                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     73290842                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     73290842                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     73290842                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000530                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000530                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000530                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000530                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000530                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000530                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18755.954629                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18755.954629                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18755.954629                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18755.954629                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18755.954629                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18755.954629                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146356849                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146356849                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     73120141                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        73120141                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      73120141                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         73120141                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     73120141                       # number of overall hits
+system.cpu.icache.overall_hits::total        73120141                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        38856                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         38856                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        38856                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          38856                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        38856                       # number of overall misses
+system.cpu.icache.overall_misses::total         38856                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    728255248                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    728255248                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    728255248                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    728255248                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    728255248                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    728255248                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     73158997                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     73158997                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     73158997                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     73158997                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     73158997                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     73158997                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000531                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000531                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000531                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000531                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000531                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000531                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18742.414247                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18742.414247                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38835                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        38835                       # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    668686502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    668686502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    668686502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    668686502                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total    668686502                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000530                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17218.655903                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17218.655903                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17218.655903                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17218.655903                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17218.655903                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 17205.251493                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.tagsinuse         4197.194738                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              35781                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5646                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.337407                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4198.154832                       # Cycle average of tags in use
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-system.cpu.l2cache.tags.occ_blocks::writebacks   353.722054                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3165.177954                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   678.294730                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5646                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1252                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172302                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           363364                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          363364                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        35411                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77596.666667                       # average ReadReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -725,104 +725,104 @@ system.cpu.l2cache.demand_mshr_hits::total           44                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
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-system.cpu.l2cache.overall_mshr_misses::total         7584                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    215060000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     85447750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    300507750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    181443000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    181443000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    215060000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    266890750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    481950750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    215060000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    266890750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    481950750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.088116                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total         7583                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    214664750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     86513250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    301178000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    181997750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    181997750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    214664750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    268511000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    483175750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    214664750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    268511000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    483175750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.088043                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116859                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116774                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088116                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088043                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.174964                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088116                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.174856                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088043                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.174964                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62846.288720                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65327.025994                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63532.293869                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63574.982481                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63574.982481                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62846.288720                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64125.600673                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63548.358386                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62846.288720                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64125.600673                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63548.358386                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.174856                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          40476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         40475                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq          40497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         40496                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback         1010                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77669                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77711                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10032                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             87701                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2485376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             87743                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2486720                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            2838720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            2840064                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        44356                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        44377                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3              44356    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3              44377    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          44356                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       23188000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          44377                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       23198500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      58975998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      59005248                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       7577458                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                4730                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4730                       # Transaction distribution
+system.membus.trans_dist::ReadReq                4729                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4729                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15168                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15168                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  485376                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15166                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15166                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  485312                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7584                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7583                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7584    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7583    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7584                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8969000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7583                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             8950500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           40262750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           40258250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index bf0686636..4230ac10b 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,46 +1,46 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.112554                       # Number of seconds simulated
-sim_ticks                                112553814500                       # Number of ticks simulated
-final_tick                               112553814500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.112557                       # Number of seconds simulated
+sim_ticks                                112556618500                       # Number of ticks simulated
+final_tick                               112556618500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 123079                       # Simulator instruction rate (inst/s)
-host_op_rate                                   147770                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50736526                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257068                       # Number of bytes of host memory used
-host_seconds                                  2218.40                       # Real time elapsed on the host
-sim_insts                                   273037219                       # Number of instructions simulated
-sim_ops                                     327811601                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  95501                       # Simulator instruction rate (inst/s)
+host_op_rate                                   114659                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39369115                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319836                       # Number of bytes of host memory used
+host_seconds                                  2859.01                       # Real time elapsed on the host
+sim_insts                                   273037220                       # Number of instructions simulated
+sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            187136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            114176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       167616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               468928                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       187136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          187136                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2924                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1784                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         2619                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7327                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1662636                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1014413                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher      1489208                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4166256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1662636                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1662636                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1662636                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1014413                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher      1489208                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4166256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7327                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            187072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            117696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       162752                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               467520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       187072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          187072                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2923                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1839                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         2543                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7305                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1662026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1045660                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher      1445957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4153643                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1662026                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1662026                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1662026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1045660                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher      1445957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4153643                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7305                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7327                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7305                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   468928                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   467520                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    468928                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    467520                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -51,13 +51,13 @@ system.physmem.perBankRdBursts::2                 601                       # Pe
 system.physmem.perBankRdBursts::3                 520                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 444                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 346                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 153                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 255                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 146                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 247                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 219                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                315                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                411                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                547                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                540                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                678                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                615                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                555                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    112553656000                       # Total gap between requests
+system.physmem.totGap                    112556460000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7327                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7305                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,22 +94,22 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3994                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       473                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       246                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       203                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       150                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       184                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4013                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1460                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       289                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       191                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       168                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       186                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        52                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       17                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
@@ -190,78 +190,78 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1397                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      334.064424                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     193.482672                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     348.087808                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            504     36.08%     36.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          315     22.55%     58.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          145     10.38%     69.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           78      5.58%     74.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           51      3.65%     78.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           45      3.22%     81.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           28      2.00%     83.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           21      1.50%     84.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          210     15.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1397                       # Bytes accessed per row activation
-system.physmem.totQLat                       96387273                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 233768523                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     36635000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13155.08                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1395                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      333.121147                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     192.861490                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.787983                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            501     35.91%     35.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          324     23.23%     59.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          138      9.89%     69.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           72      5.16%     74.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           60      4.30%     78.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           40      2.87%     81.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           25      1.79%     83.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           33      2.37%     85.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          202     14.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1395                       # Bytes accessed per row activation
+system.physmem.totQLat                      103629565                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 240598315                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     36525000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       14186.11                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31905.08                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.17                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32936.11                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.15                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.17                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.15                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.37                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5921                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5900                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.81                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.77                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15361492.56                       # Average gap between requests
-system.physmem.pageHitRate                      80.81                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4883760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2664750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  28688400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     15408139.63                       # Average gap between requests
+system.physmem.pageHitRate                      80.77                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    4800600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2619375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  28509000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             7351234800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3253381020                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            64676459250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              75317311980                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.186805                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   107592163396                       # Time in different power states
+system.physmem_0.actBackEnergy             3210095790                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            64714428750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              75311688315                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.136839                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   107655127862                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      3758300000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1200480604                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1137230638                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5654880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3085500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  28158000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    5692680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3106125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28033200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             7351234800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3298234320                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            64637123250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              75323490750                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.241613                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   107525247142                       # Time in different power states
+system.physmem_1.actBackEnergy             3321763065                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            64616466750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              75326296620                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.266714                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   107490739638                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      3758300000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1266984612                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1301464112                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37745757                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20165080                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1746215                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18666199                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                17299874                       # Number of BTB hits
+system.cpu.branchPred.lookups                37745745                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          20165036                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1746193                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18664433                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                17299757                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.680218                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7225607                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             92.688361                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7225644                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               3815                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -381,95 +381,95 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        225107630                       # number of cpu cycles simulated
+system.cpu.numCycles                        225113238                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12251626                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      334050460                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37745757                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24525481                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     210773788                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3510701                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1259                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles         2425                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  89095014                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 21830                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          224784448                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.802641                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.228554                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12251417                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      334051298                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37745745                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24525401                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     210778013                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3510671                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1214                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles         2374                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  89095174                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 21831                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          224788353                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.802613                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.228565                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 51100209     22.73%     22.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42897495     19.08%     41.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 30052167     13.37%     55.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                100734577     44.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 51103569     22.73%     22.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42898008     19.08%     41.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 30051948     13.37%     55.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                100734828     44.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            224784448                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.167679                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.483959                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 27670459                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63847459                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 108576617                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              23069322                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1620591                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6880031                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                135198                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              363530052                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               6167703                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1620591                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 44985233                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                17899875                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         341878                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 113387886                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46548985                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              355747640                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               2899285                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               6598470                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 195112                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7751940                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               21223571                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents          2892429                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           403401871                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2533892950                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        350207607                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         194891234                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            224788353                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.167674                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.483926                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 27670582                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63851253                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 108576447                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              23069494                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1620577                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6880022                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                135197                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              363530011                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               6168132                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1620577                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 44985380                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                17900890                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         342489                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 113387887                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              46551130                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              355747905                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               2899336                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               6599141                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 195125                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7751977                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               21225499                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents          2892433                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           403402217                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2533894130                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        350207887                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         194891394                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230051                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31171820                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 31172166                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts              17015                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts          17024                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  55320329                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             92416671                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            88482299                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1659115                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1844729                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  353235129                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  55319848                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             92416628                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            88482470                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1658909                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1843123                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  353235356                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded               28024                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 346404668                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           2300304                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25451552                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     73599170                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 346405014                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           2300418                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        25451778                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     73600174                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved           5904                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     224784448                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.541053                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.099675                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     224788353                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.541027                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.099686                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            40431348     17.99%     17.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            78272117     34.82%     52.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            61035980     27.15%     79.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            34788778     15.48%     95.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9595638      4.27%     99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5              651817      0.29%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                8770      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            40435382     17.99%     17.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            78271933     34.82%     52.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            61035531     27.15%     79.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34789384     15.48%     95.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9595504      4.27%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5              651863      0.29%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                8756      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       224784448                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       224788353                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9471276      7.62%      7.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   7330      0.01%      7.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9471637      7.62%      7.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   7328      0.01%      7.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.63% # attempts to use FU when none available
@@ -488,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.63% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            257049      0.21%      7.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            257062      0.21%      7.83% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp            126990      0.10%      7.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt             92940      0.07%      8.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv             68000      0.05%      8.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           719474      0.58%      8.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult           316340      0.25%      8.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        682824      0.55%      9.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            126985      0.10%      7.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             92941      0.07%      8.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv             68002      0.05%      8.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           719490      0.58%      8.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult           316341      0.25%      8.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        682827      0.55%      9.45% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               53604156     43.13%     52.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              58946138     47.43%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               53603507     43.13%     52.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              58947270     47.43%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             110656025     31.94%     31.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2148357      0.62%     32.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             110656004     31.94%     31.94% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2148356      0.62%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.56% # Type of FU issued
@@ -522,105 +522,105 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.56% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6798490      1.96%     34.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6798499      1.96%     34.53% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8668315      2.50%     37.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3332477      0.96%     37.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1592461      0.46%     38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20930112      6.04%     44.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7182294      2.07%     46.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148952      2.06%     48.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8668326      2.50%     37.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3332485      0.96%     37.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1592467      0.46%     38.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20930113      6.04%     44.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7182308      2.07%     46.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148959      2.06%     48.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     48.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             91886799     26.53%     75.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            85885100     24.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             91886991     26.53%     75.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            85885220     24.79%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              346404668                       # Type of FU issued
-system.cpu.iq.rate                           1.538840                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   124292517                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.358807                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          756686876                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         251708205                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    223263085                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           287499729                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          127016687                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    117424806                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              303164482                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               167532703                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5066223                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              346405014                       # Type of FU issued
+system.cpu.iq.rate                           1.538803                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   124293390                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.358809                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          756692141                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         251708637                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    223263072                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           287500048                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          127016707                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    117424886                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              303165485                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               167532919                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5066153                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6684396                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13685                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        10191                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6106682                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6684353                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13689                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        10190                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6106853                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       154303                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        567640                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       154467                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        567717                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1620591                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2121620                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                330440                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           353264020                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                1620577                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2121612                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                331103                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           353264247                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              92416671                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             88482299                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts              92416628                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             88482470                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts              16991                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   8046                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                336925                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          10191                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1220622                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       439103                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1659725                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             342414286                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              90666955                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3990382                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                   8045                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                337585                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          10190                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1220609                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       439082                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1659691                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             342414524                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              90667106                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3990490                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                           867                       # number of nop insts executed
-system.cpu.iew.exec_refs                    175255989                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31752931                       # Number of branches executed
-system.cpu.iew.exec_stores                   84589034                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.521114                       # Inst execution rate
-system.cpu.iew.wb_sent                      340946352                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     340687891                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 153731206                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 266896125                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    175256113                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31752933                       # Number of branches executed
+system.cpu.iew.exec_stores                   84589007                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.521077                       # Inst execution rate
+system.cpu.iew.wb_sent                      340946411                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     340687958                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 153730891                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 266895127                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.513444                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.575996                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.513407                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.575997                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23077118                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        23077429                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1611456                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    221059297                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.482915                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.052167                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1611435                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    221063225                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.482889                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.052142                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     87356112     39.52%     39.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     70369552     31.83%     71.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20804455      9.41%     80.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13442204      6.08%     86.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8808979      3.98%     90.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4514912      2.04%     92.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2991653      1.35%     94.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2424695      1.10%     95.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10346735      4.68%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     87359166     39.52%     39.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     70369846     31.83%     71.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20804571      9.41%     80.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13442893      6.08%     86.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8809424      3.99%     90.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4514904      2.04%     92.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2991184      1.35%     94.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2424669      1.10%     95.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10346568      4.68%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    221059297                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            273037831                       # Number of instructions committed
-system.cpu.commit.committedOps              327812213                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    221063225                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            273037832                       # Number of instructions committed
+system.cpu.commit.committedOps              327812214                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      168107892                       # Number of memory references committed
 system.cpu.commit.loads                      85732275                       # Number of loads committed
 system.cpu.commit.membars                       11033                       # Number of memory barriers committed
-system.cpu.commit.branches                   30563525                       # Number of branches committed
+system.cpu.commit.branches                   30563526                       # Number of branches committed
 system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 258331704                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              6225114                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        104312486     31.82%     31.82% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        104312487     31.82%     31.82% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult         2145917      0.65%     32.48% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     32.48% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     32.48% # Class of committed instruction
@@ -653,95 +653,95 @@ system.cpu.commit.op_class_0::MemRead        85732275     26.15%     74.87% # Cl
 system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         327812213                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              10346735                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    561599370                       # The number of ROB reads
-system.cpu.rob.rob_writes                   705507733                       # The number of ROB writes
-system.cpu.timesIdled                           50679                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          323182                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   273037219                       # Number of Instructions Simulated
-system.cpu.committedOps                     327811601                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.824458                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.824458                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.212919                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.212919                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                331300708                       # number of integer regfile reads
-system.cpu.int_regfile_writes               136940215                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 187107289                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132177847                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                1297030245                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 80242169                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1182847920                       # number of misc regfile reads
+system.cpu.commit.op_class_0::total         327812214                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              10346568                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    561603777                       # The number of ROB reads
+system.cpu.rob.rob_writes                   705508335                       # The number of ROB writes
+system.cpu.timesIdled                           50687                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          324885                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   273037220                       # Number of Instructions Simulated
+system.cpu.committedOps                     327811602                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.824478                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.824478                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.212888                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.212888                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                331301011                       # number of integer regfile reads
+system.cpu.int_regfile_writes               136940115                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 187107432                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                132177980                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1297030870                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80242369                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1182848919                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           1533856                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.843197                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           163689216                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           511.842901                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           163689178                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1534368                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            106.681849                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          83394000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.843197                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999694                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999694                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            106.681825                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          84489000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.842901                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999693                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999693                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336633502                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336633502                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82631348                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82631348                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     80965582                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       80965582                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        70480                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         70480                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         336633512                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336633512                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     82631334                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        82631334                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     80965560                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       80965560                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        70478                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         70478                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10909                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10909                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     163596930                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        163596930                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    163667410                       # number of overall hits
-system.cpu.dcache.overall_hits::total       163667410                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2773213                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2773213                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1087117                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1087117                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     163596894                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        163596894                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    163667372                       # number of overall hits
+system.cpu.dcache.overall_hits::total       163667372                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2773234                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2773234                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1087139                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1087139                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            5                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            5                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3860330                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3860330                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3860348                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3860348                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  22349106216                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  22349106216                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8902471046                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8902471046                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      3860373                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3860373                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3860391                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3860391                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  22353219965                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  22353219965                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8921439031                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8921439031                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189750                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       189750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  31251577262                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  31251577262                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  31251577262                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  31251577262                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     85404561                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     85404561                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  31274658996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  31274658996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  31274658996                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  31274658996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     85404568                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     85404568                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        70498                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        70498                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        70496                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        70496                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10914                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10914                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167457260                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167457260                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167527758                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167527758                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032471                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032471                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    167457267                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167457267                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167527763                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167527763                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032472                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032472                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013249                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013249                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000255                       # miss rate for SoftPFReq accesses
@@ -752,36 +752,36 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.023053
 system.cpu.dcache.demand_miss_rate::total     0.023053                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.023043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.023043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8058.921625                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  8058.921625                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8189.064329                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8189.064329                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8060.343976                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  8060.343976                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8206.346227                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8206.346227                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        37950                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        37950                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  8095.571431                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  8095.571431                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  8095.533683                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  8095.533683                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  8101.460402                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  8101.460402                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  8101.422627                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  8101.422627                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       918314                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       920181                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          117385                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          117395                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.823095                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.838332                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       966341                       # number of writebacks
 system.cpu.dcache.writebacks::total            966341                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1459499                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1459499                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       866472                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       866472                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1459520                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1459520                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       866494                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       866494                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            5                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2325971                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2325971                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2325971                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2325971                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2326014                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2326014                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2326014                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2326014                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313714                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1313714                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220645                       # number of WriteReq MSHR misses
@@ -792,16 +792,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1534359
 system.cpu.dcache.demand_mshr_misses::total      1534359                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1534370                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1534370                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9969290033                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9969290033                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1717345064                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1717345064                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1161750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1161750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11686635097                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11686635097                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11687796847                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11687796847                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9970454284                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9970454284                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1720952041                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1720952041                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       709000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       709000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11691406325                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11691406325                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11692115325                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11692115325                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015382                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015382                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002689                       # mshr miss rate for WriteReq accesses
@@ -812,76 +812,76 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009163
 system.cpu.dcache.demand_mshr_miss_rate::total     0.009163                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009159                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.009159                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7588.630427                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7588.630427                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7783.294722                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7783.294722                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7616.623683                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  7616.623683                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7617.326230                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  7617.326230                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7589.516656                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7589.516656                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7799.642145                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7799.642145                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64454.545455                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64454.545455                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7619.733273                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  7619.733273                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7620.140726                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  7620.140726                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            715719                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.828705                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            88373879                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            716231                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            123.387397                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         326261250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.828705                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999665                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999665                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            715712                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.827844                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            88374047                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            716224                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            123.388838                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         326692250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.827844                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999664                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999664                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          244                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          245                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           69                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         178906226                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        178906226                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     88373879                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        88373879                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      88373879                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         88373879                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     88373879                       # number of overall hits
-system.cpu.icache.overall_hits::total        88373879                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       721118                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        721118                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       721118                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         721118                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       721118                       # number of overall misses
-system.cpu.icache.overall_misses::total        721118                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   5972962690                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   5972962690                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   5972962690                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   5972962690                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   5972962690                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   5972962690                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     89094997                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     89094997                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     89094997                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     89094997                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     89094997                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     89094997                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         178906541                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        178906541                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     88374047                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        88374047                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      88374047                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         88374047                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     88374047                       # number of overall hits
+system.cpu.icache.overall_hits::total        88374047                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       721111                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        721111                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       721111                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         721111                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       721111                       # number of overall misses
+system.cpu.icache.overall_misses::total        721111                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   5974650710                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   5974650710                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   5974650710                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   5974650710                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   5974650710                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   5974650710                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     89095158                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     89095158                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     89095158                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     89095158                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     89095158                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     89095158                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008094                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.008094                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.008094                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.008094                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.008094                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.008094                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8282.919980                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8282.919980                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8282.919980                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8282.919980                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8282.919980                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8282.919980                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        60262                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8285.341244                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8285.341244                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8285.341244                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8285.341244                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8285.341244                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8285.341244                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        59670                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           95                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2026                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2032                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    29.744324                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    29.365157                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    31.666667                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -891,291 +891,291 @@ system.cpu.icache.demand_mshr_hits::cpu.inst         4886
 system.cpu.icache.demand_mshr_hits::total         4886                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst         4886                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total         4886                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716232                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       716232                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       716232                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       716232                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       716232                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       716232                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5192936459                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   5192936459                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5192936459                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   5192936459                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5192936459                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   5192936459                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716225                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       716225                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       716225                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       716225                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       716225                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       716225                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5193352944                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   5193352944                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5193352944                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   5193352944                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5193352944                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   5193352944                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008039                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.008039                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008039                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.008039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7250.355275                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7250.355275                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7250.355275                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7250.355275                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7250.355275                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7250.355275                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7251.007636                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7251.007636                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7251.007636                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7251.007636                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7251.007636                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7251.007636                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       404550                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       404804                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          188                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       405309                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       405577                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          209                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        28140                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage        27975                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         5993.813794                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2806615                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             7301                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           384.415149                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         5974.758413                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2806551                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             7279                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           385.568210                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2575.149913                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2681.614006                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   610.589138                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   126.460737                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.157175                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.163673                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.037267                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.007719                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.365833                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          517                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         6784                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  2575.130596                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2680.592596                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   609.586326                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   109.448896                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.157173                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.163610                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.037206                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006680                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.364670                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         6782                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::2          344                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          135                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          115                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          775                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          126                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5743                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.031555                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.414062                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     52729252                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     52729252                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    175790791                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    119823752                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    295614543                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    175790791                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    119823752                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    178618011                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    474232554                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.004086                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000787                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001950                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003467                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003467                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004088                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.001163                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.002093                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004088                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.001163                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003648                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003648                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004086                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.001199                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.002117                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004086                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.001199                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.015603                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5806.877513                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  5806.877513                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.015565                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60140.537462                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64888.297872                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61381.170331                       # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5903.946949                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  5903.946949                       # average HardPFReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5806.877513                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65502.176398                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65502.176398                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60140.537462                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65157.015769                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62077.812474                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60140.537462                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65157.015769                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5903.946949                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13543.310315                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2029957                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2029957                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2029950                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2029950                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       966341                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        31800                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        31609                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       220643                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       220643                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1431558                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1431544                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4035081                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5466639                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45780864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5466625                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45780416                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    160045376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205826240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       32706                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3248743                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.009788                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.098451                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total          205825792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       32515                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3248545                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.009730                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.098161                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            3216943     99.02%     99.02% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              31800      0.98%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            3216936     99.03%     99.03% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              31609      0.97%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3248743                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2574812500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3248545                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2574809000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1075185997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1075177011                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2301792968                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2301798469                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                6562                       # Transaction distribution
-system.membus.trans_dist::ReadResp               6562                       # Transaction distribution
+system.membus.trans_dist::ReadReq                6500                       # Transaction distribution
+system.membus.trans_dist::ReadResp               6500                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               765                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              765                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14656                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14656                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       468928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  468928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               805                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              805                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14612                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14612                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       467520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  467520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7328                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7306                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7328    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7306    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7328                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9247379                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7306                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9226230                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           38369962                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           38266679                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 833e406c9..08c45e0cd 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,40 +1,40 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.201717                       # Number of seconds simulated
-sim_ticks                                201717313500                       # Number of ticks simulated
-final_tick                               201717313500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                201717314000                       # Number of ticks simulated
+final_tick                               201717314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1235958                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1483905                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              913112758                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308700                       # Number of bytes of host memory used
-host_seconds                                   220.91                       # Real time elapsed on the host
-sim_insts                                   273037594                       # Number of instructions simulated
-sim_ops                                     327811949                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 854590                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1026030                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              631341281                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304088                       # Number of bytes of host memory used
+host_seconds                                   319.51                       # Real time elapsed on the host
+sim_insts                                   273037595                       # Number of instructions simulated
+sim_ops                                     327811950                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        1394641092                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst        1394641096                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         480709216                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1875350308                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1394641092                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1394641092                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total           1875350312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   1394641096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1394641096                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      400047763                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         400047763                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          348660273                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          348660274                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data           86300511                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             434960784                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             434960785                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          82063567                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             82063567                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           6913839312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2383083572                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9296922884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      6913839312                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         6913839312                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1983209850                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1983209850                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          6913839312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          4366293422                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11280132734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           6913839315                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2383083566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9296922881                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6913839315                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6913839315                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1983209845                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1983209845                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6913839315                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          4366293411                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11280132726                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -153,11 +153,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        403434628                       # number of cpu cycles simulated
+system.cpu.numCycles                        403434629                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   273037594                       # Number of instructions committed
-system.cpu.committedOps                     327811949                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                   273037595                       # Number of instructions committed
+system.cpu.committedOps                     327811950                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             258331481                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_func_calls                    12448615                       # number of times a function call or return occured
@@ -168,18 +168,18 @@ system.cpu.num_int_register_reads          1174407516                       # nu
 system.cpu.num_int_register_writes          162499657                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            985884623                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads            985884626                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes            76361749                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     168107829                       # number of memory refs
 system.cpu.num_load_insts                    85732235                       # Number of load instructions
 system.cpu.num_store_insts                   82375594                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               403434627.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               403434628.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          30563490                       # Number of branches fetched
+system.cpu.Branches                          30563491                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 104312492     31.82%     31.82% # Class of executed instruction
+system.cpu.op_class::IntAlu                 104312493     31.82%     31.82% # Class of executed instruction
 system.cpu.op_class::IntMult                  2145905      0.65%     32.48% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     32.48% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     32.48% # Class of executed instruction
@@ -212,9 +212,9 @@ system.cpu.op_class::MemRead                 85732235     26.15%     74.87% # Cl
 system.cpu.op_class::MemWrite                82375594     25.13%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  327812144                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           434895827                       # Transaction distribution
-system.membus.trans_dist::ReadResp          434906722                       # Transaction distribution
+system.cpu.op_class::total                  327812145                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           434895828                       # Transaction distribution
+system.membus.trans_dist::ReadResp          434906723                       # Transaction distribution
 system.membus.trans_dist::WriteReq           82052672                       # Transaction distribution
 system.membus.trans_dist::WriteResp          82052672                       # Transaction distribution
 system.membus.trans_dist::SoftPFReq             54062                       # Transaction distribution
@@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp            54062                       # Tr
 system.membus.trans_dist::LoadLockedReq         10895                       # Transaction distribution
 system.membus.trans_dist::StoreCondReq          10895                       # Transaction distribution
 system.membus.trans_dist::StoreCondResp         10895                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    697320546                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    697320548                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    336728156                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             1034048702                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1394641092                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total             1034048704                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1394641096                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    880756979                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              2275398071                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              2275398075                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         517024351                       # Request fanout histogram
+system.membus.snoop_fanout::samples         517024352                       # Request fanout histogram
 system.membus.snoop_fanout::mean             2.674359                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.468614                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::2               168364078     32.56%     32.56% # Request fanout histogram
-system.membus.snoop_fanout::3               348660273     67.44%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::3               348660274     67.44%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               2                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               3                       # Request fanout histogram
-system.membus.snoop_fanout::total           517024351                       # Request fanout histogram
+system.membus.snoop_fanout::total           517024352                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 426aa68c6..eb13035d6 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.517235                       # Number of seconds simulated
-sim_ticks                                517235404500                       # Number of ticks simulated
-final_tick                               517235404500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                517235405500                       # Number of ticks simulated
+final_tick                               517235405500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 693666                       # Simulator instruction rate (inst/s)
-host_op_rate                                   832772                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1315500911                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318184                       # Number of bytes of host memory used
-host_seconds                                   393.19                       # Real time elapsed on the host
-sim_insts                                   272739285                       # Number of instructions simulated
-sim_ops                                     327433743                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 520716                       # Simulator instruction rate (inst/s)
+host_op_rate                                   625139                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              987510163                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313820                       # Number of bytes of host memory used
+host_seconds                                   523.78                       # Real time elapsed on the host
+sim_insts                                   272739286                       # Number of instructions simulated
+sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            166976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            270272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            166912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            270336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               437248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       166976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          166976                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2609                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               4223                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst       166912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          166912                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2608                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4224                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  6832                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               322824                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               522532                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               322700                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               522656                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total                  845356                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          322824                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             322824                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              322824                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              522532                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          322700                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             322700                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              322700                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              522656                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                 845356                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -147,11 +147,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                       1034470809                       # number of cpu cycles simulated
+system.cpu.numCycles                       1034470811                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   272739285                       # Number of instructions committed
-system.cpu.committedOps                     327433743                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                   272739286                       # Number of instructions committed
+system.cpu.committedOps                     327433744                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             258331537                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_func_calls                    12448615                       # number of times a function call or return occured
@@ -162,18 +162,18 @@ system.cpu.num_int_register_reads          1215888421                       # nu
 system.cpu.num_int_register_writes          162499693                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads           1242915500                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads           1242915503                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes            76361814                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     168107847                       # number of memory refs
 system.cpu.num_load_insts                    85732248                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1034470808.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1034470810.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          30563502                       # Number of branches fetched
+system.cpu.Branches                          30563503                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 104312543     31.82%     31.82% # Class of executed instruction
+system.cpu.op_class::IntAlu                 104312544     31.82%     31.82% # Class of executed instruction
 system.cpu.op_class::IntMult                  2145905      0.65%     32.48% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     32.48% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     32.48% # Class of executed instruction
@@ -206,14 +206,14 @@ system.cpu.op_class::MemRead                 85732248     26.15%     74.87% # Cl
 system.cpu.op_class::MemWrite                82375599     25.13%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  327812213                       # Class of executed instruction
+system.cpu.op_class::total                  327812214                       # Class of executed instruction
 system.cpu.dcache.tags.replacements              1332                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3078.445039                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3078.445034                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3078.445039                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  3078.445034                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.751573                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.751573                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
@@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data         4476                       # n
 system.cpu.dcache.demand_misses::total           4476                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         4479                       # number of overall misses
 system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     78354000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     78354000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     78396000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     78396000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data    157422500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total    157422500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    235776500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    235776500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    235776500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    235776500                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    235818500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    235818500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    235818500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    235818500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
@@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000027                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52675.714924                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52640.433132                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.098302                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 52685.098302                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 52649.810225                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 52649.810225                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4475
 system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75909500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     75909500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75951500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     75951500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    153114500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total    153114500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       160500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       160500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    229024000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    229024000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    229184500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    229184500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    229066000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    229066000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    229226500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    229226500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47380.848409                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47380.848409                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53500                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51187.932961                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51187.932961                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51189.481912                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51189.481912                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13796                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1766.007658                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           348644749                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1766.007655                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           348644750                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15603                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          22344.725309                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          22344.725373                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1766.007658                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1766.007655                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.862308                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.862308                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
@@ -362,44 +362,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2           26
 system.cpu.icache.tags.age_task_id_blocks_1024::3          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1524                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.882324                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         697336307                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        697336307                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    348644749                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       348644749                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     348644749                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        348644749                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    348644749                       # number of overall hits
-system.cpu.icache.overall_hits::total       348644749                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         697336309                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        697336309                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    348644750                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       348644750                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     348644750                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        348644750                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    348644750                       # number of overall hits
+system.cpu.icache.overall_hits::total       348644750                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        15603                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         15603                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        15603                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
 system.cpu.icache.overall_misses::total         15603                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    312524000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    312524000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    312524000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    312524000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    312524000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    312524000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    348660352                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    348660352                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    348660352                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    348660352                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    348660352                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    348660352                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    312482000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    312482000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    312482000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    312482000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    312482000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    312482000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    348660353                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    348660353                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    348660353                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    348660353                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    348660353                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    348660353                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20029.737871                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20029.737871                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.046081                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20027.046081                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.046081                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20027.046081                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.046081                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20027.046081                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -414,37 +414,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        15603
 system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    289119500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    289119500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    289119500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    289119500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    289119500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    289119500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    289077500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    289077500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    289077500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    289077500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    289077500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    289077500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18527.046081                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18527.046081                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18527.046081                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18527.046081                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18527.046081                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18527.046081                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3487.765017                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3487.765010                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              13310                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4882                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             2.726342                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   341.623060                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2408.427163                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   737.714793                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   341.623059                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.427162                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   738.714789                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.010426                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073499                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.022513                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073469                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.022544                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.106438                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4882                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
@@ -455,40 +455,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3543
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148987                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           176386                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          176386                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12994                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          239                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12995                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          238                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          13233                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks          998                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          998                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12994                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          255                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        12995                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          254                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total           13249                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12994                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          255                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst        12995                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          254                       # number of overall hits
 system.cpu.l2cache.overall_hits::total          13249                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2609                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         1367                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2608                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         1368                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total         3976                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         2856                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         2856                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2609                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         4223                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         2608                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         4224                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          6832                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2609                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         4223                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst         2608                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         4224                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         6832                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    137079500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     71954500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    137027000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     72007000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total    209034000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    150074500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total    150074500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    137079500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    222029000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    137027000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    222081500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total    359108500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    137079500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    222029000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    137027000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    222081500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total    359108500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        15603                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data         1606                       # number of ReadReq accesses(hits+misses)
@@ -503,27 +503,27 @@ system.cpu.l2cache.demand_accesses::total        20081                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst        15603                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4478                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total        20081                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.167211                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.851183                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.167147                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.851806                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.231042                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994429                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.994429                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167211                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.943055                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167147                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.943278                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.340222                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167211                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.943055                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167147                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.943278                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.340222                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.027607                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.695906                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.027607                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.112689                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.027607                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.112689                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -533,48 +533,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2609                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1367                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2608                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1368                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total         3976                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2856                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         2856                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2609                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         4223                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2608                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4224                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         6832                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2609                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         4223                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2608                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4224                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         6832                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    105665500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     55363500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    105625000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     55404000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total    161029000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115668000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115668000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    105665500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    171031500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    105625000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    171072000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total    276697000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    105665500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    171031500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    105625000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    171072000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total    276697000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.167211                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.851183                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.851806                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.231042                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994429                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167211                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943055                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.340222                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167211                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943055                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.340222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383436                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383436                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383436                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index ab62c741a..5cc3f8bc2 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,80 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.545057                       # Number of seconds simulated
-sim_ticks                                545056655500                       # Number of ticks simulated
-final_tick                               545056655500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.545048                       # Number of seconds simulated
+sim_ticks                                545048444500                       # Number of ticks simulated
+final_tick                               545048444500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 122221                       # Simulator instruction rate (inst/s)
-host_op_rate                                   150470                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              103982941                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247272                       # Number of bytes of host memory used
-host_seconds                                  5241.79                       # Real time elapsed on the host
-sim_insts                                   640655084                       # Number of instructions simulated
-sim_ops                                     788730743                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 131789                       # Simulator instruction rate (inst/s)
+host_op_rate                                   162250                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              112122004                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314432                       # Number of bytes of host memory used
+host_seconds                                  4861.21                       # Real time elapsed on the host
+sim_insts                                   640655085                       # Number of instructions simulated
+sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            164864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18429248                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18594112                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       164864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          164864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            164544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18429312                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18593856                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       164544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          164544                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2576                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             287957                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                290533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2571                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             287958                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                290529                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               302471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             33811619                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34114090                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          302471                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             302471                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7761160                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7761160                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7761160                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              302471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            33811619                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41875251                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        290533                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               301889                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             33812246                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34114135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          301889                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             301889                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7761277                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7761277                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7761277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              301889                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            33812246                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41875412                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        290529                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      290533                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      290529                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18574784                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19328                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18594112                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18574016                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19840                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228992                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18593856                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      302                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      310                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18287                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18141                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18224                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18184                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18267                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18318                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18100                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17916                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               17940                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               17966                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18025                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18111                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18143                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18269                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18078                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18262                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4173                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4136                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4223                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18284                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18137                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18223                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18185                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18266                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18315                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18094                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17909                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               17941                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               17963                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18019                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18118                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18147                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18275                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18266                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4147                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4226                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4225                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4094                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4093                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4090                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4090                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    545056561000                       # Total gap between requests
+system.physmem.totGap                    545048350000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  290533                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  290529                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,8 +97,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    289840                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       375                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    289827                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       376                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,19 +144,19 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      967                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      967                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4010                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     4010                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4010                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4009                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4009                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     4009                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                     4009                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4010                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                     4009                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                     4009                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     4009                       # What write queue length does an incoming req see
@@ -193,42 +193,44 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       112303                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      203.039278                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     132.213865                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     254.441282                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          47271     42.09%     42.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43737     38.95%     81.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8997      8.01%     89.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1907      1.70%     90.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          490      0.44%     91.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          737      0.66%     91.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          726      0.65%     92.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          505      0.45%     92.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7933      7.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         112303                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       112309                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      203.026151                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     132.211216                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     254.422571                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          47277     42.10%     42.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43772     38.97%     81.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8960      7.98%     89.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1911      1.70%     90.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          490      0.44%     91.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          736      0.66%     91.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          729      0.65%     92.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          499      0.44%     92.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7935      7.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         112309                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          4009                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.526066                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.050433                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      507.549530                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.524570                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.056534                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      507.518625                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023           4006     99.93%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            4009                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          4009                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.481417                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.460113                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.855134                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3044     75.93%     75.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                965     24.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.482415                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.461068                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.856030                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3042     75.88%     75.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1      0.02%     75.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                965     24.07%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4009                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2738025750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8179857000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1451155000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9433.95                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     2724193250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8165799500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1451095000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9386.68                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28183.95                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28136.68                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          34.08                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           7.76                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       34.11                       # Average system read bandwidth in MiByte/s
@@ -238,49 +240,49 @@ system.physmem.busUtil                           0.33                       # Da
 system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.96                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     193900                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50093                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        21.79                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     193908                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50072                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   66.81                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1528348.80                       # Average gap between requests
+system.physmem.writeRowHitRate                  75.75                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1528342.92                       # Average gap between requests
 system.physmem.pageHitRate                      68.47                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  424055520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  231379500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1134369600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215570160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            35600217120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           106906564890                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           233254311000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             377766467790                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              693.081659                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   387327017750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18200520000                       # Time in different power states
+system.physmem_0.actEnergy                  423889200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  231288750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1134182400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                215628480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            35599708560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           106422668235                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           233674110000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             377701475625                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.972318                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   388027097500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18200260000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    139526544250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    138818528500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  424894680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  231837375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1129096800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212589360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            35600217120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           105911923725                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           234126803250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             377637362310                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              692.844791                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   388779883250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18200520000                       # Time in different power states
+system.physmem_1.actEnergy                  425113920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  231957000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1129245000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212556960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            35599708560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           106328346345                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           233756848500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             377683776285                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              692.939845                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   388162097500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18200260000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    138072943000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    138683202500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               155213668                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         105449696                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12879317                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90304208                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                82854286                       # Number of BTB hits
+system.cpu.branchPred.lookups               155052076                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         105344550                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12879569                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90401009                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                82966187                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.750194                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19341274                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             91.775731                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19284792                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               1316                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -400,37 +402,37 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1090113311                       # number of cpu cycles simulated
+system.cpu.numCycles                       1090096889                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   640655084                       # Number of instructions committed
-system.cpu.committedOps                     788730743                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      22623250                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   640655085                       # Number of instructions committed
+system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      22623818                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.701560                       # CPI: cycles per instruction
-system.cpu.ipc                               0.587696                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1030410775                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        59702536                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            778141                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.460106                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378456342                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782237                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.812888                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.701535                       # CPI: cycles per instruction
+system.cpu.ipc                               0.587705                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1030366439                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        59730450                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            778156                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.460333                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378456871                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782252                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.804287                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         802330000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.460106                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.460333                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999136                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999136                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          963                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          962                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         1339                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1594                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1593                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759397955                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759397955                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    249627614                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249627614                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses         759399046                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759399046                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    249628143                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249628143                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         3485                       # number of SoftPFReq hits
@@ -439,30 +441,30 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739
 system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     378441379                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378441379                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    378444864                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378444864                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       713664                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        713664                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data     378441908                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378441908                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    378445393                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378445393                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       713673                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        713673                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       851376                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         851376                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       851517                       # number of overall misses
-system.cpu.dcache.overall_misses::total        851517                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24697977718                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24697977718                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10190251750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10190251750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34888229468                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34888229468                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34888229468                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34888229468                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250341278                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250341278                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       851385                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         851385                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       851526                       # number of overall misses
+system.cpu.dcache.overall_misses::total        851526                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  24678796218                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  24678796218                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10203720250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10203720250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34882516468                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34882516468                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34882516468                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34882516468                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250341816                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250341816                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         3626                       # number of SoftPFReq accesses(hits+misses)
@@ -471,10 +473,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739
 system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    379292755                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379292755                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    379296381                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379296381                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    379293293                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379293293                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    379296919                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379296919                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002851                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.002851                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
@@ -485,14 +487,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002245
 system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002245                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.290991                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.290991                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.638660                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40978.638660                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40971.853137                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40971.853137                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34579.977410                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34579.977410                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74094.634091                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74094.634091                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40971.495232                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40971.495232                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.710964                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40964.710964                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -503,34 +505,34 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        91420                       # number of writebacks
 system.cpu.dcache.writebacks::total             91420                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          888                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          888                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          882                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          882                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        69278                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        69278                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        69278                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        69278                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712776                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712776                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data        69272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        69272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        69272                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        69272                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712791                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712791                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       782098                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782098                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       782237                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782237                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23542622277                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23542622277                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5045531250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5045531250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       782113                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782113                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       782252                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782252                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23523501277                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23523501277                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5052240750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5052240750                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1719000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1719000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28588153527                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28588153527                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28589872527                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28589872527                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28575742027                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28575742027                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28577461027                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28577461027                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -541,69 +543,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33029.482302                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33029.482302                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33001.961693                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33001.961693                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72880.770174                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72880.770174                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36553.160252                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36553.160252                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36548.862464                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 36548.862464                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36536.590016                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36536.590016                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36532.295254                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36532.295254                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             23596                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1712.064970                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           291953853                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             25347                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11518.280388                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             23595                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1710.136306                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           292011682                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             25344                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11521.925584                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1712.064970                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.835969                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.835969                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1710.136306                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.835027                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.835027                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1600                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         583983749                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        583983749                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    291953853                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       291953853                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     291953853                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        291953853                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    291953853                       # number of overall hits
-system.cpu.icache.overall_hits::total       291953853                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        25348                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         25348                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        25348                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          25348                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        25348                       # number of overall misses
-system.cpu.icache.overall_misses::total         25348                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    499948995                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    499948995                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    499948995                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    499948995                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    499948995                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    499948995                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    291979201                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    291979201                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    291979201                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    291979201                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    291979201                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    291979201                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1601                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.854004                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         584099398                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        584099398                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    292011682                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       292011682                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     292011682                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        292011682                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    292011682                       # number of overall hits
+system.cpu.icache.overall_hits::total       292011682                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        25345                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         25345                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        25345                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          25345                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        25345                       # number of overall misses
+system.cpu.icache.overall_misses::total         25345                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    498945745                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    498945745                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    498945745                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    498945745                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    498945745                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    498945745                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    292037027                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    292037027                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    292037027                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    292037027                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    292037027                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    292037027                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19723.409934                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19723.409934                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19723.409934                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19723.409934                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19723.409934                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19723.409934                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19686.160781                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19686.160781                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19686.160781                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19686.160781                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19686.160781                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19686.160781                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -612,123 +614,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25348                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        25348                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        25348                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        25348                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        25348                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        25348                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    460820505                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    460820505                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    460820505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    460820505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    460820505                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    460820505                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25345                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        25345                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        25345                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        25345                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        25345                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        25345                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    459825255                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    459825255                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    459825255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    459825255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    459825255                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    459825255                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18179.757969                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18179.757969                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18179.757969                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18179.757969                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18179.757969                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18179.757969                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18142.641744                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18142.641744                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18142.641744                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18142.641744                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18142.641744                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18142.641744                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           257753                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32573.758043                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             538992                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           290497                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.855413                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           257749                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32573.780035                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             539008                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           290493                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.855494                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2882.231572                       # Average occupied blocks per requestor
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -748,105 +750,105 @@ system.cpu.l2cache.demand_mshr_hits::total           32                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66003.071930                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101480                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368114                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.359746                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101480                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368114                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.359746                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63326.594090                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67062.223089                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67019.413961                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62348.129851                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62348.129851                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63326.594090                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65980.262747                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65956.770385                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63326.594090                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65980.262747                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65956.770385                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         738263                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        738262                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         738275                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        738274                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback        91420                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50695                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1655894                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1706589                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55914048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57536256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50689                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1655924                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1706613                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55915008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           57537024                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       899005                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       899017                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3             899005    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3             899017    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         899005                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      540922500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         899017                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      540928500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      38574495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      38568245                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1224002973                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1224009973                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              224442                       # Transaction distribution
-system.membus.trans_dist::ReadResp             224442                       # Transaction distribution
+system.membus.trans_dist::ReadReq              224438                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224438                       # Transaction distribution
 system.membus.trans_dist::Writeback             66098                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       647164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 647164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22824384                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22824384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       647156                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 647156                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22824128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22824128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            356631                       # Request fanout histogram
+system.membus.snoop_fanout::samples            356627                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  356631    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  356627    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              356631                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           731518000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              356627                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           732101500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1551221500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1551130500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 5365dab14..d04be0b82 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.409399                       # Number of seconds simulated
-sim_ticks                                409399480000                       # Number of ticks simulated
-final_tick                               409399480000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.409388                       # Number of seconds simulated
+sim_ticks                                409388341000                       # Number of ticks simulated
+final_tick                               409388341000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  92444                       # Simulator instruction rate (inst/s)
-host_op_rate                                   113811                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59075206                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244496                       # Number of bytes of host memory used
-host_seconds                                  6930.14                       # Real time elapsed on the host
-sim_insts                                   640649298                       # Number of instructions simulated
-sim_ops                                     788724957                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  75979                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93540                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48552243                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312124                       # Number of bytes of host memory used
+host_seconds                                  8431.91                       # Real time elapsed on the host
+sim_insts                                   640649299                       # Number of instructions simulated
+sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            232192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7025088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12938560                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             20195840                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       232192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          232192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4244864                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4244864                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3628                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             109767                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       202165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                315560                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66326                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66326                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               567153                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             17159494                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     31603753                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                49330400                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          567153                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             567153                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          10368513                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               10368513                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          10368513                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              567153                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            17159494                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     31603753                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               59698913                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        315560                       # Number of read requests accepted
-system.physmem.writeReqs                        66326                       # Number of write requests accepted
-system.physmem.readBursts                      315560                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66326                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 20177344                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18496                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4238912                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  20195840                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4244864                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      289                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      63                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             16                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               19910                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               19474                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               19822                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               19845                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               19720                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               20103                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               19622                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               19424                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               19577                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               19501                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              19475                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              19731                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              19558                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              20043                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              19546                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              19920                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4269                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4104                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4141                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4150                       # Per bank write bursts
+system.physmem.bytes_read::cpu.inst            226496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7024000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     12938624                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             20189120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       226496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          226496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4245888                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4245888                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3539                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             109750                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       202166                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                315455                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66342                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66342                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               553255                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             17157303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     31604769                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                49315327                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          553255                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             553255                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          10371297                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               10371297                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          10371297                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              553255                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            17157303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     31604769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               59686624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        315455                       # Number of read requests accepted
+system.physmem.writeReqs                        66342                       # Number of write requests accepted
+system.physmem.readBursts                      315455                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66342                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 20169536                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19584                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4238784                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  20189120                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4245888                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      306                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      81                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs             18                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               19899                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               19575                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               19715                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               19833                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               19635                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               20130                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               19631                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               19419                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               19547                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               19463                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              19540                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              19765                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              19604                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              19959                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              19457                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              19977                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4260                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4107                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4142                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4156                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                4244                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4227                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4228                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4097                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4154                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4150                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    409399425500                       # Total gap between requests
+system.physmem.totGap                    409388286500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  315560                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  315455                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66326                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    122658                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    117599                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6797                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6389                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8395                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      8262                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     10480                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4277                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     3294                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2442                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1850                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1337                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66342                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    122393                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    117234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     14139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      6795                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6485                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7459                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8460                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      8297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     10473                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4424                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     3291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2480                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1879                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1340                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,158 +148,165 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      589                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1000                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1792                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3281                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                     3720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4886                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4902                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4379                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::34                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       66                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::47                       60                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::49                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       63                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       136638                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      178.677557                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     128.806703                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     198.419690                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          53973     39.50%     39.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        57563     42.13%     81.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        14775     10.81%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1288      0.94%     93.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1420      1.04%     94.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1465      1.07%     95.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1207      0.88%     96.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1190      0.87%     97.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3757      2.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         136638                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4034                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        68.784581                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.732770                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      517.054396                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4014     99.50%     99.50% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            8      0.20%     99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            5      0.12%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-6143            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7168-8191            3      0.07%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::19456-20479            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4034                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4034                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.418691                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.384198                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.147646                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3405     84.41%     84.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  7      0.17%     84.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                450     11.16%     95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 75      1.86%     97.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 34      0.84%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 21      0.52%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 13      0.32%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 12      0.30%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  6      0.15%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  6      0.15%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  3      0.07%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4034                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9487812639                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15399143889                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1576355000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       30094.15                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       136711                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      178.525503                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     128.653130                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     198.190580                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54126     39.59%     39.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        57416     42.00%     81.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        14736     10.78%     92.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1353      0.99%     93.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1490      1.09%     94.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1455      1.06%     95.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1216      0.89%     96.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1169      0.86%     97.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3750      2.74%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         136711                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4038                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        65.701585                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.708310                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      449.952316                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            3996     98.96%     98.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023           21      0.52%     99.48% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            8      0.20%     99.68% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            4      0.10%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            1      0.02%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119            1      0.02%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5120-5631            1      0.02%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9728-10239            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-10751            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-14847            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15872-16383            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4038                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4038                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.401932                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.368431                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.138933                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3429     84.92%     84.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  6      0.15%     85.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                436     10.80%     95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 81      2.01%     97.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 33      0.82%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 20      0.50%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 10      0.25%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  9      0.22%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.02%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.05%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  6      0.15%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  2      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  2      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4038                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9474891317                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15383935067                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1575745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       30064.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  48844.15                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          49.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  48814.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          49.27                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          10.35                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       49.33                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       49.32                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                       10.37                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.47                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.39                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.86                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     218399                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     26454                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.27                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.92                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1072046.17                       # Average gap between requests
-system.physmem.pageHitRate                      64.18                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  517640760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  282442875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1231518600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216464400                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26739576240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            96784987680                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           160736987250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             286509617805                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              699.839198                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   266762765318                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13670540000                       # Time in different power states
+system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     218193                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     26465                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.23                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.94                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1072266.90                       # Average gap between requests
+system.physmem.pageHitRate                      64.15                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  518729400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  283036875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1231058400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                216470880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26739067680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            96374211480                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           161092645500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             286455220215                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              699.719632                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   267357168520                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13670280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    128960598682                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    128358277730                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  515168640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  281094000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1226955600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212725440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26739576240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96280028955                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           161179933500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             286435482375                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              699.658112                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   267502793659                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13670540000                       # Time in different power states
+system.physmem_1.actEnergy                  514715040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  280846500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1226721600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212706000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26739067680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            96210213075                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           161236503750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             286420773645                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              699.635490                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   267598080337                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13670280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    128220707341                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    128117581163                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               234006176                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         161868409                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15514584                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            121529948                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               108213709                       # Number of BTB hits
+system.cpu.branchPred.lookups               233960254                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         161822373                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15514618                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            121575796                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               108259792                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.042833                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25036783                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1300149                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             89.047159                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25036830                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1300193                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -418,84 +425,84 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                        818798961                       # number of cpu cycles simulated
+system.cpu.numCycles                        818776683                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           84078294                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1200783068                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   234006176                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133250492                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     718844861                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                31063585                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2466                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles           84080283                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1200690611                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   233960254                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          133296622                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     718833631                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                31063665                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2156                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3349                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 370656305                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                652882                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          818460793                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.833394                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.163540                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3279                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 370702181                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                652815                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          818451212                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.833527                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.163546                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                136795118     16.71%     16.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                223180654     27.27%     43.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 98074923     11.98%     55.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                360410098     44.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                136785734     16.71%     16.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                223134622     27.26%     43.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 98075130     11.98%     55.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                360455726     44.04%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            818460793                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.285792                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.466518                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                119991092                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             159658898                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 484662986                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              38629701                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15518116                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             25135087                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13824                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1248129900                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              39966537                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               15518116                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                176998470                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                78894904                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         210510                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 464956548                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              81882245                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1190637892                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              25457774                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              24955109                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2267146                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               41533192                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1699566                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1225425199                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5812490436                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1358169789                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          40876588                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            818451212                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.285744                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.466445                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                119992571                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             159648210                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 484662538                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              38629741                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               15518152                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             25181026                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13828                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1248127712                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              39967189                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               15518152                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                177000170                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                78888622                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         210704                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 464955823                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              81877741                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1190635480                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              25549977                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              24948594                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2267380                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               41534187                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1694220                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1225376851                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5812387634                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1358166964                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          40876517                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                350646969                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               7267                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                350598621                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               7265                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 108140115                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            366205100                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           236096667                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1646330                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5328678                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1168639452                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               12360                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1017122920                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          18523621                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       379926855                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1032577011                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            206                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     818460793                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.242727                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.084979                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                 108139964                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            366113107                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           236095924                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1592417                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5322589                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1168545112                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               12357                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1017136895                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          18518107                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       379832511                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1032101117                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            203                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     818451212                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.242758                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.084999                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           260810349     31.87%     31.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           227739162     27.83%     59.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           216495712     26.45%     86.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            97269955     11.88%     98.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            16145606      1.97%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           260801504     31.87%     31.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           227738074     27.83%     59.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           216482418     26.45%     86.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            97282888     11.89%     98.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            16146319      1.97%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                   9      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -503,43 +510,43 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       818460793                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       818451212                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                64512117     19.12%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  18144      0.01%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              155573719     46.11%     65.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite             116674794     34.58%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                64511713     19.12%     19.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  18146      0.01%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              155540663     46.10%     65.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite             116678902     34.58%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             456371749     44.87%     44.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             456370981     44.87%     44.87% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult              5195830      0.51%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
@@ -564,100 +571,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt         2550147      0.25%     46.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       11478997      1.13%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            322115143     31.67%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           215585851     21.20%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11478993      1.13%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            322128329     31.67%     78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           215587412     21.20%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1017122920                       # Type of FU issued
-system.cpu.iq.rate                           1.242213                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   337415663                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.331735                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3146768879                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1505031237                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    934270592                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            61877038                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           43565815                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total             1017136895                       # Type of FU issued
+system.cpu.iq.rate                           1.242264                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   337386313                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.331702                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3146752380                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1504842501                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    934271178                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            61877042                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           43565869                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses     26152443                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1320728240                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                33810343                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9960122                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses             1320712858                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                33810350                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          9960171                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    113964162                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1106                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18388                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    107116171                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    113872169                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1090                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18393                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    107115428                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2065787                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         22375                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2065797                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         22350                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15518116                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                35326355                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 41902                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1168657365                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               15518152                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                35325435                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 42128                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1168563023                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             366205100                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            236096667                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6620                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    109                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 45517                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18388                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15437362                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3784555                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19221917                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             974750423                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             303297711                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          42372497                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             366113107                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            236095924                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6617                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    102                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 45749                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18393                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15437385                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3784510                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19221895                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             974751162                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             303297617                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          42385733                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          5553                       # number of nop insts executed
-system.cpu.iew.exec_refs                    497763737                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                150613650                       # Number of branches executed
-system.cpu.iew.exec_stores                  194466026                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.190464                       # Inst execution rate
-system.cpu.iew.wb_sent                      963723367                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     960423035                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 536681402                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 893284482                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          5554                       # number of nop insts executed
+system.cpu.iew.exec_refs                    497765227                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                150613464                       # Number of branches executed
+system.cpu.iew.exec_stores                  194467610                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.190497                       # Inst execution rate
+system.cpu.iew.wb_sent                      963723916                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     960423621                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 536680580                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 893282190                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.172966                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       1.172998                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.600796                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       357409752                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       357407190                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15500908                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    767640271                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.027474                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.786859                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15500938                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    767630958                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.027486                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.786865                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    430932808     56.14%     56.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    172476946     22.47%     78.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     73566678      9.58%     88.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     31624021      4.12%     92.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8540196      1.11%     93.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14250754      1.86%     95.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7269409      0.95%     96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6618976      0.86%     97.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22360483      2.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    430922921     56.14%     56.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    172477665     22.47%     78.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     73566542      9.58%     88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     31624091      4.12%     92.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8540357      1.11%     93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14250533      1.86%     95.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7269334      0.95%     96.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6619169      0.86%     97.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22360346      2.91%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    767640271                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            640654410                       # Number of instructions committed
-system.cpu.commit.committedOps              788730069                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    767630958                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
+system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      381221434                       # Number of memory references committed
 system.cpu.commit.loads                     252240938                       # Number of loads committed
 system.cpu.commit.membars                        5740                       # Number of memory barriers committed
-system.cpu.commit.branches                  137364859                       # Number of branches committed
+system.cpu.commit.branches                  137364860                       # Number of branches committed
 system.cpu.commit.fp_insts                   24239771                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 682251399                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             19275340                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        385756793     48.91%     48.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        385756794     48.91%     48.91% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult         5173441      0.66%     49.56% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.56% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.56% # Class of committed instruction
@@ -690,382 +697,382 @@ system.cpu.commit.op_class_0::MemRead       252240938     31.98%     83.65% # Cl
 system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         788730069                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              22360483                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1891410858                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2343104087                       # The number of ROB writes
-system.cpu.timesIdled                          647398                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          338168                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   640649298                       # Number of Instructions Simulated
-system.cpu.committedOps                     788724957                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.278077                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.278077                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.782426                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.782426                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                995803851                       # number of integer regfile reads
-system.cpu.int_regfile_writes               567906934                       # number of integer regfile writes
+system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              22360346                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1891399121                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2343098694                       # The number of ROB writes
+system.cpu.timesIdled                          647342                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          325471                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
+system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.278042                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.278042                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.782447                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.782447                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                995806500                       # number of integer regfile reads
+system.cpu.int_regfile_writes               567906149                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                  31889841                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                 22959492                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                3794434058                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                384899317                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               715816288                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                3794435390                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                384898944                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               715817585                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2756182                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.932940                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           414226912                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2756694                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.262202                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2756184                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.932971                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           414226707                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2756696                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            150.262019                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         257775000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.932940                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.932971                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999869                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          222                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          224                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         839344268                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        839344268                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    286295518                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       286295518                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127916671                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127916671                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3177                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          3177                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         839343974                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        839343974                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    286295255                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       286295255                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127916705                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127916705                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3174                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3174                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     414212189                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414212189                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414215366                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414215366                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      3031489                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       3031489                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1034806                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1034806                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     414211960                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        414211960                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    414215134                       # number of overall hits
+system.cpu.dcache.overall_hits::total       414215134                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      3031607                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       3031607                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1034772                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1034772                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          647                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          647                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4066295                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4066295                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4066942                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4066942                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  35316006617                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  35316006617                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10004118304                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10004118304                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       202750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       202750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  45320124921                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  45320124921                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  45320124921                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  45320124921                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    289327007                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    289327007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      4066379                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4066379                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4067026                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4067026                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  35304231919                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  35304231919                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9981686625                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9981686625                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       189500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  45285918544                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  45285918544                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  45285918544                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  45285918544                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    289326862                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    289326862                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3824                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3824                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3821                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3821                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418278484                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418278484                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418282308                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418282308                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    418278339                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    418278339                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    418282160                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    418282160                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010478                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.010478                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008025                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.008025                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169195                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.169195                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169327                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.169327                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.009722                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.009722                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.009723                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.009723                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9667.626883                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9667.626883                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 11145.311622                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 11143.538541                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.385407                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.385407                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9646.266641                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  9646.266641                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.669392                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 11136.669392                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11134.897722                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 11134.897722                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       349732                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       343566                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            5194                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            5188                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    67.333847                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    66.223207                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       735277                       # number of writebacks
-system.cpu.dcache.writebacks::total            735277                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       996280                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       996280                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       313945                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       313945                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       735673                       # number of writebacks
+system.cpu.dcache.writebacks::total            735673                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       996398                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       996398                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       313907                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       313907                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1310225                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1310225                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1310225                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1310225                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1310305                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1310305                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1310305                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1310305                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035209                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      2035209                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720861                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       720861                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720865                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       720865                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2756070                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2756070                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2756711                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2756711                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23121613833                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23121613833                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5599042571                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5599042571                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5366500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5366500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28720656404                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28720656404                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28726022904                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28726022904                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      2756074                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2756074                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2756715                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2756715                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23117834450                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23117834450                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5596502782                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5596502782                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5770003                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5770003                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28714337232                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28714337232                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28720107235                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28720107235                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005590                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.167626                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.167626                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.167757                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.167757                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11360.805614                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11360.805614                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7767.159787                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7767.159787                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8372.074883                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8372.074883                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10420.873346                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10420.873346                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10420.396953                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10420.396953                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11358.948614                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11358.948614                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7763.593436                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7763.593436                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9001.564743                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9001.564743                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.565406                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.565406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.235920                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.235920                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           5169874                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.641329                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           365482216                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           5170384                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.687635                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         247770250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.641329                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997346                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997346                       # Average percentage of cache occupancy
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+system.cpu.icache.tags.tagsinuse           511.005918                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           365527993                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           5170483                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             70.695135                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         247768250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.005918                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998058                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          328                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         746482947                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        746482947                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    365482251                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       365482251                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     365482251                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        365482251                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    365482251                       # number of overall hits
-system.cpu.icache.overall_hits::total       365482251                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      5174022                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       5174022                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      5174022                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        5174022                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      5174022                       # number of overall misses
-system.cpu.icache.overall_misses::total       5174022                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  41654200685                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  41654200685                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  41654200685                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  41654200685                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  41654200685                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  41654200685                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    370656273                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    370656273                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    370656273                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    370656273                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    370656273                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    370656273                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013959                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013959                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013959                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013959                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013959                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013959                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8050.642360                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8050.642360                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8050.642360                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8050.642360                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8050.642360                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8050.642360                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        76485                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          100                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3140                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         746574800                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        746574800                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    365528016                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       365528016                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     365528016                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        365528016                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    365528016                       # number of overall hits
+system.cpu.icache.overall_hits::total       365528016                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      5174133                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       5174133                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      5174133                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        5174133                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      5174133                       # number of overall misses
+system.cpu.icache.overall_misses::total       5174133                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  41647669446                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  41647669446                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  41647669446                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  41647669446                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  41647669446                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  41647669446                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    370702149                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    370702149                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    370702149                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    370702149                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    370702149                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    370702149                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013958                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013958                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013958                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013958                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total     0.013958                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8049.207364                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8049.207364                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8049.207364                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8049.207364                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8049.207364                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8049.207364                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        75182                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          145                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3130                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    24.358280                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           20                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    24.019808                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           29                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3620                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3620                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3620                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3620                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3620                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3620                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5170402                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      5170402                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      5170402                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      5170402                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      5170402                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      5170402                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36439121179                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  36439121179                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36439121179                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  36439121179                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36439121179                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  36439121179                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013949                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013949                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013949                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013949                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013949                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013949                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7047.637917                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7047.637917                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7047.637917                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7047.637917                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7047.637917                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7047.637917                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3630                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3630                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3630                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_miss_latency::total  36431563436                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36431563436                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  36431563436                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36431563436                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  36431563436                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013948                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013948                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013948                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7046.038545                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7046.038545                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7046.038545                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7046.038545                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7046.038545                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7046.038545                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      1347058                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      1355234                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         7153                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      1347095                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      1354943                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         6866                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4790478                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           299258                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16361.552831                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7824313                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           315622                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            24.790138                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      13409363000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   738.976811                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   129.067019                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8785.583028                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6707.925973                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.045104                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007878                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.536229                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.409419                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.tagsinuse        16361.556320                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            7824806                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           315528                       # Sample count of references to valid blocks.
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+system.cpu.l2cache.tags.warmup_cycle      13406100000                       # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst   127.512594                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8771.582471                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6718.474196                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_percent::total     0.998630                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         6482                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         9882                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2          155                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1470                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4840                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024         9846                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           16                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2          171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1451                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4880                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2079                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7315                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.395630                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.603149                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        139634451                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       139634451                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      5166743                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1926167                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        7092910                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       735277                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       735277                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          225                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2089                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7268                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.397827                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.600952                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        139642343                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       139642343                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      5166932                       # number of ReadReq hits
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1074,143 +1081,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    230067036                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   7609571000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7839638036                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17078829649                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17078829649                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       248018                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       248018                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    114010508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    114010508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    230067036                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7723581508                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   7953648544                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    230067036                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7723581508                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17078829649                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  25032478193                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.053222                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015527                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.941176                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.941176                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001924                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001924                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039818                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014305                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039818                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.947368                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.947368                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001939                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001939                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039812                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014291                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039812                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.039817                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.039804                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395                       # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.715074                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65009.052275                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7206252                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7206251                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       735277                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       248818                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       720844                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       720844                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     10340787                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6248699                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16589486                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330904640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223486144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          554390784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      248834                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      8911208                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.027922                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.164749                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        7206353                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7206352                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       735673                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       248887                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           19                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           19                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       720846                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       720846                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     10340987                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6249103                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16590090                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330910976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223511616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          554422592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      248905                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      8911778                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.027928                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.164766                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            8662390     97.21%     97.21% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4             248818      2.79%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            8662891     97.21%     97.21% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4             248887      2.79%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        8911208                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5066472000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        8911778                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5067118500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    7756152507                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    7756291499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4138701196                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4138722865                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              314173                       # Transaction distribution
-system.membus.trans_dist::ReadResp             314173                       # Transaction distribution
-system.membus.trans_dist::Writeback             66326                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1387                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1387                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       697478                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 697478                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24440704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                24440704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq              314057                       # Transaction distribution
+system.membus.trans_dist::ReadResp             314057                       # Transaction distribution
+system.membus.trans_dist::Writeback             66342                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               18                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              18                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1398                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1398                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       697288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 697288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24435008                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                24435008                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            381902                       # Request fanout histogram
+system.membus.snoop_fanout::samples            381815                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  381902    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  381815    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              381902                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           746879857                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              381815                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           746604866                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1648874306                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1648190996                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index ba52b772d..790f4a782 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,40 +1,40 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.395727                       # Number of seconds simulated
-sim_ticks                                395726778000                       # Number of ticks simulated
-final_tick                               395726778000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                395726778500                       # Number of ticks simulated
+final_tick                               395726778500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1601804                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1972032                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              989420456                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309588                       # Number of bytes of host memory used
-host_seconds                                   399.96                       # Real time elapsed on the host
-sim_insts                                   640654410                       # Number of instructions simulated
-sim_ops                                     788730069                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1109777                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1366282                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              685499869                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303676                       # Number of bytes of host memory used
+host_seconds                                   577.28                       # Real time elapsed on the host
+sim_insts                                   640654411                       # Number of instructions simulated
+sim_ops                                     788730070                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        2573511592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst        2573511596                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        1144718516                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           3718230108                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   2573511592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      2573511592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total           3718230112                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   2573511596                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      2573511596                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      523317413                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         523317413                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          643377898                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          643377899                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data          250335238                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             893713136                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             893713137                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data         128957216                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total            128957216                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           6503253596                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2892699154                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9395952750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      6503253596                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         6503253596                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1322421029                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1322421029                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          6503253596                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          4215120183                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10718373779                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           6503253598                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2892699151                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9395952748                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6503253598                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6503253598                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1322421027                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1322421027                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6503253598                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          4215120178                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10718373776                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -153,11 +153,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                        791453557                       # number of cpu cycles simulated
+system.cpu.numCycles                        791453558                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   640654410                       # Number of instructions committed
-system.cpu.committedOps                     788730069                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                   640654411                       # Number of instructions committed
+system.cpu.committedOps                     788730070                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             682251400                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               24239771                       # Number of float alu accesses
 system.cpu.num_func_calls                    37261296                       # number of times a function call or return occured
@@ -168,18 +168,18 @@ system.cpu.num_int_register_reads          1320162254                       # nu
 system.cpu.num_int_register_writes          468423268                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads             28064643                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            21684311                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads           2369173291                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads           2369173294                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes           351919006                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     381221435                       # number of memory refs
 system.cpu.num_load_insts                   252240938                       # Number of load instructions
 system.cpu.num_store_insts                  128980497                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               791453556.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               791453557.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                         137364859                       # Number of branches fetched
+system.cpu.Branches                         137364860                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 385757466     48.91%     48.91% # Class of executed instruction
+system.cpu.op_class::IntAlu                 385757467     48.91%     48.91% # Class of executed instruction
 system.cpu.op_class::IntMult                  5173441      0.66%     49.56% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     49.56% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     49.56% # Class of executed instruction
@@ -212,9 +212,9 @@ system.cpu.op_class::MemRead                252240938     31.98%     83.65% # Cl
 system.cpu.op_class::MemWrite               128980497     16.35%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  788730743                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           893703777                       # Transaction distribution
-system.membus.trans_dist::ReadResp          893709516                       # Transaction distribution
+system.cpu.op_class::total                  788730744                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           893703778                       # Transaction distribution
+system.membus.trans_dist::ReadResp          893709517                       # Transaction distribution
 system.membus.trans_dist::WriteReq          128951477                       # Transaction distribution
 system.membus.trans_dist::WriteResp         128951477                       # Transaction distribution
 system.membus.trans_dist::SoftPFReq              3620                       # Transaction distribution
@@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp             3620                       # Tr
 system.membus.trans_dist::LoadLockedReq          5739                       # Transaction distribution
 system.membus.trans_dist::StoreCondReq           5739                       # Transaction distribution
 system.membus.trans_dist::StoreCondResp          5739                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1286755796                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1286755798                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    758584908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             2045340704                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2573511592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total             2045340706                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2573511596                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   1668035929                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              4241547521                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              4241547525                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples        1022670352                       # Request fanout histogram
+system.membus.snoop_fanout::samples        1022670353                       # Request fanout histogram
 system.membus.snoop_fanout::mean             2.629116                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.483042                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::2               379292454     37.09%     37.09% # Request fanout histogram
-system.membus.snoop_fanout::3               643377898     62.91%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::3               643377899     62.91%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               2                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               3                       # Request fanout histogram
-system.membus.snoop_fanout::total          1022670352                       # Request fanout histogram
+system.membus.snoop_fanout::total          1022670353                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index e078716d2..e0c0a3846 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,40 +1,40 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.043695                       # Number of seconds simulated
-sim_ticks                                1043695077500                       # Number of ticks simulated
-final_tick                               1043695077500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1043695078500                       # Number of ticks simulated
+final_tick                               1043695078500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 877071                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1077535                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1431720298                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317788                       # Number of bytes of host memory used
-host_seconds                                   728.98                       # Real time elapsed on the host
-sim_insts                                   639366786                       # Number of instructions simulated
-sim_ops                                     785501034                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 624059                       # Simulator instruction rate (inst/s)
+host_op_rate                                   766694                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1018706197                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313408                       # Number of bytes of host memory used
+host_seconds                                  1024.53                       # Real time elapsed on the host
+sim_insts                                   639366787                       # Number of instructions simulated
+sim_ops                                     785501035                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            113280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18428288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            113216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18428352                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             18541568                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       113280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          113280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       113216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          113216                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1770                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             287942                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               1769                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             287943                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                289712                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               108537                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             17656774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108476                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             17656835                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total                17765311                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108537                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108537                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108476                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108476                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks           4053168                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total                4053168                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks           4053168                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108537                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            17656774                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108476                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            17656835                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               21818480                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -154,11 +154,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       2087390155                       # number of cpu cycles simulated
+system.cpu.numCycles                       2087390157                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   639366786                       # Number of instructions committed
-system.cpu.committedOps                     785501034                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                   639366787                       # Number of instructions committed
+system.cpu.committedOps                     785501035                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             682251400                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               24239771                       # Number of float alu accesses
 system.cpu.num_func_calls                    37261296                       # number of times a function call or return occured
@@ -169,18 +169,18 @@ system.cpu.num_int_register_reads          1323974869                       # nu
 system.cpu.num_int_register_writes          468423268                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads             28064643                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            21684311                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads           3116296057                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads           3116296060                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes           351919006                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     381221435                       # number of memory refs
 system.cpu.num_load_insts                   252240938                       # Number of load instructions
 system.cpu.num_store_insts                  128980497                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               2087390154.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               2087390156.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                         137364859                       # Number of branches fetched
+system.cpu.Branches                         137364860                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 385757466     48.91%     48.91% # Class of executed instruction
+system.cpu.op_class::IntAlu                 385757467     48.91%     48.91% # Class of executed instruction
 system.cpu.op_class::IntMult                  5173441      0.66%     49.56% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     49.56% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     49.56% # Class of executed instruction
@@ -213,14 +213,14 @@ system.cpu.op_class::MemRead                252240938     31.98%     83.65% # Cl
 system.cpu.op_class::MemWrite               128980497     16.35%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  788730743                       # Class of executed instruction
+system.cpu.op_class::total                  788730744                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            778046                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4093.640588                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4093.640584                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378510311                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            782142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            483.940654                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         996414000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640588                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle         996415000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640584                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999424                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999424                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data       782004                       # n
 system.cpu.dcache.demand_misses::total         782004                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       782143                       # number of overall misses
 system.cpu.dcache.overall_misses::total        782143                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18582698000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18582698000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18582740000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18582740000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data   3677152000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total   3677152000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22259850000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22259850000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22259850000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22259850000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22259892000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22259892000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22259892000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22259892000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    250325879                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    250325879                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
@@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_miss_rate::total     0.002062                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002062                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002062                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.414780                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.414780                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28465.135728                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28460.076994                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.189436                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28465.189436                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.130692                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28460.130692                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       782003
 system.cpu.dcache.demand_mshr_misses::total       782003                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       782142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       782142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17513638000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17513638000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17513680000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17513680000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3573167500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total   3573167500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1682500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1682500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21086805500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21086805500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21088488000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  21088488000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21086847500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21086847500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21088530000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  21088530000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.395241                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.395241                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.174686                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.174686                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.533658                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.533658                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              8769                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1391.464503                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           643367691                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1391.464501                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           643367692                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             10208                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          63025.831799                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          63025.831897                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1391.464503                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1391.464501                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.679426                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.679426                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1439                       # Occupied blocks per task id
@@ -367,44 +367,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           43
 system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1339                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.702637                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1286766006                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1286766006                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    643367691                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       643367691                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     643367691                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        643367691                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    643367691                       # number of overall hits
-system.cpu.icache.overall_hits::total       643367691                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        1286766008                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1286766008                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    643367692                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       643367692                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     643367692                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        643367692                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    643367692                       # number of overall hits
+system.cpu.icache.overall_hits::total       643367692                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        10208                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         10208                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        10208                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          10208                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        10208                       # number of overall misses
 system.cpu.icache.overall_misses::total         10208                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    207116000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    207116000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    207116000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    207116000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    207116000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    207116000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    643377899                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    643377899                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    643377899                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    643377899                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    643377899                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    643377899                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    207074000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    207074000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    207074000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    207074000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    207074000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    207074000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    643377900                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    643377900                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    643377900                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    643377900                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    643377900                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    643377900                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000016                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000016                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20289.576803                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20289.576803                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20285.462382                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20285.462382                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20285.462382                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20285.462382                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20285.462382                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20285.462382                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -419,37 +419,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        10208
 system.cpu.icache.demand_mshr_misses::total        10208                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        10208                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        10208                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    191804000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    191804000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    191804000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    191804000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    191804000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    191804000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    191762000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    191762000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    191762000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    191762000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    191762000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    191762000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18785.462382                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18785.462382                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18785.462382                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18785.462382                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18785.462382                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18785.462382                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           256932                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32626.698188                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        32626.698157                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             524746                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           289675                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             1.811499                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2792.505447                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    49.080663                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks  2792.505444                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    49.076488                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.116225                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.085221                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001498                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.908969                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.908970                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.995688                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32743                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
@@ -460,40 +460,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        30967
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999237                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          7430286                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         7430286                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8438                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       490970                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8439                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       490969                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         499408                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks        91561                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total        91561                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         3230                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         3230                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8438                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       494200                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         8439                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       494199                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          502638                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8438                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       494200                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst         8439                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       494199                       # number of overall hits
 system.cpu.l2cache.overall_hits::total         502638                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1770                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       221849                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1769                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       221850                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total       223619                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66093                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66093                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1770                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       287942                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         1769                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       287943                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        289712                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1770                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       287942                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst         1769                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       287943                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       289712                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     92997000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11647316500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     92944500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11647369000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total  11740313500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3469929500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total   3469929500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     92997000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  15117246000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     92944500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  15117298500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total  15210243000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     92997000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  15117246000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     92944500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  15117298500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total  15210243000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        10208                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data       712819                       # number of ReadReq accesses(hits+misses)
@@ -508,27 +508,27 @@ system.cpu.l2cache.demand_accesses::total       792350                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst        10208                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       782142                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       792350                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.173393                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311228                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.173295                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311229                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.309282                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953407                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.953407                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.173393                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.368145                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.173295                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.368147                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.365636                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.173393                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.368145                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.173295                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.368147                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.365636                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.700961                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099842                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.700961                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010617                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.700961                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010617                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -540,48 +540,48 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1770                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221849                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1769                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221850                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total       223619                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1770                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       287942                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1769                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       287943                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       289712                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1770                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       287942                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1769                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       287943                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       289712                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     71689000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8984884500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     71648500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8984925000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total   9056573500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2676766500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2676766500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71689000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11661651000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71648500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11661691500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total  11733340000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71689000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11661651000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71648500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11661691500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total  11733340000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.173393                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311228                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311229                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.309282                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953407                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953407                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.173393                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368145                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368147                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.365636                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.173393                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368145                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368147                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.365636                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.261164                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.261164                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.261164                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index 6d11e3682..22befaf24 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,80 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.057738                       # Number of seconds simulated
-sim_ticks                                 57738195500                       # Number of ticks simulated
-final_tick                                57738195500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.057717                       # Number of seconds simulated
+sim_ticks                                 57716694500                       # Number of ticks simulated
+final_tick                                57716694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 113055                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144580                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               92047581                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250264                       # Number of bytes of host memory used
-host_seconds                                   627.26                       # Real time elapsed on the host
-sim_insts                                    70915127                       # Number of instructions simulated
-sim_ops                                      90690083                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 141604                       # Simulator instruction rate (inst/s)
+host_op_rate                                   181090                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              115249030                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314220                       # Number of bytes of host memory used
+host_seconds                                   500.80                       # Real time elapsed on the host
+sim_insts                                    70915128                       # Number of instructions simulated
+sim_ops                                      90690084                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            324352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7922944                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8247296                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       324352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          324352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            324096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7923392                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8247488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       324096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          324096                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      5372992                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           5372992                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5068                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             123796                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128864                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               5064                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             123803                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128867                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           83953                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                83953                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5617633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            137221885                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               142839518                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5617633                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5617633                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          93057844                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               93057844                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          93057844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5617633                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           137221885                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              235897362                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128864                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst              5615290                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            137280765                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               142896056                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5615290                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5615290                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          93092511                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               93092511                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          93092511                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5615290                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           137280765                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              235988567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128867                       # Number of read requests accepted
 system.physmem.writeReqs                        83953                       # Number of write requests accepted
-system.physmem.readBursts                      128864                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      128867                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      83953                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8246976                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5371008                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8247296                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                  8247040                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5371776                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8247488                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                5372992                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8158                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8374                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8229                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                8159                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8373                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8230                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                8170                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8316                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8318                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                8449                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                8089                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7971                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8070                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7642                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7819                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7972                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8072                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7639                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7818                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               7829                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7880                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7877                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7978                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8008                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5182                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7878                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7976                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8006                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5185                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                5285                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5155                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                5266                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5197                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5047                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5518                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5200                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5050                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                5033                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5088                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5087                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5254                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5143                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               5451                       # Pe
 system.physmem.perBankWrBursts::15               5225                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     57738161000                       # Total gap between requests
+system.physmem.totGap                     57716659500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128864                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128867                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  83953                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    116707                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    116721                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12117                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      615                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      635                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       12                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -193,99 +193,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38462                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      353.991784                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     215.320111                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.607526                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12100     31.46%     31.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8198     21.31%     52.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4148     10.78%     63.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2890      7.51%     71.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2484      6.46%     77.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1581      4.11%     81.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1319      3.43%     85.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1187      3.09%     88.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4555     11.84%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38462                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        38389                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      354.703274                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     215.932875                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.531195                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12049     31.39%     31.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8167     21.27%     52.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4156     10.83%     63.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2841      7.40%     70.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2531      6.59%     77.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1630      4.25%     81.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1300      3.39%     85.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1165      3.03%     88.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4550     11.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38389                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5156                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.974593                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      361.421207                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.991854                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      361.399783                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023           5153     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            5156                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          5156                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.276571                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.259351                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.782645                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4530     87.86%     87.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  9      0.17%     88.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                479      9.29%     97.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                112      2.17%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 15      0.29%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  8      0.16%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.278898                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.261929                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.774840                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4519     87.65%     87.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  7      0.14%     87.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                495      9.60%     97.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                111      2.15%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 19      0.37%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  3      0.06%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  2      0.04%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5156                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1653247250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4069353500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    644295000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12829.89                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     1645819000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4061944000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    644300000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12772.15                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31579.89                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         142.83                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          93.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      142.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       93.06                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31522.15                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         142.89                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          93.07                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      142.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       93.09                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.84                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.73                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112168                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     62144                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        23.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112172                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     62224                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   87.05                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                       271304.27                       # Average gap between requests
-system.physmem.pageHitRate                      81.91                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  151283160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   82545375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 512694000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                272322000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3770972400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11678597190                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            24396798750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              40865212875                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              707.802856                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    40459125250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1927900000                       # Time in different power states
+system.physmem.writeRowHitRate                  74.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                       271199.41                       # Average gap between requests
+system.physmem.pageHitRate                      81.95                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  151063920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   82425750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 512577000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                272309040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3769446720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11829284955                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24250601250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              40867708635                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              708.132582                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    40213391000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1927120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     15348292250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     15571447750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  139489560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   76110375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 492070800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                271492560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3770972400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11151778680                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24858920250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              40760834625                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              705.994980                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    41228847750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1927900000                       # Time in different power states
+system.physmem_1.actEnergy                  139058640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   75875250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 492008400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                271479600                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3769446720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11209873365                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24793944750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              40751686725                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              706.122220                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    41121510500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1927120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     14578569750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     14663764500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14838314                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9926302                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            397118                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9672403                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6752101                       # Number of BTB hits
+system.cpu.branchPred.lookups                14827145                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9920468                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            395132                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9565987                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6746821                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             69.807896                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1719649                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             70.529272                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1718856                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -405,97 +404,97 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        115476391                       # number of cpu cycles simulated
+system.cpu.numCycles                        115433389                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    70915127                       # Number of instructions committed
-system.cpu.committedOps                      90690083                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1150638                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                    70915128                       # Number of instructions committed
+system.cpu.committedOps                      90690084                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       1146778                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.628375                       # CPI: cycles per instruction
-system.cpu.ipc                               0.614109                       # IPC: instructions per cycle
-system.cpu.tickCycles                        96920862                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        18555529                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            156418                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.282815                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42627759                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160514                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.570349                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         830513250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.282815                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992989                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992989                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.627768                       # CPI: cycles per instruction
+system.cpu.ipc                               0.614338                       # IPC: instructions per cycle
+system.cpu.tickCycles                        96895866                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18537523                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            156436                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4067.344190                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42626825                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160532                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.534753                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         829717250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.344190                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993004                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993004                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1135                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2916                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1141                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2911                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86021754                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86021754                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22869180                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22869180                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19642188                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642188                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        84553                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         84553                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          86020072                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86020072                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22868301                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22868301                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19642179                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642179                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        84507                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         84507                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42511368                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42511368                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42595921                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42595921                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        51489                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         51489                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       207713                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207713                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        43659                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        43659                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       259202                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         259202                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       302861                       # number of overall misses
-system.cpu.dcache.overall_misses::total        302861                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1477411436                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1477411436                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  16920342250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  16920342250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18397753686                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18397753686                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18397753686                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18397753686                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22920669                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22920669                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      42510480                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42510480                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42594987                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42594987                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        51533                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         51533                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       207722                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207722                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        43690                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        43690                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       259255                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         259255                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       302945                       # number of overall misses
+system.cpu.dcache.overall_misses::total        302945                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1474342937                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1474342937                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  16908501000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  16908501000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18382843937                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18382843937                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18382843937                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18382843937                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22919834                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22919834                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128212                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128212                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128197                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128197                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42770570                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42770570                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42898782                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42898782                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002246                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002246                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.340522                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.340522                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006060                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006060                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007060                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28693.729457                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28693.729457                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81460.198688                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 81460.198688                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70978.440313                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70978.440313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60746.526248                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60746.526248                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     42769735                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42769735                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42897932                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42897932                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002248                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002248                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.340804                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.340804                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007062                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007062                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28609.685774                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28609.685774                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81399.663974                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81399.663974                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70906.420077                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70906.420077                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60680.466543                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60680.466543                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -504,110 +503,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128435                       # number of writebacks
-system.cpu.dcache.writebacks::total            128435                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21989                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        21989                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100683                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100683                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       122672                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       122672                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       122672                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       122672                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29500                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29500                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107030                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107030                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23984                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        23984                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136530                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136530                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       160514                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160514                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    558489314                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    558489314                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8444692500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8444692500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1685620500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1685620500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9003181814                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9003181814                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10688802314                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10688802314                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       128445                       # number of writebacks
+system.cpu.dcache.writebacks::total            128445                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22036                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        22036                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100688                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100688                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       122724                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       122724                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       122724                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       122724                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29497                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29497                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107034                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107034                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        24001                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        24001                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       136531                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136531                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       160532                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160532                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    558577313                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    558577313                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8440191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8440191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1682073500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1682073500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8998768313                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   8998768313                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10680841813                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10680841813                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001287                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001287                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187065                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187065                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187220                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187220                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003192                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18931.841153                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18931.841153                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78900.238251                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78900.238251                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70281.041528                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70281.041528                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65942.882985                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65942.882985                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66591.090584                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66591.090584                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18936.749941                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18936.749941                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78855.232917                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78855.232917                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70083.475689                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70083.475689                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65910.073998                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65910.073998                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66534.035663                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66534.035663                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             42756                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1854.448619                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25096729                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             44798                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            560.219854                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             42847                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1854.482229                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25082964                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             44889                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            558.777518                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1854.448619                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.905492                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.905492                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1854.482229                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.905509                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.905509                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          918                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1004                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           40                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          916                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1005                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50327854                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50327854                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25096729                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25096729                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25096729                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25096729                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25096729                       # number of overall hits
-system.cpu.icache.overall_hits::total        25096729                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        44799                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         44799                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        44799                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          44799                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        44799                       # number of overall misses
-system.cpu.icache.overall_misses::total         44799                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    934736739                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    934736739                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    934736739                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    934736739                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    934736739                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    934736739                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25141528                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25141528                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25141528                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25141528                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25141528                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25141528                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001782                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001782                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001782                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001782                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001782                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001782                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20865.125092                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20865.125092                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20865.125092                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20865.125092                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20865.125092                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20865.125092                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          50300597                       # Number of tag accesses
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+system.cpu.icache.ReadReq_hits::cpu.inst     25082964                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst    936252739                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_avg_miss_latency::total 20856.599220                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -616,123 +615,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44799                       # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    865619261                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total    865619261                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001782                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19322.289806                       # average ReadReq mshr miss latency
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19322.289806                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 19313.895322                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            95726                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29866.578850                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              99768                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1560.467773                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31118                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12771                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        15838                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          578                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949646                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.overall_miss_latency::cpu.inst    404023750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10134945750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10538969500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        44890                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        53498                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        98388                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       128445                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       128445                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       107034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       107034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        44890                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       160532                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       205422                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        44890                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       160532                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       205422                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113054                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.403492                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.270978                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955584                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955584                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113054                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771597                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.627688                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113054                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771597                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.627688                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79610.591133                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85784.408876                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 84609.204456                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80985.564138                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80985.564138                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79610.591133                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81821.853858                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81734.820577                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79610.591133                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81821.853858                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81734.820577                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -744,113 +743,113 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks::writebacks        83953                       # number of writebacks
 system.cpu.l2cache.writebacks::total            83953                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           64                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           63                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           64                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           63                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           64                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           74                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5069                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21514                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        26583                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102282                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102282                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         5069                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       123796                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       128865                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         5069                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       123796                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       128865                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    339459750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1581559750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1921019500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7009102000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7009102000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    339459750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8590661750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8930121500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    339459750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8590661750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8930121500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113150                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.402251                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.270474                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955639                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955639                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113150                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771247                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.627651                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113150                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771247                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.627651                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66967.794437                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73513.049642                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72264.962570                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68527.228642                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68527.228642                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66967.794437                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69393.694061                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69298.269507                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66967.794437                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69393.694061                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69298.269507                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data           63                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           73                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5065                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21523                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        26588                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102280                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102280                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         5065                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       123803                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       128868                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         5065                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       123803                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       128868                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    339808000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1578466750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1918274750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7004628000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7004628000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    339808000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8583094750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8922902750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    339808000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8583094750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8922902750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.112831                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.402314                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.270236                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955584                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955584                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.112831                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771204                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.627333                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.112831                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771204                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.627333                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67089.437315                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73338.602890                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72148.140138                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68484.825968                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68484.825968                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67089.437315                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69328.649144                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69240.639647                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67089.437315                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69328.649144                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69240.639647                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          98283                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         98282                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       128435                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107030                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107030                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        89597                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       449463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            539060                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2867072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18492736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           21359808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq          98388                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         98387                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       128445                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        89779                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       449509                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            539288                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2872896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18494528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           21367424                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       333748                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       333867                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3             333748    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3             333867    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         333748                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      295309000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         333867                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      295378500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      68157239                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      68292739                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     268247686                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     268237687                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq               26582                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26582                       # Transaction distribution
+system.membus.trans_dist::ReadReq               26587                       # Transaction distribution
+system.membus.trans_dist::ReadResp              26587                       # Transaction distribution
 system.membus.trans_dist::Writeback             83953                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102282                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102282                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       341681                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 341681                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13620288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13620288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq            102280                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102280                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       341687                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 341687                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13620480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13620480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            212817                       # Request fanout histogram
+system.membus.snoop_fanout::samples            212820                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  212817    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  212820    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              212817                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           578407500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              212820                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           578469000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          680129500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          680054250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 46a8a5ebb..e0d8233d1 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,118 +1,118 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033359                       # Number of seconds simulated
-sim_ticks                                 33359312000                       # Number of ticks simulated
-final_tick                                33359312000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.033331                       # Number of seconds simulated
+sim_ticks                                 33330913000                       # Number of ticks simulated
+final_tick                                33330913000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 119579                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152928                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56257417                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252556                       # Number of bytes of host memory used
-host_seconds                                   592.98                       # Real time elapsed on the host
-sim_insts                                    70907629                       # Number of instructions simulated
-sim_ops                                      90682584                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  93420                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119473                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               43913176                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317168                       # Number of bytes of host memory used
+host_seconds                                   759.02                       # Real time elapsed on the host
+sim_insts                                    70907630                       # Number of instructions simulated
+sim_ops                                      90682585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            593600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           2515776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher      6204544                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9313920                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       593600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          593600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6264768                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6264768                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               9275                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              39309                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        96946                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                145530                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97887                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97887                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             17794132                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             75414505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher    185991366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               279200003                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        17794132                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           17794132                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         187796679                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              187796679                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         187796679                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            17794132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            75414505                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher    185991366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              466996681                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        145530                       # Number of read requests accepted
-system.physmem.writeReqs                        97887                       # Number of write requests accepted
-system.physmem.readBursts                      145530                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97887                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9306560                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6263296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9313920                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6264768                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            583488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           2505024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher      6203200                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9291712                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       583488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          583488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6256128                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6256128                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               9117                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              39141                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        96925                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                145183                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97752                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97752                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             17505911                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             75156177                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher    186109513                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               278771602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        17505911                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           17505911                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         187697469                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              187697469                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         187697469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            17505911                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            75156177                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher    186109513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              466469070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        145183                       # Number of read requests accepted
+system.physmem.writeReqs                        97752                       # Number of write requests accepted
+system.physmem.readBursts                      145183                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97752                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9284992                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6254720                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9291712                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6256128                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9160                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9419                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9305                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9483                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9789                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9711                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9074                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                9074                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9205                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8628                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8849                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8741                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               8642                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               8695                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8691                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8949                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5976                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6255                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6149                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6169                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6151                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6334                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6086                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6007                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5979                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6153                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6241                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5938                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6061                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6105                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6219                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6041                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9145                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9372                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9233                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9500                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9743                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9700                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9083                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8995                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9233                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8567                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8856                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8704                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               8629                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               8694                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8697                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8927                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5993                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6233                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6131                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6188                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6147                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6290                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6056                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6014                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6000                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6152                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6228                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5920                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6078                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6086                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6193                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6021                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     33359040500                       # Total gap between requests
+system.physmem.totGap                     33330641500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  145530                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  145183                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97887                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     42093                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     51689                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     18360                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9225                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6081                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4669                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4300                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3562                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        86                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97752                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     41867                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     51877                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     18150                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9231                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6097                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5279                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4608                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3567                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        88                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4431                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5913                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6430                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6850                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6431                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       17                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,104 +197,101 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        88927                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      175.072858                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     110.491943                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     238.713124                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          52339     58.86%     58.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22656     25.48%     84.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4441      4.99%     89.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1741      1.96%     91.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1037      1.17%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          849      0.95%     93.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          689      0.77%     94.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          765      0.86%     95.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4410      4.96%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          88927                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5911                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.598207                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       21.088924                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      187.219466                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            5910     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        88649                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      175.273178                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     110.551570                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     239.030923                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          52157     58.84%     58.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22538     25.42%     84.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4461      5.03%     89.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1758      1.98%     91.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1068      1.20%     92.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          785      0.89%     93.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          713      0.80%     94.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          748      0.84%     95.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4421      4.99%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          88649                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5905                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.566130                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       21.054973                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      187.117675                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            5904     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5911                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5911                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.556251                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.512708                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.281856                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4715     79.77%     79.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 33      0.56%     80.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                741     12.54%     92.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                193      3.27%     96.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                104      1.76%     97.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 53      0.90%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 34      0.58%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 17      0.29%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 11      0.19%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  4      0.07%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  3      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5911                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7478329771                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10204861021                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    727075000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       51427.50                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5905                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5905                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.550381                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.508750                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.243905                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4712     79.80%     79.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 29      0.49%     80.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                757     12.82%     93.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                163      2.76%     95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                111      1.88%     97.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 62      1.05%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 43      0.73%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 20      0.34%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.10%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5905                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7425181339                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10145393839                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    725390000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       51180.62                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  70177.50                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         278.98                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         187.75                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      279.20                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      187.80                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  69930.62                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         278.57                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         187.66                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      278.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      187.70                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.65                       # Data bus utilization in percentage
+system.physmem.busUtil                           3.64                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.61                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     118188                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     36158                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.28                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  36.94                       # Row buffer hit rate for writes
-system.physmem.avgGap                       137044.83                       # Average gap between requests
-system.physmem.pageHitRate                      63.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  343556640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  187456500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 584859600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                318226320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             2178671040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11869125390                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             9602419500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              25084314990                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              752.005565                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    15876395968                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1113840000                       # Time in different power states
+system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.63                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     117819                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     36329                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.21                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  37.16                       # Row buffer hit rate for writes
+system.physmem.avgGap                       137199.83                       # Average gap between requests
+system.physmem.pageHitRate                      63.48                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  342679680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  186978000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 582769200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                317714400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             2176636800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11943657450                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             9518358000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              25068793530                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              752.242445                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    15735797307                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1112800000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16366332782                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16476833443                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  328413960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  179194125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 548948400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                315725040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             2178671040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11416289175                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             9999644250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              24966885990                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              748.485148                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    16542747198                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1113840000                       # Time in different power states
+system.physmem_1.actEnergy                  327053160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  178451625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 548121600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                315264960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             2176636800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11265215805                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            10113486000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              24924229950                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              747.904367                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    16730540892                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1112800000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     15699981552                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     15482244108                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17207670                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11518844                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            648137                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9345275                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7675164                       # Number of BTB hits
+system.cpu.branchPred.lookups                17205793                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11516695                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            648305                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9352037                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7676056                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.128819                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1873048                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             101561                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             82.078974                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1873350                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             101557                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -413,129 +410,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         66718625                       # number of cpu cycles simulated
+system.cpu.numCycles                         66661827                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            4981358                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       88194612                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17207670                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9548212                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      60206161                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1322349                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 5969                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            4979954                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       88191186                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17205793                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9549406                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      60159688                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1322593                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 6446                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            25                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        13195                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22764676                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 68972                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           65867882                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.694526                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.296864                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles        13285                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22768352                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 68999                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           65820694                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.695691                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.296532                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 20086614     30.50%     30.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8263984     12.55%     43.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9201027     13.97%     57.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28316257     42.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 20039717     30.45%     30.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8265549     12.56%     43.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9200264     13.98%     56.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 28315164     43.02%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             65867882                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.257914                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.321889                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8560400                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              19609685                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  31575881                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5629864                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 492052                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3179520                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                171002                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              101414286                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3048471                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 492052                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13316863                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5341740                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         787564                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  32235527                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13694136                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               99203918                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                983561                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3871797                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  66642                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4317748                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5384160                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           103925780                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             457714134                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        115415425                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total             65820694                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258106                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.322964                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8562659                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              19557917                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31575920                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5632021                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 492177                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3179708                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                171007                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              101418024                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3051775                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 492177                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13320782                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5331170                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         788978                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  32236803                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13650784                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               99206458                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                984473                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3857341                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  63915                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4307533                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5353775                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           103928524                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             457724306                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        115417327                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 10296554                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18659                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18650                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12695794                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24322207                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21994092                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1403605                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2365005                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   98166864                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               34522                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  94891849                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            694587                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7518802                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     20250811                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            736                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      65867882                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.440639                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.150059                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 10299298                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18661                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          18655                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12693692                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             24322711                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21993814                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1396246                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2340033                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   98168548                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               34521                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  94889336                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            694958                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7520484                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     20257229                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            735                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      65820694                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.441634                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.150001                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17597825     26.72%     26.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17436284     26.47%     53.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17101122     25.96%     79.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            11678255     17.73%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2053424      3.12%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 972      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17560123     26.68%     26.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17422684     26.47%     53.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17103546     25.99%     79.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            11678791     17.74%     96.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2054563      3.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 987      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        65867882                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        65820694                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 6717330     22.42%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     38      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11201861     37.39%     59.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              12041280     40.19%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 6715459     22.40%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     39      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11205581     37.37%     59.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              12062957     40.23%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49497025     52.16%     52.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                89873      0.09%     52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49498174     52.16%     52.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                89865      0.09%     52.26% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.26% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.26% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.26% # Type of FU issued
@@ -563,96 +560,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.26% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24063293     25.36%     77.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21241620     22.39%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24060336     25.36%     77.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21240923     22.38%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               94891849                       # Type of FU issued
-system.cpu.iq.rate                           1.422269                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    29960509                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.315733                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          286306469                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         105731477                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     93465742                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total               94889336                       # Type of FU issued
+system.cpu.iq.rate                           1.423443                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    29984036                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.315990                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          286278153                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         105734805                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     93465836                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              124852240                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              124873254                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1363033                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          1363649                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1455945                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2039                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11790                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1438354                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1456449                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2030                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11752                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1438076                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       142055                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        176720                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       138616                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        176709                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 492052                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  623106                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                467581                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98211247                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 492177                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  621288                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                454814                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            98212928                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24322207                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21994092                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18602                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1655                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                463043                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11790                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         303168                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       221686                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               524854                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              93974313                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23756309                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            917536                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              24322711                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21993814                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18601                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1642                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                450257                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11752                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         303335                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       221647                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               524982                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93971179                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23753264                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            918157                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9861                       # number of nop insts executed
-system.cpu.iew.exec_refs                     44740784                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14252664                       # Number of branches executed
-system.cpu.iew.exec_stores                   20984475                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.408517                       # Inst execution rate
-system.cpu.iew.wb_sent                       93587501                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      93465799                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  44986533                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  76576760                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          9859                       # number of nop insts executed
+system.cpu.iew.exec_refs                     44736876                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14252919                       # Number of branches executed
+system.cpu.iew.exec_stores                   20983612                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.409670                       # Inst execution rate
+system.cpu.iew.wb_sent                       93587571                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      93465893                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  44982416                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  76564206                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.400895                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.587470                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.402090                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.587512                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         6538748                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         6539953                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            479015                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     64808930                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.399315                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.164562                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            479186                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     64761460                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.400341                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.165093                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31222194     48.18%     48.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16795938     25.92%     74.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4338232      6.69%     80.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4159188      6.42%     87.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1936724      2.99%     90.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1268170      1.96%     92.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       738929      1.14%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       579590      0.89%     94.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3769965      5.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     31172018     48.13%     48.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16800427     25.94%     74.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4337432      6.70%     80.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4161423      6.43%     87.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1935218      2.99%     90.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1264756      1.95%     92.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       739046      1.14%     93.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       579471      0.89%     94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3771669      5.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     64808930                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
-system.cpu.commit.committedOps               90688136                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     64761460                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             70913182                       # Number of instructions committed
+system.cpu.commit.committedOps               90688137                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       43422000                       # Number of memory references committed
 system.cpu.commit.loads                      22866262                       # Number of loads committed
 system.cpu.commit.membars                       15920                       # Number of memory barriers committed
-system.cpu.commit.branches                   13741485                       # Number of branches committed
+system.cpu.commit.branches                   13741486                       # Number of branches committed
 system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  81528487                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         47186010     52.03%     52.03% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         47186011     52.03%     52.03% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
@@ -685,381 +682,380 @@ system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Cl
 system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          90688136                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3769965                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    158240550                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195514428                       # The number of ROB writes
-system.cpu.timesIdled                           23835                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          850743                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
-system.cpu.committedOps                      90682584                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.940923                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.940923                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.062786                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.062786                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                102271067                       # number of integer regfile reads
-system.cpu.int_regfile_writes                56793819                       # number of integer regfile writes
+system.cpu.commit.op_class_0::total          90688137                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               3771669                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    158192582                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195517129                       # The number of ROB writes
+system.cpu.timesIdled                           23763                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          841133                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    70907630                       # Number of Instructions Simulated
+system.cpu.committedOps                      90682585                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.940122                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.940122                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.063692                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.063692                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                102266688                       # number of integer regfile reads
+system.cpu.int_regfile_writes                56794481                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 346093039                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 38805147                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44210055                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                 346084159                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 38805382                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                44209334                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            485079                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           510.744077                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40428139                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            485591                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             83.255536                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         152734000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   510.744077                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997547                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997547                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            485106                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           510.740457                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40427935                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            485618                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             83.250487                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         152807000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   510.740457                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997540                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997540                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84616103                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84616103                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21501727                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21501727                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18833421                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18833421                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        61667                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         61667                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          84615616                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84615616                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21501539                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21501539                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18833357                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18833357                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        61715                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         61715                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15379                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15379                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40335148                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40335148                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40396815                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40396815                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       552941                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        552941                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1016480                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1016480                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        67175                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        67175                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data      40334896                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40334896                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40396611                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40396611                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       552871                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        552871                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1016544                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1016544                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        67128                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        67128                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          547                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          547                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1569421                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1569421                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1636596                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1636596                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9116754245                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9116754245                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  14723087903                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  14723087903                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5168250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      5168250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  23839842148                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  23839842148                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  23839842148                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  23839842148                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22054668                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22054668                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      1569415                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1569415                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1636543                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1636543                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9102953011                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9102953011                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14661434456                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14661434456                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5113500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      5113500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  23764387467                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  23764387467                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  23764387467                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  23764387467                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22054410                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22054410                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128842                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128842                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128843                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128843                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41904569                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41904569                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42033411                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42033411                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025071                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025071                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051208                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.051208                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.521375                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.521375                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     41904311                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41904311                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42033154                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42033154                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025069                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025069                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051212                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.051212                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.521006                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.521006                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.034346                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.034346                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.037452                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.037452                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.038936                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.038936                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16487.752301                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16487.752301                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14484.385234                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 14484.385234                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9448.354662                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9448.354662                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15190.214830                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15190.214830                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14566.723949                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14566.723949                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           97                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3023244                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          128456                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.818182                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    23.535249                       # average number of cycles each access was blocked
+system.cpu.dcache.overall_miss_rate::cpu.data     0.038935                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.038935                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16464.876998                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16464.876998                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14422.823268                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 14422.823268                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9348.263254                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9348.263254                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15142.194682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15142.194682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14521.089557                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14521.089557                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           25                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3013610                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          128472                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.250000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    23.457329                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       262833                       # number of writebacks
-system.cpu.dcache.writebacks::total            262833                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       253459                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       253459                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       867955                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       867955                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       264409                       # number of writebacks
+system.cpu.dcache.writebacks::total            264409                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       253375                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       253375                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       868011                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       868011                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          547                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          547                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1121414                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1121414                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1121414                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1121414                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299482                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       299482                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148525                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       148525                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37595                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        37595                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       448007                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       448007                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       485602                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       485602                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3044598863                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3044598863                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2289083292                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2289083292                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2038189218                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2038189218                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5333682155                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5333682155                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7371871373                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7371871373                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013579                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013579                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007482                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007482                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291791                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291791                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010691                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.010691                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data      1121386                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1121386                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1121386                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1121386                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299496                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       299496                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148533                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       148533                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37600                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        37600                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       448029                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       448029                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       485629                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       485629                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3035888114                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3035888114                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2279411901                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2279411901                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2033283784                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2033283784                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5315300015                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5315300015                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7348583799                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7348583799                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013580                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013580                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291828                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291828                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010692                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.010692                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011553                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.011553                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10166.216544                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10166.216544                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15412.107672                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15412.107672                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54214.369411                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54214.369411                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11905.354503                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11905.354503                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15180.891703                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15180.891703                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10136.656630                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10136.656630                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15346.164832                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15346.164832                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54076.696383                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54076.696383                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11863.740997                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11863.740997                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15132.094251                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15132.094251                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            322801                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.305225                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22431720                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            323313                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             69.380817                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        1103729250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.305225                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996690                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996690                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            322771                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.304013                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22435446                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            323283                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             69.398781                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        1099609250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.304013                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996688                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996688                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
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 system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          352                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          354                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45852448                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45852448                       # Number of data accesses
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-system.cpu.icache.overall_hits::total        22431720                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       332842                       # number of ReadReq misses
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-system.cpu.icache.demand_misses::total         332842                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       332842                       # number of overall misses
-system.cpu.icache.overall_misses::total        332842                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   3383637839                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   3383637839                       # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::cpu.inst   3383637839                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3383637839                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22764562                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22764562                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22764562                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22764562                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22764562                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22764562                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014621                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014621                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014621                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014621                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014621                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014621                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10165.898051                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10165.898051                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10165.898051                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10165.898051                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10165.898051                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10165.898051                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       260603                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          45859770                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45859770                       # Number of data accesses
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+system.cpu.icache.overall_miss_latency::total   3372368098                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22768238                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total     22768238                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014617                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014617                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014617                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014617                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total     0.014617                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10133.561197                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10133.561197                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10133.561197                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10133.561197                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10133.561197                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10133.561197                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       259166                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           49                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs             14904                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs             14826                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    17.485440                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    17.480507                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9518                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         9518                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         9518                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         9518                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         9518                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         9518                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323324                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       323324                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       323324                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       323324                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       323324                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       323324                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2932923000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2932923000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2932923000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2932923000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2932923000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2932923000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014203                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014203                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014203                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9071.157724                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9071.157724                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9071.157724                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9071.157724                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9071.157724                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9071.157724                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9498                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         9498                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         9498                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst         9498                       # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_miss_latency::total   2922927754                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2922927754                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2922927754                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total   2922927754                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014199                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014199                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014199                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9041.082587                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  9041.082587                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  9041.082587                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       824674                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       826525                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         1627                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       824420                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       826170                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         1539                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        78731                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           129661                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16079.092385                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             870667                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           145945                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.965720                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage        78694                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           129309                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16078.989093                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             872580                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           145594                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             5.993241                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 12574.733150                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1436.327637                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1964.109767                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   103.921830                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.767501                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087666                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.119880                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006343                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.981390                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022           37                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        16247                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 12596.793225                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1430.956994                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1951.680185                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    99.558690                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768847                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087339                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.119121                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006077                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.981384                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022           24                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        16261                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           19                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2630                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11951                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          605                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          907                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.002258                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.991638                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         17442481                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        17442481                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       313998                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       305857                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         619855                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       262833                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       262833                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           13                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11971                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.992493                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         17467290                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        17467290                       # Number of data accesses
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+system.cpu.l2cache.ReadReq_hits::total         620064                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       264409                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       264409                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       137138                       # number of ReadExReq hits
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-system.cpu.l2cache.demand_hits::cpu.data       442995                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.data       442995                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         756993                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         9315                       # number of ReadReq misses
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 system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
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-system.cpu.l2cache.ReadExReq_misses::cpu.data        11425                       # number of ReadExReq misses
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-system.cpu.l2cache.overall_misses::total        51911                       # number of overall misses
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-system.cpu.l2cache.overall_miss_latency::cpu.data   3983561838                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total       660341                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       262833                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       262833                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.Writeback_accesses::total       264409                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.545455                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.545455                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87828.093677                       # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109047.906346                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109047.906346                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78080.031455                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93519.622453                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 90749.115428                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78080.031455                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93519.622453                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 90749.115428                       # average overall miss latency
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+system.cpu.l2cache.demand_miss_rate::total     0.063756                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028313                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.087351                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.063756                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78284.495794                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87540.746754                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 85436.624935                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109263.061997                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109263.061997                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78284.495794                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93330.940263                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 90660.496878                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78284.495794                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93330.940263                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 90660.496878                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1068,143 +1064,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97887                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97887                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           40                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          132                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total          172                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3155                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3155                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           40                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         3287                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         3327                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           40                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         3287                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         3327                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         9275                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31039                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        40314                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112789                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       112789                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        97752                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97752                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           36                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          124                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total          160                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3154                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3154                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           36                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         3278                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         3314                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           36                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         3278                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         3314                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         9117                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30988                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        40105                       # number of ReadReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112705                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       112705                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8270                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         8270                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         9275                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        39309                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        48584                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         9275                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        39309                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112789                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       161373                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    645635507                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2465712994                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3111348501                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10913543372                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10913543372                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        83006                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        83006                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    614828776                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    614828776                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    645635507                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3080541770                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   3726177277                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    645635507                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3080541770                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10913543372                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14639720649                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.028687                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.092096                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.061050                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8153                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         8153                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9117                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        39141                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        48258                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9117                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        39141                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112705                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       160963                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    636175260                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2451921294                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3088096554                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10874977234                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10874977234                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        82006                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        82006                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    605818037                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    605818037                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    636175260                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3057739331                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3693914591                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    636175260                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3057739331                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10874977234                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14568891825                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.091940                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.060735                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.545455                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.545455                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.055667                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.055667                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028687                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080951                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060062                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028687                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080951                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.054876                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.054876                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080600                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.059659                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080600                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.199496                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69610.297251                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79439.189214                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77177.866275                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96760.706913                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13834.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13834.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74344.471100                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74344.471100                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69610.297251                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78367.340049                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76695.563910                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69610.297251                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78367.340049                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90719.765072                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.198990                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79124.864270                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77000.288094                       # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96490.636919                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13667.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13667.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74306.149516                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74306.149516                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78121.134641                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76545.123938                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78121.134641                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90510.811957                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         660352                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        660352                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       262833                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       151427                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         660341                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        660341                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       264409                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       151292                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       148563                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       148563                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       646637                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1234037                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1880674                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20692032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47899136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           68591168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      151438                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1223186                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.123797                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.329350                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       148571                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       148571                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       646576                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1235667                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1882243                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20690048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     48001728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           68691776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      151304                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1224624                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.123542                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.329058                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            1071759     87.62%     87.62% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4             151427     12.38%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            1073332     87.65%     87.65% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4             151292     12.35%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1223186                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      798712500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1224624                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      801075000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     486658187                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     486570693                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     734620345                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     734618165                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq              137260                       # Transaction distribution
-system.membus.trans_dist::ReadResp             137260                       # Transaction distribution
-system.membus.trans_dist::Writeback             97887                       # Transaction distribution
+system.membus.trans_dist::ReadReq              137030                       # Transaction distribution
+system.membus.trans_dist::ReadResp             137030                       # Transaction distribution
+system.membus.trans_dist::Writeback             97752                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              8270                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8270                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       388959                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 388959                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15578688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15578688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq              8153                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             8153                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       388130                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 388130                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15547840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15547840                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            243423                       # Request fanout histogram
+system.membus.snoop_fanout::samples            242941                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  243423    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  242941    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              243423                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           692237323                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              242941                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           691321050                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          758965490                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          757153835                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index a72b0bcd6..abad5bc99 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.121241                       # Number of seconds simulated
-sim_ticks                                1121241432500                       # Number of ticks simulated
-final_tick                               1121241432500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.121265                       # Number of seconds simulated
+sim_ticks                                1121265462500                       # Number of ticks simulated
+final_tick                               1121265462500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 170583                       # Simulator instruction rate (inst/s)
-host_op_rate                                   183778                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              123831111                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241824                       # Number of bytes of host memory used
-host_seconds                                  9054.60                       # Real time elapsed on the host
-sim_insts                                  1544563087                       # Number of instructions simulated
-sim_ops                                    1664032480                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 175724                       # Simulator instruction rate (inst/s)
+host_op_rate                                   189316                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              127565822                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306448                       # Number of bytes of host memory used
+host_seconds                                  8789.70                       # Real time elapsed on the host
+sim_insts                                  1544563088                       # Number of instructions simulated
+sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             50560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         131525952                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131576512                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     66977984                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          66977984                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                790                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2055093                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2055883                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1046531                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1046531                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                45093                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            117303864                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               117348956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           45093                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              45093                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          59735559                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               59735559                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          59735559                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               45093                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           117303864                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              177084516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2055883                       # Number of read requests accepted
-system.physmem.writeReqs                      1046531                       # Number of write requests accepted
-system.physmem.readBursts                     2055883                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1046531                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                131490688                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     85824                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  66976384                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131576512                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               66977984                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1341                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             50816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         131531264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131582080                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     66976320                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          66976320                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                794                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2055176                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2055970                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1046505                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1046505                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                45320                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            117306087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               117351407                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           45320                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              45320                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          59732795                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               59732795                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          59732795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               45320                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           117306087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177084202                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2055970                       # Number of read requests accepted
+system.physmem.writeReqs                      1046505                       # Number of write requests accepted
+system.physmem.readBursts                     2055970                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1046505                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                131497344                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     84736                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  66974720                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131582080                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               66976320                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1324                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              127988                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              125250                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              122092                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              124158                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              123330                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              123315                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              123951                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124319                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              132052                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              134015                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132327                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133706                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             133817                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133969                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129938                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             130315                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               65788                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              128088                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              125235                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              122283                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              124122                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              123237                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              123404                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              123754                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124260                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              132002                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              134077                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132455                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133729                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             133726                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             133924                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129890                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             130460                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               65849                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               64148                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               62323                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               62858                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               62842                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               62926                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64344                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65270                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67114                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67597                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67253                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67655                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67032                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67505                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66189                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              65662                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               62390                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               62849                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               62818                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               62997                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64238                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65252                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67098                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67598                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67270                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              67670                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67009                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67470                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66159                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              65665                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1121241338000                       # Total gap between requests
+system.physmem.totGap                    1121265368000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2055883                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2055970                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1046531                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1926751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    127772                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1046505                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1926795                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    127832                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    32090                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    60994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61458                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61494                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    61881                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60987                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    32223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    56905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    60965                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61436                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61459                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61467                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    61856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60967                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -193,105 +193,105 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1919691                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.383938                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.729389                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     124.654868                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1494811     77.87%     77.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305161     15.90%     93.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53151      2.77%     96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21323      1.11%     97.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13050      0.68%     98.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7398      0.39%     98.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5428      0.28%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5020      0.26%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        14349      0.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1919691                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60985                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.641650                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      160.664141                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          60945     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           17      0.03%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            9      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1920747                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.329698                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.701744                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     124.647307                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1495902     77.88%     77.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       305625     15.91%     93.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52698      2.74%     96.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21305      1.11%     97.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13173      0.69%     98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7131      0.37%     98.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5450      0.28%     98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5094      0.27%     99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        14369      0.75%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1920747                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60965                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.654375                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      161.846066                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          60925     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           15      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60985                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60985                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.160056                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.125150                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.096252                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27287     44.74%     44.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1323      2.17%     46.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              28176     46.20%     93.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3806      6.24%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                330      0.54%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 51      0.08%     99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           60965                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60965                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.165259                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.130353                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.096188                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27136     44.51%     44.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1324      2.17%     46.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              28285     46.40%     93.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3807      6.24%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                355      0.58%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 47      0.08%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::22                  9      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60985                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38434561000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76957223500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10272710000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18707.12                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60965                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38466601000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76991213500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10273230000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18721.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37457.12                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         117.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37471.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         117.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          59.73                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      117.35                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       59.74                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       59.73                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.38                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     774810                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    406537                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.71                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  38.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                       361409.32                       # Average gap between requests
-system.physmem.pageHitRate                      38.09                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 7080832080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3863549250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7756031400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3308033520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            73233657120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           422818284195                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           301848259500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             819908647065                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              731.254419                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   499427924250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     37440520000                       # Time in different power states
+system.physmem.avgWrQLen                        24.95                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     774547                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    405822                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.70                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  38.78                       # Row buffer hit rate for writes
+system.physmem.avgGap                       361409.96                       # Average gap between requests
+system.physmem.pageHitRate                      38.06                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 7084922040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3865780875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7755875400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3308305680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            73235182800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           422966689965                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           301732094250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             819948851010                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              731.275041                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   499232206000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     37441300000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    584369735750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    584588629000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7432016760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 4055167875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                8269029600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3473325360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            73233657120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           431345081205                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           294368613000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             822176890920                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              733.277404                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   486933261750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     37440520000                       # Time in different power states
+system.physmem_1.actEnergy                 7435910160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 4057292250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                8269996800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3472884720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            73235182800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           431711081055                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           294061575750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             822243923535                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              733.321912                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   486423236500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     37441300000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    596864300250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    597397500000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               240141357                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186745174                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14595264                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            132286195                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122283419                       # Number of BTB hits
+system.cpu.branchPred.lookups               240144458                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186748856                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14594265                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            132793559                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122289853                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.438534                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15659523                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             92.090199                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15658823                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -411,68 +411,68 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       2242482865                       # number of cpu cycles simulated
+system.cpu.numCycles                       2242530925                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1544563087                       # Number of instructions committed
-system.cpu.committedOps                    1664032480                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      40063388                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                  1544563088                       # Number of instructions committed
+system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      40067412                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.451856                       # CPI: cycles per instruction
-system.cpu.ipc                               0.688774                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1838984644                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       403498221                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9223361                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.642531                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624067002                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9227457                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.631526                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        9813070000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.642531                       # Average occupied blocks per requestor
+system.cpu.cpi                               1.451887                       # CPI: cycles per instruction
+system.cpu.ipc                               0.688759                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1838970368                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       403560557                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9223420                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4085.640559                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624065637                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9227516                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.630946                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        9814734000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.640559                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997471                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997471                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          255                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1217                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2563                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          252                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1219                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2564                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1276544027                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1276544027                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    453735352                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       453735352                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170331527                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170331527                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1276541490                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276541490                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    453733959                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453733959                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170331555                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170331555                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624066879                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624066879                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624066880                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624066880                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7336761                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7336761                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2254520                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2254520                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     624065514                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624065514                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    624065515                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624065515                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7336856                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7336856                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2254492                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2254492                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9591281                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9591281                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9591283                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9591283                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442274246                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 192442274246                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711140250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 109711140250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 302153414496                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 302153414496                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 302153414496                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 302153414496                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461072113                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461072113                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9591348                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9591348                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9591350                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9591350                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 192473949996                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 192473949996                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 109728776250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 109728776250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 302202726246                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 302202726246                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 302202726246                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 302202726246                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    461070815                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461070815                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -481,28 +481,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    633658160                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    633658160                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    633658163                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    633658163                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015912                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.015912                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    633656862                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633656862                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    633656865                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633656865                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015913                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.015913                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013063                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013063                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.666667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.666667                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.015136                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015136                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.015136                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015136                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.868227                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.868227                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.748723                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.748723                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.925886                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31502.925886                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.919317                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31502.919317                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.015137                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015137                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015137                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015137                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26233.845941                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26233.845941                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48671.175702                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48671.175702                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31507.847098                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31507.847098                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31507.840528                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31507.840528                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -511,36 +511,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3701040                       # number of writebacks
-system.cpu.dcache.writebacks::total           3701040                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          208                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          208                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       363617                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       363617                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       363825                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       363825                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       363825                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       363825                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7336553                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7336553                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890903                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890903                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3700612                       # number of writebacks
+system.cpu.dcache.writebacks::total           3700612                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          212                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          212                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       363621                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       363621                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       363833                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       363833                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       363833                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       363833                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7336644                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7336644                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890871                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1890871                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9227456                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9227456                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9227457                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9227457                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020814754                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020814754                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83976850000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83976850000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9227515                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9227515                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9227516                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9227516                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181052332504                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 181052332504                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83984263000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  83984263000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        73750                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        73750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997664754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 264997664754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997738504                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 264997738504                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265036595504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 265036595504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265036669254                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 265036669254                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015912                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015912                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
@@ -551,69 +551,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014562
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014562                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014562                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014562                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.823627                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.823627                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.977189                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.977189                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24677.813521                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24677.813521                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44415.649190                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44415.649190                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        73750                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        73750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.388335                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.388335                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393215                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393215                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28722.423697                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28722.423697                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28722.428577                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28722.428577                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                32                       # number of replacements
-system.cpu.icache.tags.tagsinuse           661.433391                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           466139348                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               823                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          566390.459295                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                35                       # number of replacements
+system.cpu.icache.tags.tagsinuse           662.614734                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           466141021                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               828                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          562972.247585                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   661.433391                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.322966                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.322966                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   662.614734                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.323542                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.323542                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          793                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          753                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         932281165                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        932281165                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    466139348                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       466139348                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     466139348                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        466139348                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    466139348                       # number of overall hits
-system.cpu.icache.overall_hits::total       466139348                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          823                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           823                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          823                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            823                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          823                       # number of overall misses
-system.cpu.icache.overall_misses::total           823                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     63711749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     63711749                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     63711749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     63711749                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     63711749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     63711749                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    466140171                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    466140171                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    466140171                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    466140171                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    466140171                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    466140171                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.387207                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         932284526                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        932284526                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    466141021                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       466141021                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     466141021                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        466141021                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    466141021                       # number of overall hits
+system.cpu.icache.overall_hits::total       466141021                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          828                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           828                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          828                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            828                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          828                       # number of overall misses
+system.cpu.icache.overall_misses::total           828                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     63773749                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     63773749                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     63773749                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     63773749                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     63773749                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     63773749                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    466141849                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    466141849                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    466141849                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    466141849                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    466141849                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    466141849                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77414.032807                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77414.032807                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77414.032807                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77414.032807                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77414.032807                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77414.032807                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77021.435990                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77021.435990                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77021.435990                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77021.435990                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77021.435990                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77021.435990                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -622,123 +622,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          823                       # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     62143751                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75508.810450                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 75116.245169                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2023178                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31261.935104                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.warmup_cycle      59841737750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14973.678994                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.751537                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16261.504573                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12852                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -747,8 +747,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1046531                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1046531                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1046505                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1046505                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
@@ -758,105 +758,105 @@ system.cpu.l2cache.demand_mshr_hits::total            5                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          790                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1254946                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1255736                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       800147                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       800147                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          790                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2055093                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2055883                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          790                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2055093                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2055883                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     51082250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  93955002000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  94006084250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60459126500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60459126500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     51082250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414128500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 154465210750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     51082250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414128500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 154465210750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.959903                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.171054                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171142                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423156                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423156                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.959903                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.222715                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.222781                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.959903                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.222715                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.222781                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64661.075949                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.343666                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.023971                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.023971                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64661.075949                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294760                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.269135                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64661.075949                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294760                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.269135                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          794                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1255064                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1255858                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       800112                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       800112                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          794                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2055176                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2055970                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          794                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2055176                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2055970                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     51069250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  93985038750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  94036108000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60466755500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60466755500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     51069250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154451794250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 154502863500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     51069250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154451794250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 154502863500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.958937                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.171068                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171157                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423145                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423145                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.958937                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.222723                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.222789                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.958937                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.222723                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.222789                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64318.954660                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74884.658272                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74877.978243                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75572.864174                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75572.864174                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64318.954660                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75152.587540                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75148.403673                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64318.954660                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75152.587540                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75148.403673                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7337377                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7337377                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3701040                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890903                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890903                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1646                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22155954                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22157600                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827423808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          827476480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq        7337473                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7337473                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3700612                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1890871                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1890871                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1656                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22155644                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22157300                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827400192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          827453184                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12929320                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples     12928956                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3           12929320    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3           12928956    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12929320                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10165700000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       12928956                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10165090000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1401249                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1409749                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14190167496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14190252246                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             1255736                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1255736                       # Transaction distribution
-system.membus.trans_dist::Writeback           1046531                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            800147                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           800147                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5158297                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5158297                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198554496                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               198554496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq             1255858                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1255858                       # Transaction distribution
+system.membus.trans_dist::Writeback           1046505                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            800112                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           800112                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5158445                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5158445                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198558400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               198558400                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3102414                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3102475                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3102414    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3102475    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3102414                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7944829000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3102475                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          7945005500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11243795750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        11244435500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index b2838e173..ddc6d4e58 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.771783                       # Number of seconds simulated
-sim_ticks                                771782683000                       # Number of ticks simulated
-final_tick                               771782683000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.771725                       # Number of seconds simulated
+sim_ticks                                771725169000                       # Number of ticks simulated
+final_tick                               771725169000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140791                       # Simulator instruction rate (inst/s)
-host_op_rate                                   151681                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               70349895                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240068                       # Number of bytes of host memory used
-host_seconds                                 10970.63                       # Real time elapsed on the host
-sim_insts                                  1544563023                       # Number of instructions simulated
-sim_ops                                    1664032415                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 109963                       # Simulator instruction rate (inst/s)
+host_op_rate                                   118469                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54942138                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305172                       # Number of bytes of host memory used
+host_seconds                                 14046.14                       # Real time elapsed on the host
+sim_insts                                  1544563024                       # Number of instructions simulated
+sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             66112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         238756480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63336128                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            302158720                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        66112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           66112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    104900608                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         104900608                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1033                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            3730570                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       989627                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               4721230                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1639072                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1639072                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                85661                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            309357135                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     82064718                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               391507515                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           85661                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              85661                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         135919878                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              135919878                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         135919878                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               85661                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           309357135                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     82064718                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              527427392                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       4721230                       # Number of read requests accepted
-system.physmem.writeReqs                      1639072                       # Number of write requests accepted
-system.physmem.readBursts                     4721230                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1639072                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                301708544                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    450176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104898432                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 302158720                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              104900608                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     7034                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      11                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             66304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         238609216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     63286144                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            301961664                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        66304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           66304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    104822848                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         104822848                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1036                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            3728269                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       988846                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               4718151                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1637857                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1637857                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                85917                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            309189366                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     82006065                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               391281347                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           85917                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              85917                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         135829246                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              135829246                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         135829246                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               85917                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           309189366                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     82006065                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              527110594                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       4718151                       # Number of read requests accepted
+system.physmem.writeReqs                      1637857                       # Number of write requests accepted
+system.physmem.readBursts                     4718151                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1637857                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                301519872                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    441792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 104820544                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 301961664                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              104822848                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     6903                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      19                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              296496                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              294922                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              288553                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              293200                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              290519                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              289057                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              284695                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              280747                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              297891                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              303659                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             295750                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             302488                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             303486                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             302338                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             297681                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             292714                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              104090                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              102136                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               99204                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              100079                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               99319                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               99058                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              102867                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104266                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              105488                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              104503                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             102301                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             102956                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             103260                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102520                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104484                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102507                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              296668                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              294562                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              288307                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              292737                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              290232                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              289394                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              285167                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              280683                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              297292                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              302920                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             295430                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             301815                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             303322                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             302849                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             297025                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             292845                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103942                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              102053                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               99317                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               99871                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               99169                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               98963                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              102735                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104389                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              105226                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104532                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102159                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             102806                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             103028                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102702                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104263                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102666                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    771782536000                       # Total gap between requests
+system.physmem.totGap                    771725022000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 4721230                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 4718151                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1639072                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2775597                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1044443                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    331745                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    234202                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    153941                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     85295                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     39428                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     23872                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     18360                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1645                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      788                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      434                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      248                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1637857                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   2774626                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1044189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    331696                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    233512                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    153773                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     84990                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     39149                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     23715                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     18258                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4255                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1688                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      754                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      411                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
@@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    22873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    24573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    60114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    75847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    85447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    93235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    99435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   103341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   105611                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   106485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   107133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   108359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   110847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   113228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   106323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   103422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   101669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2755                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    22760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    24545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    59860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    75448                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    85202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    93103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    99273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   103279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   105460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   106422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   106536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   107239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   108154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   110632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   113547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   106733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   103419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   101598                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      449                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
@@ -197,120 +197,121 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      4289012                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       94.801701                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      78.923105                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     101.558340                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3414847     79.62%     79.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       675748     15.76%     95.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        96615      2.25%     97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35482      0.83%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        22807      0.53%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12154      0.28%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7173      0.17%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5164      0.12%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19022      0.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        4289012                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         98837                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        47.696531                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       32.309771                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       98.301255                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-127           95044     96.16%     96.16% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-255          1344      1.36%     97.52% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      4287400                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       94.775232                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      78.917076                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     101.448471                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3413764     79.62%     79.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       675374     15.75%     95.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        96809      2.26%     97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35249      0.82%     98.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22885      0.53%     98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12087      0.28%     99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7187      0.17%     99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5043      0.12%     99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19002      0.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        4287400                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         98767                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        47.700609                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       32.313411                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       98.282358                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-127           94950     96.14%     96.14% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-255          1367      1.38%     97.52% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::256-383           770      0.78%     98.30% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::384-511           419      0.42%     98.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-639           374      0.38%     99.10% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::640-767           356      0.36%     99.46% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-895           254      0.26%     99.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::896-1023          146      0.15%     99.87% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1151           62      0.06%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1152-1279           41      0.04%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1407            8      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1408-1535            7      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1663            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::384-511           428      0.43%     98.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-639           356      0.36%     99.09% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::640-767           374      0.38%     99.47% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-895           247      0.25%     99.72% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::896-1023          145      0.15%     99.87% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1151           66      0.07%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1152-1279           31      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1407           13      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1408-1535            9      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1663            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1792-1919            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1920-2047            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2304-2431            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-2687            3      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2944-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3200-3327            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-3711            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           98837                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         98837                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.583243                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.550199                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.089458                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              73410     74.27%     74.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1674      1.69%     75.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18461     18.68%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3603      3.65%     98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                928      0.94%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                388      0.39%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                174      0.18%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                100      0.10%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 61      0.06%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 27      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  7      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  4      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           98837                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   132409571838                       # Total ticks spent queuing
-system.physmem.totMemAccLat              220800746838                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  23570980000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       28087.41                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::1920-2047            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2688-2815            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2944-3071            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3199            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3200-3327            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3328-3455            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           98767                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         98767                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.582674                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.549780                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.086524                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              73305     74.22%     74.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1806      1.83%     76.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              18343     18.57%     94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3630      3.68%     98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                937      0.95%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                387      0.39%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                162      0.16%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                107      0.11%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 60      0.06%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 22      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  6      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           98767                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   132285118194                       # Total ticks spent queuing
+system.physmem.totMemAccLat              220621018194                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  23556240000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       28078.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46837.41                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         390.92                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         135.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      391.51                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      135.92                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46828.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         390.71                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         135.83                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      391.28                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      135.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           4.12                       # Data bus utilization in percentage
+system.physmem.busUtil                           4.11                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       3.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1710867                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    353347                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   36.29                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  21.56                       # Row buffer hit rate for writes
-system.physmem.avgGap                       121343.69                       # Average gap between requests
-system.physmem.pageHitRate                      32.49                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                16078381200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 8772926250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy               18081671400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5255351280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            50408975760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           410988240855                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           102552687000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             612138233745                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              793.150023                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   168058001250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     25771460000                       # Time in different power states
+system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1709073                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    352585                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   36.28                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  21.53                       # Row buffer hit rate for writes
+system.physmem.avgGap                       121416.62                       # Average gap between requests
+system.physmem.pageHitRate                      32.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                16073195040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 8770096500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy               18077007000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5251294800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            50404907280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           410674128390                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           102790850250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             612041479260                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              793.088667                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   168453702129                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     25769380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    577951698750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    577496605871                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                16346489040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 8919215250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy               18688846800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5365504800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            50408975760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           412404849315                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           101310048000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             613443928965                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              794.841817                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   165993972457                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     25771460000                       # Time in different power states
+system.physmem_1.actEnergy                16339027320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 8915143875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy               18669222000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5361163200                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            50404907280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           412008151545                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           101620654500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             613318269720                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              794.743144                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   166509885283                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     25769380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    580015821043                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    579440435717                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               286268512                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         223399208                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14631885                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157652290                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               150341382                       # Number of BTB hits
+system.cpu.branchPred.lookups               286277860                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         223409255                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14633591                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            157407621                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               150346120                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.362638                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                16641174                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             95.513876                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                16641206                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 65                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -430,94 +431,94 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1543565367                       # number of cpu cycles simulated
+system.cpu.numCycles                       1543450339                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           13925779                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2067423618                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   286268512                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          166982556                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1514915602                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29288421                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  253                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          919                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 656914213                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   942                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1543486763                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.434983                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.229356                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           13927699                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2067517377                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   286277860                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          166987326                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1514795150                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29291799                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  180                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          907                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 656942032                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   957                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1543369835                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.435149                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.229340                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                461116597     29.87%     29.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                465422138     30.15%     60.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                101389056      6.57%     66.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                515558972     33.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                460957271     29.87%     29.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                465455811     30.16%     60.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                101360614      6.57%     66.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                515596139     33.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1543486763                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185459                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.339382                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 74615169                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             546131714                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 850052649                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              58043724                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               14643507                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             42202613                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   760                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2037139109                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              52472329                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               14643507                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                139680975                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               464946049                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14177                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 837873228                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              86328827                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1976320354                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              26732336                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              45128593                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 125639                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1500891                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               25518898                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1985788047                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9127865226                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2432787425                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               124                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1543369835                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.185479                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.339543                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 74619350                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             545977788                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 850086533                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              58040967                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14645197                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             42200501                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   754                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2037190940                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              52475133                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14645197                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                139685845                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               464851768                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          13523                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 837895691                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              86277811                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1976364426                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              26735694                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              45105241                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 125505                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1481556                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               25500508                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1985835865                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            9128071192                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2432849079                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               136                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                310889102                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                151                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            141                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 111344488                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            542536301                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           199301557                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          26908887                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29198248                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1947883742                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 210                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1857409514                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13500100                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       283851537                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    646881302                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             40                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1543486763                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.203385                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.151093                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                310936920                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                149                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            140                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 111342876                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            542549398                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           199301403                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          26926926                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         29153523                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1947926711                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 208                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1857446823                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13498178                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       283894503                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    646939215                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             38                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1543369835                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.203501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.151095                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           590762659     38.27%     38.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           325764931     21.11%     59.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           378272466     24.51%     83.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           219653351     14.23%     98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            29027182      1.88%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                6174      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           590630846     38.27%     38.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           325771475     21.11%     59.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           378267234     24.51%     83.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           219666416     14.23%     98.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            29027688      1.88%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                6176      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1543486763                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1543369835                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu               166053840     40.99%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   1992      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu               166059149     40.99%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   1996      0.00%     40.99% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
@@ -545,13 +546,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              191416352     47.25%     88.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              47630536     11.76%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              191393147     47.24%     88.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              47682914     11.77%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1138248479     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               801009      0.04%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1138268714     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               801071      0.04%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -573,102 +574,102 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              26      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              28      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            532044411     28.64%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186315567     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            532058987     28.64%     89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186318001     10.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1857409514                       # Type of FU issued
-system.cpu.iq.rate                           1.203324                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   405102720                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.218101                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5676908390                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2231748222                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805707256                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 221                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                208                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           66                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2262512110                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     124                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17814082                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1857446823                       # Type of FU issued
+system.cpu.iq.rate                           1.203438                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   405137206                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.218115                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5676898637                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2231834122                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1805736851                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 228                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                232                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           68                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2262583902                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     127                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         17817639                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     84229967                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        66402                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads     84243064                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        66651                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation        13168                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24454512                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores     24454358                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      4520775                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4802645                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      4525889                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4805394                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               14643507                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25316113                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1330365                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1947884031                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               14645197                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                25323327                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1332663                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1947926995                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             542536301                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            199301557                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                148                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 158933                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1170467                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewDispLoadInsts             542549398                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            199301403                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                146                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 158839                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1172731                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          13168                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        7700956                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8705023                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             16405979                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1827745758                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             516865735                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29663756                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect        7701738                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8706499                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             16408237                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1827783249                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             516881888                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29663574                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            79                       # number of nop insts executed
-system.cpu.iew.exec_refs                    698617938                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                229554698                       # Number of branches executed
-system.cpu.iew.exec_stores                  181752203                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.184106                       # Inst execution rate
-system.cpu.iew.wb_sent                     1808737138                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1805707322                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1169287953                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1689671414                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            76                       # number of nop insts executed
+system.cpu.iew.exec_refs                    698636146                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                229555717                       # Number of branches executed
+system.cpu.iew.exec_stores                  181754258                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.184219                       # Inst execution rate
+system.cpu.iew.wb_sent                     1808767141                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1805736919                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1169322951                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1689713401                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.169829                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.692021                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.169935                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.692024                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       257958644                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       258002520                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14631182                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1504006174                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.106400                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.024308                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14632889                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1503882923                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.106491                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.024391                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    923727407     61.42%     61.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    250637926     16.66%     78.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110048306      7.32%     85.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     55269063      3.67%     89.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29308073      1.95%     91.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     34102690      2.27%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24713726      1.64%     94.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18129256      1.21%     96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     58069727      3.86%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    923604765     61.41%     61.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    250635322     16.67%     78.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110056363      7.32%     85.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55280526      3.68%     89.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29292132      1.95%     91.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     34092515      2.27%     93.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24716046      1.64%     94.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     18126603      1.21%     96.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58078651      3.86%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1504006174                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1544563041                       # Number of instructions committed
-system.cpu.commit.committedOps             1664032433                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1503882923                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
+system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      633153379                       # Number of memory references committed
 system.cpu.commit.loads                     458306334                       # Number of loads committed
 system.cpu.commit.membars                          62                       # Number of memory barriers committed
-system.cpu.commit.branches                  213462426                       # Number of branches committed
+system.cpu.commit.branches                  213462427                       # Number of branches committed
 system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1477900421                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu       1030178729     61.91%     61.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu       1030178730     61.91%     61.91% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.95% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.95% # Class of committed instruction
@@ -701,77 +702,77 @@ system.cpu.commit.op_class_0::MemRead       458306334     27.54%     89.49% # Cl
 system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1664032433                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              58069727                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3367926925                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883468057                       # The number of ROB writes
-system.cpu.timesIdled                             846                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           78604                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1544563023                       # Number of Instructions Simulated
-system.cpu.committedOps                    1664032415                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.999354                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.999354                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.000646                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.000646                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2175695472                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1261559121                       # number of integer regfile writes
+system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              58078651                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3367838627                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3883562090                       # The number of ROB writes
+system.cpu.timesIdled                             851                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           80504                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
+system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.999280                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.999280                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.000721                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.000721                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2175739809                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1261583749                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        38                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       48                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                6965502930                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                551873305                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675842878                       # number of misc regfile reads
+system.cpu.fp_regfile_writes                       50                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                6965641029                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                551880821                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               675853491                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements          17005493                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.964646                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           638183172                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          17006005                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.526931                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          79063000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.964646                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999931                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999931                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements          17005885                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.964949                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           638186886                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          17006397                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.526284                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          78340000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.964949                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999932                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999932                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          392                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          423                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1335677307                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1335677307                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    469397613                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       469397613                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    168785441                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      168785441                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1335687679                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1335687679                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    469400845                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       469400845                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    168785923                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      168785923                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     638183054                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        638183054                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    638183054                       # number of overall hits
-system.cpu.dcache.overall_hits::total       638183054                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     17351867                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      17351867                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3800606                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3800606                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     638186768                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        638186768                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    638186768                       # number of overall hits
+system.cpu.dcache.overall_hits::total       638186768                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     17353625                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      17353625                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3800124                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3800124                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     21152473                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       21152473                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21152475                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21152475                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 417182903209                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 149917932873                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       358750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       358750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 567100836082                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 567100836082                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 567100836082                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 567100836082                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    486749480                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    486749480                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     21153749                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       21153749                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21153751                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21153751                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 417050356298                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 149886013526                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       204500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       204500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 566936369824                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 566936369824                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 566936369824                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 566936369824                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    486754470                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    486754470                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
@@ -780,72 +781,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    659335527                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    659335527                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    659335529                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    659335529                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035648                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.035648                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022022                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.022022                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    659340517                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    659340517                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    659340519                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    659340519                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035652                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.035652                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022019                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.022019                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032082                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032082                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032082                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032082                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26810.143480                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26810.140945                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20723795                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3315809                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            944207                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67033                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.948360                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    49.465323                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032083                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032083                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032083                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032083                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        51125                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        51125                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26800.751480                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26800.748946                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     20736521                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3309459                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            945396                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67047                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.934217                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    49.360285                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      4835251                       # number of writebacks
-system.cpu.dcache.writebacks::total           4835251                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3083373                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3083373                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1063096                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1063096                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      4830628                       # number of writebacks
+system.cpu.dcache.writebacks::total           4830628                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3084713                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3084713                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1062640                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1062640                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4146469                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4146469                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4146469                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4146469                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14268494                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total     14268494                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737510                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2737510                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4147353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4147353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4147353                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4147353                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14268912                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total     14268912                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737484                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2737484                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     17006004                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     17006004                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     17006005                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     17006005                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data     17006396                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     17006396                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     17006397                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     17006397                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        67750                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        67750                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 444180625298                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 444180693048                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 444043827535                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 444043895285                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029314                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029314                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
@@ -856,343 +857,343 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025793
 system.cpu.dcache.demand_mshr_miss_rate::total     0.025793                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025793                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.025793                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        67750                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        67750                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               588                       # number of replacements
-system.cpu.icache.tags.tagsinuse           446.068543                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           656912599                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1076                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          610513.567844                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               589                       # number of replacements
+system.cpu.icache.tags.tagsinuse           446.078018                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           656940406                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1077                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          609972.521820                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   446.068543                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.871228                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.871228                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   446.078018                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.871246                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.871246                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          488                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.953125                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1313829498                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1313829498                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    656912599                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       656912599                       # number of ReadReq hits
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-system.cpu.icache.demand_hits::total        656912599                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    656912599                       # number of overall hits
-system.cpu.icache.overall_hits::total       656912599                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1612                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1612                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1612                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1612                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1612                       # number of overall misses
-system.cpu.icache.overall_misses::total          1612                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    102924516                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    102924516                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    102924516                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    102924516                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    102924516                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    102924516                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    656914211                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    656914211                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    656914211                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    656914211                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    656914211                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    656914211                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses        1313885139                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1313885139                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    656940406                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst         1625                       # number of ReadReq misses
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst    105016775                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst    656942031                       # number of ReadReq accesses(hits+misses)
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 63848.955335                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 63848.955335                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        17306                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          307                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               186                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               8                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    93.043011                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    38.375000                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692                       # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64625.707692                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        17596                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          547                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               191                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               9                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    92.125654                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    60.777778                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          536                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          536                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          536                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          536                       # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total          536                       # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76203217                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76203217                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     76203217                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76203217                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     76203217                       # number of overall MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total     76192959                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued     10941726                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified     11630409                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       431114                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued     10938258                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified     11626730                       # number of prefetch candidates identified
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 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4654951                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements          4713207                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16130.406064                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           15325447                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          4729134                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             3.240646                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      29468558500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  5233.732135                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.908605                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7574.796716                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3302.968608                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.319442                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001154                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.462329                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.201597                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.984522                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          731                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15196                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.sampled_refs          4726123                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             3.242364                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      29466216500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  5234.041152                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.862974                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7585.301260                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3292.214193                       # Average occupied blocks per requestor
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+system.cpu.l2cache.ReadReq_mshr_misses::total      2747642                       # number of ReadReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       992835                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       992835                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       981042                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       981042                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1036                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      3727648                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      3728684                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1036                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      3727648                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       992835                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      4721519                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     66562530                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212706720467                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212773282997                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  70893901794                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  70893901794                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  91380975745                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  91380975745                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66562530                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304087696212                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 304154258742                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66562530                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304087696212                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  70893901794                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 375048160536                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.961931                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.192489                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.192547                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358628                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358628                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.960037                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.219332                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.219379                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.960037                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.219332                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358368                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358368                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.961931                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.219191                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.219238                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.961931                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.219191                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.277809                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.277614                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904                       # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       14269530                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      14269530                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4835251                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq      1300143                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737551                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737551                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2152                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     38847261                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          38849413                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1397840384                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1397909248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1300143                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     23142477                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.056180                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.230269                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq       14269946                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      14269946                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4830628                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq      1298291                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2737528                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2737528                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2154                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     38843422                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          38845576                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1397569600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         1397638528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1298291                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     23136394                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.056115                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.230143                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3           21842334     94.38%     94.38% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4            1300143      5.62%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3           21838103     94.39%     94.39% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4            1298291      5.61%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       23142477                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    15756418748                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       23136394                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    15749679999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1812271                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1817030                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   26100835834                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   26101043977                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          3.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq             3739202                       # Transaction distribution
-system.membus.trans_dist::ReadResp            3739202                       # Transaction distribution
-system.membus.trans_dist::Writeback           1639072                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            982028                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           982028                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     11081532                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               11081532                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    407059328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               407059328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq             3736842                       # Transaction distribution
+system.membus.trans_dist::ReadResp            3736842                       # Transaction distribution
+system.membus.trans_dist::Writeback           1637857                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            981309                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           981309                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     11074159                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               11074159                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    406784512                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               406784512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           6360302                       # Request fanout histogram
+system.membus.snoop_fanout::samples           6356008                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 6360302    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 6356008    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             6360302                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         14493239223                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             6356008                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         14483850639                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        25671846860                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        25655332661                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index a5246083c..93ba57c1e 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,40 +1,40 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.832017                       # Number of seconds simulated
-sim_ticks                                832017490000                       # Number of ticks simulated
-final_tick                               832017490000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                832017490500                       # Number of ticks simulated
+final_tick                               832017490500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1937211                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2087051                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1043527090                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301332                       # Number of bytes of host memory used
-host_seconds                                   797.31                       # Real time elapsed on the host
-sim_insts                                  1544563041                       # Number of instructions simulated
-sim_ops                                    1664032433                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1379227                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1485908                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              742955189                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295688                       # Number of bytes of host memory used
+host_seconds                                  1119.88                       # Real time elapsed on the host
+sim_insts                                  1544563042                       # Number of instructions simulated
+sim_ops                                    1664032434                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        6178262356                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst        6178262360                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        1581387671                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           7759650027                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   6178262356                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      6178262356                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total           7759650031                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   6178262360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      6178262360                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      624158392                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         624158392                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst         1544565589                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst         1544565590                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data          454909197                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            1999474786                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total            1999474787                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data         172586108                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total            172586108                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst           7425640002                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1900666380                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9326306382                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1900666379                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9326306381                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst      7425640002                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total         7425640002                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data           750174605                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total              750174605                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst          7425640002                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2650840985                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10076480987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2650840984                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10076480986                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -153,11 +153,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1664034981                       # number of cpu cycles simulated
+system.cpu.numCycles                       1664034982                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1544563041                       # Number of instructions committed
-system.cpu.committedOps                    1664032433                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                  1544563042                       # Number of instructions committed
+system.cpu.committedOps                    1664032434                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1477900422                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_func_calls                    27330256                       # number of times a function call or return occured
@@ -168,18 +168,18 @@ system.cpu.num_int_register_reads          2605402942                       # nu
 system.cpu.num_int_register_writes         1125475224                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads           4992096236                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads           4992096239                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes           518236214                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     633153380                       # number of memory refs
 system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1664034980.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1664034981.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                         213462426                       # Number of branches fetched
+system.cpu.Branches                         213462427                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                1030178775     61.91%     61.91% # Class of executed instruction
+system.cpu.op_class::IntAlu                1030178776     61.91%     61.91% # Class of executed instruction
 system.cpu.op_class::IntMult                   700322      0.04%     61.95% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     61.95% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     61.95% # Class of executed instruction
@@ -212,9 +212,9 @@ system.cpu.op_class::MemRead                458306334     27.54%     89.49% # Cl
 system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1664032480                       # Class of executed instruction
-system.membus.trans_dist::ReadReq          1999474724                       # Transaction distribution
-system.membus.trans_dist::ReadResp         1999474785                       # Transaction distribution
+system.cpu.op_class::total                 1664032481                       # Class of executed instruction
+system.membus.trans_dist::ReadReq          1999474725                       # Transaction distribution
+system.membus.trans_dist::ReadResp         1999474786                       # Transaction distribution
 system.membus.trans_dist::WriteReq          172586047                       # Transaction distribution
 system.membus.trans_dist::WriteResp         172586047                       # Transaction distribution
 system.membus.trans_dist::SoftPFReq                 1                       # Transaction distribution
@@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp                1                       # Tr
 system.membus.trans_dist::LoadLockedReq            61                       # Transaction distribution
 system.membus.trans_dist::StoreCondReq             61                       # Transaction distribution
 system.membus.trans_dist::StoreCondResp            61                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   3089131178                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   3089131180                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port   1254990610                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             4344121788                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   6178262356                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total             4344121790                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   6178262360                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   2205546063                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              8383808419                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              8383808423                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples        2172060894                       # Request fanout histogram
+system.membus.snoop_fanout::samples        2172060895                       # Request fanout histogram
 system.membus.snoop_fanout::mean             2.711106                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.453249                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::2               627495305     28.89%     28.89% # Request fanout histogram
-system.membus.snoop_fanout::3              1544565589     71.11%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::3              1544565590     71.11%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               2                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               3                       # Request fanout histogram
-system.membus.snoop_fanout::total          2172060894                       # Request fanout histogram
+system.membus.snoop_fanout::total          2172060895                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 893b8aa6f..15b1ad4ad 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.363663                       # Number of seconds simulated
-sim_ticks                                2363662966500                       # Number of ticks simulated
-final_tick                               2363662966500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                2363662967500                       # Number of ticks simulated
+final_tick                               2363662967500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1021163                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1100446                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1568591191                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309800                       # Number of bytes of host memory used
-host_seconds                                  1506.87                       # Real time elapsed on the host
-sim_insts                                  1538759601                       # Number of instructions simulated
-sim_ops                                    1658228914                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 734295                       # Simulator instruction rate (inst/s)
+host_op_rate                                   791306                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1127938114                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305424                       # Number of bytes of host memory used
+host_seconds                                  2095.56                       # Real time elapsed on the host
+sim_insts                                  1538759602                       # Number of instructions simulated
+sim_ops                                    1658228915                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
@@ -154,11 +154,11 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       4727325933                       # number of cpu cycles simulated
+system.cpu.numCycles                       4727325935                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1538759601                       # Number of instructions committed
-system.cpu.committedOps                    1658228914                       # Number of ops (including micro ops) committed
+system.cpu.committedInsts                  1538759602                       # Number of instructions committed
+system.cpu.committedOps                    1658228915                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1477900422                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_func_calls                    27330256                       # number of times a function call or return occured
@@ -169,18 +169,18 @@ system.cpu.num_int_register_reads          2601860372                       # nu
 system.cpu.num_int_register_writes         1125475224                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads           6356387675                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads           6356387678                       # number of times the CC registers were read
 system.cpu.num_cc_register_writes           518236214                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     633153380                       # number of memory refs
 system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               4727325932.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               4727325934.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                         213462426                       # Number of branches fetched
+system.cpu.Branches                         213462427                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                1030178775     61.91%     61.91% # Class of executed instruction
+system.cpu.op_class::IntAlu                1030178776     61.91%     61.91% # Class of executed instruction
 system.cpu.op_class::IntMult                   700322      0.04%     61.95% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     61.95% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     61.95% # Class of executed instruction
@@ -213,14 +213,14 @@ system.cpu.op_class::MemRead                458306334     27.54%     89.49% # Cl
 system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1664032480                       # Class of executed instruction
+system.cpu.op_class::total                 1664032481                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           9111140                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4083.733675                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4083.733673                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           618380069                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9115236                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             67.840270                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       25164658000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4083.733675                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle       25164659000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4083.733673                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997005                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997005                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -347,9 +347,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 7                       # number of replacements
 system.cpu.icache.tags.tagsinuse           515.012767                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs          1544564952                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs          1544564953                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               638                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          2420948.200627                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          2420948.202194                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   515.012767                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.251471                       # Average percentage of cache occupancy
@@ -359,14 +359,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           24
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          606                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.308105                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        3089131818                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       3089131818                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst   1544564952                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      1544564952                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    1544564952                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       1544564952                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   1544564952                       # number of overall hits
-system.cpu.icache.overall_hits::total      1544564952                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        3089131820                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       3089131820                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst   1544564953                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1544564953                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1544564953                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1544564953                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1544564953                       # number of overall hits
+system.cpu.icache.overall_hits::total      1544564953                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          638                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           638                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          638                       # number of demand (read+write) misses
@@ -379,12 +379,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     34207000
 system.cpu.icache.demand_miss_latency::total     34207000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     34207000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     34207000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   1544565590                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   1544565590                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   1544565590                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   1544565590                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   1544565590                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   1544565590                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   1544565591                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1544565591                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1544565591                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1544565591                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1544565591                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1544565591                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
@@ -431,14 +431,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1926075                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31008.535045                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        31008.535032                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            8967572                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs          1955843                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             4.585016                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     150067842000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.warmup_cycle     150067843000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160482                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.inst    23.876098                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498452                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.477849                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000729                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.467728                       # Average percentage of cache occupancy
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index f50e78f71..fc0b314ed 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.131756                       # Number of seconds simulated
-sim_ticks                                131756455500                       # Number of ticks simulated
-final_tick                               131756455500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.131767                       # Number of seconds simulated
+sim_ticks                                131767151500                       # Number of ticks simulated
+final_tick                               131767151500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 150043                       # Simulator instruction rate (inst/s)
-host_op_rate                                   158169                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              114724713                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245376                       # Number of bytes of host memory used
-host_seconds                                  1148.46                       # Real time elapsed on the host
-sim_insts                                   172317809                       # Number of instructions simulated
-sim_ops                                     181650742                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 176753                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186327                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              135158895                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309748                       # Number of bytes of host memory used
+host_seconds                                   974.91                       # Real time elapsed on the host
+sim_insts                                   172317810                       # Number of instructions simulated
+sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            138304                       # Number of bytes read from this memory
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          138304                       # Nu
 system.physmem.num_reads::cpu.inst               2161                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3869                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1049694                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               829652                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1879346                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1049694                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1049694                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1049694                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              829652                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1879346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1049609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               829585                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1879194                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1049609                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1049609                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1049609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              829585                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1879194                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          3869                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        3869                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -52,11 +52,11 @@ system.physmem.perBankRdBursts::7                 222                       # Pe
 system.physmem.perBankRdBursts::8                 249                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 218                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                201                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                200                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                183                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                218                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                224                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                204                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                205                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    131756361000                       # Total gap between requests
+system.physmem.totGap                    131767057000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3618                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       238                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       237                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          895                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      274.663687                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.028895                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     274.690311                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            245     27.37%     27.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          357     39.89%     67.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           81      9.05%     76.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           51      5.70%     82.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           43      4.80%     86.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           26      2.91%     89.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           22      2.46%     92.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           16      1.79%     93.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           54      6.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            895                       # Bytes accessed per row activation
-system.physmem.totQLat                       26795500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  99339250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          907                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      272.793826                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.627814                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     276.033343                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            260     28.67%     28.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          352     38.81%     67.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           83      9.15%     76.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           54      5.95%     82.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           42      4.63%     87.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           20      2.21%     89.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           22      2.43%     91.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           19      2.09%     93.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           55      6.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            907                       # Bytes accessed per row activation
+system.physmem.totQLat                       28218000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 100761750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     19345000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6925.69                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7293.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25675.69                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26043.36                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
@@ -216,49 +216,49 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       2968                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       2961                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.71                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.53                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     34054370.90                       # Average gap between requests
-system.physmem.pageHitRate                      76.71                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3069360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1674750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16169400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     34057135.44                       # Average gap between requests
+system.physmem.pageHitRate                      76.53                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3114720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1699500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16200600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             8605343760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3539591415                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            75945924750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              88111773435                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.773046                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   126343729250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      4399460000                       # Time in different power states
+system.physmem_0.refreshEnergy             8606360880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3598001595                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            75904039500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              88129416795                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.827838                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   126271035750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      4399980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1010946750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1095966750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3681720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2008875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13774800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3742200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2041875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13954200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             8605343760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3587668065                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            75903760500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              88116237720                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.806861                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   126271447000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      4399460000                       # Time in different power states
+system.physmem_1.refreshEnergy             8606360880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3577878315                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75921691500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              88125668970                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.799395                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   126300767500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      4399980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1080937500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1066235000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                49934475                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          39666705                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           5743450                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24374227                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23299942                       # Number of BTB hits
+system.cpu.branchPred.lookups                49934214                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39669228                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5745476                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24397430                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23302007                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.592537                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1908561                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                139                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             95.510089                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1908013                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                140                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,24 +377,24 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        263512911                       # number of cpu cycles simulated
+system.cpu.numCycles                        263534303                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   172317809                       # Number of instructions committed
-system.cpu.committedOps                     181650742                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      11759003                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   172317810                       # Number of instructions committed
+system.cpu.committedOps                     181650743                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      11762366                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.529226                       # CPI: cycles per instruction
-system.cpu.ipc                               0.653925                       # IPC: instructions per cycle
-system.cpu.tickCycles                       257129929                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         6382982                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.529350                       # CPI: cycles per instruction
+system.cpu.ipc                               0.653872                       # IPC: instructions per cycle
+system.cpu.tickCycles                       257146871                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         6387432                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1377.698550                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40765676                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1377.696434                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40764379                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22522.472928                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22521.756354                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1377.698550                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  1377.696434                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.336352                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.336352                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
@@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           83
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1358                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.431641                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          81538034                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         81538034                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28357756                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28357756                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          81535444                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         81535444                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28356460                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28356460                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12362641                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       12362641                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          465                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           465                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          464                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           464                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40720397                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40720397                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40720862                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40720862                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          789                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           789                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data      40719101                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40719101                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40719565                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40719565                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          791                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           791                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         1646                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         1646                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         2435                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2435                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2436                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2436                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     57528734                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     57528734                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    127304750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    127304750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    184833484                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    184833484                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    184833484                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    184833484                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28358545                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28358545                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         2437                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2437                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2438                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2438                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     59434234                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     59434234                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    127677000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    127677000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    187111234                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    187111234                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    187111234                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    187111234                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28357251                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28357251                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          466                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          466                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          465                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          465                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     40722832                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40722832                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     40723298                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40723298                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     40721538                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40721538                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40722003                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40722003                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000133                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000133                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002146                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.002146                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002151                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.002151                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000060                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000060                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75906.974949                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75875.814450                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76779.332786                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76747.840033                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           78                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           80                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          548                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          548                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          626                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          626                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          626                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          626                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          628                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          628                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          628                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          628                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1098                       # number of WriteReq MSHR misses
@@ -498,91 +498,91 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1809
 system.cpu.dcache.demand_mshr_misses::total         1809                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1810                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51124264                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     51124264                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85250250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     85250250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52911264                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     52911264                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85210500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85210500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        69500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        69500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    136374514                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    136374514                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    136444014                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    136444014                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    138121764                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    138121764                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    138191264                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    138191264                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002146                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002146                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002151                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002151                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74418.092827                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        69500                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        69500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2891                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1424.909257                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            71597353                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4688                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15272.472910                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2892                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1425.992142                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            71598587                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4690                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15266.223241                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1424.909257                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.695756                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.695756                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1797                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1425.992142                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.696285                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.696285                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1798                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          490                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          129                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1067                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.877441                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         143208772                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        143208772                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     71597353                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        71597353                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      71597353                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         71597353                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     71597353                       # number of overall hits
-system.cpu.icache.overall_hits::total        71597353                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4689                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4689                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4689                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4689                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4689                       # number of overall misses
-system.cpu.icache.overall_misses::total          4689                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    200357248                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    200357248                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    200357248                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    200357248                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    200357248                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    200357248                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     71602042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     71602042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     71602042                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     71602042                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     71602042                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     71602042                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000065                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000065                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000065                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000065                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000065                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000065                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42729.206227                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42729.206227                       # average overall miss latency
+system.cpu.icache.tags.age_task_id_blocks_1024::3          128                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1069                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.877930                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         143211246                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        143211246                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     71598587                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        71598587                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      71598587                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         71598587                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     71598587                       # number of overall hits
+system.cpu.icache.overall_hits::total        71598587                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4691                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4691                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4691                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4691                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4691                       # number of overall misses
+system.cpu.icache.overall_misses::total          4691                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    200040248                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    200040248                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    200040248                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    200040248                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    200040248                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    200040248                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     71603278                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     71603278                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     71603278                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     71603278                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     71603278                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     71603278                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.412492                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.412492                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42643.412492                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.412492                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42643.412492                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,66 +591,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4689                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4689                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4689                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4689                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4689                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4689                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    192396752                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    192396752                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    192396752                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    192396752                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    192396752                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    192396752                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000065                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000065                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41031.510343                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41031.510343                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41031.510343                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41031.510343                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41031.510343                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41031.510343                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4691                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4691                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4691                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4691                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4691                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4691                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    192077752                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    192077752                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    192077752                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    192077752                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    192077752                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    192077752                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40946.014069                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40946.014069                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40946.014069                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40946.014069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40946.014069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40946.014069                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2001.520504                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2606                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2003.582702                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2608                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             2787                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.935056                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.935773                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.029170                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1507.676370                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   490.814964                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.029186                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1509.739376                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   490.814139                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046011                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046074                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.014978                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.061082                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.061144                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         2787                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          520                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          157                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2005                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2007                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.085052                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            56005                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           56005                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         2525                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses            56021                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           56021                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         2527                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           80                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           2605                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           2607                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2525                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         2527                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           88                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2613                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2525                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            2615                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2527                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           88                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2613                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2615                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         2164                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data          632                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total         2796                       # number of ReadReq misses
@@ -662,52 +662,52 @@ system.cpu.l2cache.demand_misses::total          3886                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2164                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1722                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3886                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    161196250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     49637250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    210833500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     84066750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     84066750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    161196250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    133704000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    294900250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    161196250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    133704000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    294900250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4689                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    160854250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     51424250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    212278500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     84027000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     84027000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    160854250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    135451250                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data    135451250                       # number of overall miss cycles
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+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4691                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          712                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5401                       # number of ReadReq accesses(hits+misses)
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 system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1098                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4689                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         4691                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         1810                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         6499                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4689                       # number of overall (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data         1810                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         6499                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.461506                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total         6501                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.461309                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.887640                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.517682                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.517490                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992714                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461506                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461309                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.951381                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.597938                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461506                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.597754                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461309                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.951381                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.597938                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74489.949168                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75405.400572                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77125.458716                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77125.458716                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74489.949168                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.599303                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75887.866701                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74489.949168                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.599303                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75887.866701                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.597754                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74331.908503                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81367.484177                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 75922.210300                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77088.990826                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77088.990826                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74331.908503                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78659.262485                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76249.485332                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74331.908503                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78659.262485                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76249.485332                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -736,70 +736,70 @@ system.cpu.l2cache.demand_mshr_misses::total         3870
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2162                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3870                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    134003000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     40696500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    174699500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     70437750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     70437750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    134003000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    111134250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    245137250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    134003000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    111134250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    245137250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.461079                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    133664500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     42488500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    176153000                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     70398000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    133664500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    112886500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    246551000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    133664500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    112886500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    246551000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.460883                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.514719                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.514529                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992714                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461079                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.460883                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.595476                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461079                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.595293                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.460883                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.595476                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.595293                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           5401                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          5400                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           5403                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5402                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9377                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9381                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3636                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             13013                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       300032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             13017                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       300160                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             416896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             417024                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         6515                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         6517                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3               6515    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3               6517    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           6515                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        3273500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           6517                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        3274500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7496248                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7498748                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3020486                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3019736                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq                2779                       # Transaction distribution
 system.membus.trans_dist::ReadResp               2779                       # Transaction distribution
@@ -820,9 +820,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                3869                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4526500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4517000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20559750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20556500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 3b1c45895..e84c7e623 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,46 +1,46 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.085027                       # Number of seconds simulated
-sim_ticks                                 85027009000                       # Number of ticks simulated
-final_tick                                85027009000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.085032                       # Number of seconds simulated
+sim_ticks                                 85032044000                       # Number of ticks simulated
+final_tick                                85032044000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 123827                       # Simulator instruction rate (inst/s)
-host_op_rate                                   130534                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61105425                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242728                       # Number of bytes of host memory used
-host_seconds                                  1391.48                       # Real time elapsed on the host
-sim_insts                                   172303021                       # Number of instructions simulated
-sim_ops                                     181635953                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  98638                       # Simulator instruction rate (inst/s)
+host_op_rate                                   103981                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48678127                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307440                       # Number of bytes of host memory used
+host_seconds                                  1746.82                       # Real time elapsed on the host
+sim_insts                                   172303022                       # Number of instructions simulated
+sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            127040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             47680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher        71040                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               245760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             47488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher        71360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               245888                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       127040                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          127040                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst               1985                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                745                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         1110                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3840                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1494113                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               560763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher       835499                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2890376                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1494113                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1494113                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1494113                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              560763                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher       835499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2890376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3840                       # Number of read requests accepted
+system.physmem.num_reads::cpu.data                742                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         1115                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3842                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1494025                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               558472                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher       839213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2891710                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1494025                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1494025                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1494025                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              558472                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher       839213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2891710                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3842                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3840                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3842                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   245760                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   245888                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    245760                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    245888                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -48,11 +48,11 @@ system.physmem.neitherReadNorWriteReqs              0                       # Nu
 system.physmem.perBankRdBursts::0                 309                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 220                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 142                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 304                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 310                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 300                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 302                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 262                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 237                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 233                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 219                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                292                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     85026865500                       # Total gap between requests
+system.physmem.totGap                     85031900500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3840                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3842                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,16 +94,16 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      2543                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       851                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        86                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        41                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      2554                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       839                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       163                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        88                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                        36                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
@@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          767                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      319.332464                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     200.822648                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     307.559029                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            236     30.77%     30.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          188     24.51%     55.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           81     10.56%     65.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           90     11.73%     77.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           32      4.17%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           41      5.35%     87.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           12      1.56%     88.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           16      2.09%     90.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           71      9.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            767                       # Bytes accessed per row activation
-system.physmem.totQLat                       42919435                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 114919435                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     19200000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11176.94                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          763                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      320.083879                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     201.433795                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     309.783352                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            232     30.41%     30.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          191     25.03%     55.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           88     11.53%     66.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           86     11.27%     78.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           27      3.54%     81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           37      4.85%     86.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           11      1.44%     88.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           17      2.23%     90.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           74      9.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            763                       # Bytes accessed per row activation
+system.physmem.totQLat                       43141443                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 115178943                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     19210000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11228.90                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29926.94                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29978.90                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.89                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.89                       # Average system read bandwidth in MiByte/s
@@ -218,51 +218,51 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         2.30                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                       3071                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.97                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.93                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22142412.89                       # Average gap between requests
-system.physmem.pageHitRate                      79.97                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    2691360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1468500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16192800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     22132196.90                       # Average gap between requests
+system.physmem.pageHitRate                      79.93                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    2729160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1489125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16177200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             5553475200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2327866605                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            48973677750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              56875372215                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.916551                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    81470624236                       # Time in different power states
+system.physmem_0.actBackEnergy             2330695800                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            48971187750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              56875754235                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.921152                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    81466351731                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      2839200000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       716299514                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       720558269                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3107160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1695375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13657800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3016440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1645875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13548600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             5553475200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2285718525                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            49010649750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              56868303810                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.833418                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    81532427147                       # Time in different power states
+system.physmem_1.actBackEnergy             2293230555                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            49004052000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              56868968670                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.841346                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    81522647918                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      2839200000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       654496603                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       665486082                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                85926168                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          68405800                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6016539                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             40105937                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                39014203                       # Number of BTB hits
+system.cpu.branchPred.lookups                85925704                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          68401753                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6018362                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             40106814                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                39018678                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.277874                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3700977                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              81896                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.286905                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3705148                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              81894                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,96 +381,96 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        170054019                       # number of cpu cycles simulated
+system.cpu.numCycles                        170064089                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5612946                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      349281739                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85926168                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42715180                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     158272644                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12047045                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1757                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5613343                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      349288276                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85925704                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42723826                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     158284040                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12050671                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1737                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         2232                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  78951619                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 17953                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          169913124                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.150597                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.047113                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         2225                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  78959765                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 17996                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          169926703                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.150511                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.047128                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 17360928     10.22%     10.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30199989     17.77%     27.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31841897     18.74%     46.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 90510310     53.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 17361476     10.22%     10.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30212798     17.78%     28.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31840839     18.74%     46.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 90511590     53.27%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            169913124                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.505287                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.053946                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17565564                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              17109843                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 122664763                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6724358                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5848596                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11135936                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                189930                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              306620744                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              27649027                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5848596                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37751386                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8466295                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         579465                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 108929053                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8338329                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              278664885                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13415182                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3050613                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 842331                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2187361                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  37352                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            26454                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           483122463                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1196977553                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        297589838                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3006277                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            169926703                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.505255                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.053863                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17566577                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              17110905                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 122676579                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6722207                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5850435                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11136607                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                190140                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              306627324                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              27647944                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5850435                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37756146                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8468505                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         579113                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 108935441                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8337063                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              278668040                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13416082                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3052051                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 841470                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2187697                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  36000                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            26450                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           483113762                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1196983953                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        297587542                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3006013                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                190145534                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              23528                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          23432                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13338171                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             34140942                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14477069                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2549253                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1790153                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  264824262                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               45858                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 214907174                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5191222                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        83234167                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    219950944                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            642                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     169913124                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.264806                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.017451                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                190136833                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              23525                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          23424                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13336678                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             34143660                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14476609                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2548114                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1810648                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  264825192                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               45854                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 214913936                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5193552                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        83235092                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    219939501                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            638                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     169926703                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.264745                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.017460                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            52840350     31.10%     31.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            36091754     21.24%     52.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            65793999     38.72%     91.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            13568282      7.99%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1571301      0.92%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               47256      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 182      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            52848454     31.10%     31.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            36099011     21.24%     52.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            65787739     38.72%     91.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13574201      7.99%     99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1569834      0.92%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               47276      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 188      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       169913124                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       169926703                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                35600908     66.11%     66.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 152918      0.28%     66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                35606881     66.11%     66.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 152777      0.28%     66.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.39% # attempts to use FU when none available
@@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.39% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd              1064      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp             35736      0.07%     66.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               241      0.00%     66.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd              1069      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp             35731      0.07%     66.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               243      0.00%     66.46% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc             1033      0.00%     66.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult            34370      0.06%     66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc             1036      0.00%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult            34373      0.06%     66.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               14078817     26.14%     92.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3947857      7.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               14081261     26.14%     92.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3945561      7.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             167349433     77.87%     77.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               918954      0.43%     78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             167354642     77.87%     77.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               918991      0.43%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.30% # Type of FU issued
@@ -523,105 +523,105 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.30% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33017      0.02%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33018      0.02%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          165198      0.08%     78.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          245711      0.11%     78.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          165174      0.08%     78.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          245708      0.11%     78.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         460497      0.21%     78.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206696      0.10%     78.85% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         460494      0.21%     78.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206680      0.10%     78.85% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.88% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             32005154     14.89%     93.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13374554      6.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             32007537     14.89%     93.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13373732      6.22%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              214907174                       # Type of FU issued
-system.cpu.iq.rate                           1.263758                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    53853149                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.250588                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          654819591                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         346099299                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    204603377                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3952252                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2011948                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1806382                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266627232                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2133091                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1600790                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              214913936                       # Type of FU issued
+system.cpu.iq.rate                           1.263723                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    53859137                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.250608                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          654855291                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         346101904                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    204603491                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3951973                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2011176                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1806361                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266640239                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2132834                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1601131                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6244798                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7531                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         7120                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1832435                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6247516                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7571                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         7104                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1831975                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        25844                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           768                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        25920                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           745                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5848596                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5681557                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 36821                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           264886087                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                5850435                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5682032                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 37041                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           264886958                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              34140942                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             14477069                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              23450                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3913                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 29719                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           7120                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3233413                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3247375                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              6480788                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             207526427                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              30720305                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7380747                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              34143660                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14476609                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              23446                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3875                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 29998                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           7104                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3234550                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3248118                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6482668                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             207528127                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              30721496                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7385809                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         15967                       # number of nop insts executed
-system.cpu.iew.exec_refs                     43860812                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 44937004                       # Number of branches executed
-system.cpu.iew.exec_stores                   13140507                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.220356                       # Inst execution rate
-system.cpu.iew.wb_sent                      206744573                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     206409759                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 129475490                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 221697589                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         15912                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43861162                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 44936179                       # Number of branches executed
+system.cpu.iew.exec_stores                   13139666                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.220294                       # Inst execution rate
+system.cpu.iew.wb_sent                      206744895                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     206409852                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 129477271                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 221697359                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.213789                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.584018                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.213718                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.584027                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        69541306                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        69541697                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           5841613                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158471260                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.146267                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.646384                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           5843462                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158482976                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.146182                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.646662                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     73683520     46.50%     46.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     41279039     26.05%     72.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     22557642     14.23%     86.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9629639      6.08%     92.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3553008      2.24%     95.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2147976      1.36%     96.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1280790      0.81%     97.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       986719      0.62%     97.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3352927      2.12%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     73704941     46.51%     46.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     41274815     26.04%     72.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     22552900     14.23%     86.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9628649      6.08%     92.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3549516      2.24%     95.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2148015      1.36%     96.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1280291      0.81%     97.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       986897      0.62%     97.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3356952      2.12%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158471260                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            172317409                       # Number of instructions committed
-system.cpu.commit.committedOps              181650341                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    158482976                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
+system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       40540778                       # Number of memory references committed
 system.cpu.commit.loads                      27896144                       # Number of loads committed
 system.cpu.commit.membars                       22408                       # Number of memory barriers committed
-system.cpu.commit.branches                   40300311                       # Number of branches committed
+system.cpu.commit.branches                   40300312                       # Number of branches committed
 system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 143085667                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        138987812     76.51%     76.51% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        138987813     76.51%     76.51% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          908940      0.50%     77.01% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     77.01% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     77.01% # Class of committed instruction
@@ -654,186 +654,186 @@ system.cpu.commit.op_class_0::MemRead        27896144     15.36%     93.04% # Cl
 system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         181650341                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3352927                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    406304779                       # The number of ROB reads
-system.cpu.rob.rob_writes                   513839131                       # The number of ROB writes
-system.cpu.timesIdled                            3408                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          140895                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   172303021                       # Number of Instructions Simulated
-system.cpu.committedOps                     181635953                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.986947                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.986947                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.013225                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.013225                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218958782                       # number of integer regfile reads
-system.cpu.int_regfile_writes               114515411                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2904346                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2441525                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 709584302                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                229541480                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                59315386                       # number of misc regfile reads
+system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               3356952                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    406312862                       # The number of ROB reads
+system.cpu.rob.rob_writes                   513841850                       # The number of ROB writes
+system.cpu.timesIdled                            3415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          137386                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
+system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.987006                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.987006                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.013165                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.013165                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                218961575                       # number of integer regfile reads
+system.cpu.int_regfile_writes               114515726                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2904225                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2441500                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 709589041                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                229545726                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                59313943                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements             72889                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.417696                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            41115745                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs             73401                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            560.152382                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements             72899                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.418278                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            41116599                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs             73411                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            560.087712                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         506067250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.417696                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998863                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998863                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.418278                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998864                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998864                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          165                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          82529901                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         82529901                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28729389                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28729389                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12341441                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12341441                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          82531693                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         82531693                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28730266                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28730266                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12341417                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12341417                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          361                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           361                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22147                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22147                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22148                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22148                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41070830                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41070830                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41071191                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41071191                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89283                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89283                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        22846                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        22846                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data      41071683                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41071683                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41072044                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41072044                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89294                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89294                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22870                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22870                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          118                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          118                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          260                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          260                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       112129                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         112129                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       112245                       # number of overall misses
-system.cpu.dcache.overall_misses::total        112245                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    853218237                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    853218237                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    244809935                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    244809935                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data       112164                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         112164                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       112282                       # number of overall misses
+system.cpu.dcache.overall_misses::total        112282                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    853196487                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    853196487                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    241173427                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    241173427                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2319500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total      2319500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1098028172                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1098028172                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1098028172                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1098028172                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28818672                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28818672                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data   1094369914                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1094369914                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1094369914                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1094369914                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28819560                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28819560                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          477                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          477                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          479                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          479                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22408                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22408                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41182959                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41182959                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41183436                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41183436                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     41183847                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41183847                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41184326                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41184326                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003098                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003098                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001848                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001848                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.243187                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.243187                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011604                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011604                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001850                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001850                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.246347                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.246347                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011603                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011603                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.002723                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.002723                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002725                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002725                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9556.334767                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9556.334767                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10715.658540                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10715.658540                       # average WriteReq miss latency
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002726                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002726                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9554.913958                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9554.913958                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10545.405641                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10545.405641                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8921.153846                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8921.153846                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9792.544052                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9792.544052                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9782.423912                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9782.423912                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9756.873097                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9756.873097                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9746.619351                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9746.619351                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          167                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        10490                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         9765                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             844                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             848                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    12.428910                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    11.515330                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        64871                       # number of writebacks
-system.cpu.dcache.writebacks::total             64871                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24560                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        24560                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14281                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        14281                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        64878                       # number of writebacks
+system.cpu.dcache.writebacks::total             64878                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24567                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        24567                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14301                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        14301                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          260                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          260                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        38841                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        38841                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        38841                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        38841                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64723                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        64723                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8565                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         8565                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data        73288                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total        73288                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data        73401                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total        73401                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    526941010                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    526941010                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     81775757                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     81775757                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       905500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       905500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    608716767                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    608716767                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    609622267                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    609622267                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data        38868                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        38868                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        38868                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        38868                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64727                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        64727                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8569                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         8569                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          115                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          115                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data        73296                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total        73296                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data        73411                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total        73411                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    526755010                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    526755010                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     81248758                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     81248758                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       920500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       920500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    608003768                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    608003768                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    608924268                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    608924268                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002246                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002246                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000693                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000693                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.236897                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.236897                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.240084                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.240084                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001780                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001780                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001782                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001782                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8141.479999                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8141.479999                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9547.665733                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9547.665733                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8013.274336                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8013.274336                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8305.817692                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8305.817692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8305.367325                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8305.367325                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8138.103264                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8138.103264                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9481.708251                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9481.708251                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8004.347826                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8004.347826                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8295.183475                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8295.183475                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8294.727875                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8294.727875                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             54441                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.602621                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78893897                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             54953                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1435.661329                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       84271974250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.602621                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997271                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997271                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             54462                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.603252                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            78902001                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             54974                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1435.260323                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       84278847250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.603252                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997272                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997272                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
@@ -841,188 +841,188 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          272
 system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           48                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         157958145                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        157958145                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     78893897                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78893897                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78893897                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78893897                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78893897                       # number of overall hits
-system.cpu.icache.overall_hits::total        78893897                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        57699                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         57699                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        57699                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          57699                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        57699                       # number of overall misses
-system.cpu.icache.overall_misses::total         57699                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    607673936                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    607673936                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    607673936                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    607673936                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    607673936                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    607673936                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78951596                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78951596                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78951596                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78951596                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78951596                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78951596                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         157974458                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        157974458                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     78902001                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78902001                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78902001                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78902001                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78902001                       # number of overall hits
+system.cpu.icache.overall_hits::total        78902001                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        57741                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         57741                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        57741                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          57741                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        57741                       # number of overall misses
+system.cpu.icache.overall_misses::total         57741                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    606045932                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    606045932                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    606045932                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    606045932                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    606045932                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    606045932                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78959742                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78959742                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78959742                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78959742                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78959742                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78959742                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000731                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000731                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000731                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000731                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000731                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000731                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10531.793203                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10531.793203                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10531.793203                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10531.793203                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10531.793203                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10531.793203                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        55459                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          532                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2752                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    20.152253                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets   177.333333                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10495.937583                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10495.937583                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10495.937583                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10495.937583                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10495.937583                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10495.937583                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        55224                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2764                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.979740                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2746                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2746                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2746                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2746                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2746                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2746                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54953                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        54953                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        54953                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        54953                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        54953                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        54953                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    509320483                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    509320483                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    509320483                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    509320483                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    509320483                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    509320483                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2767                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2767                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2767                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2767                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2767                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2767                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54974                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        54974                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        54974                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        54974                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        54974                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        54974                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    508400239                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    508400239                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    508400239                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    508400239                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    508400239                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    508400239                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000696                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000696                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000696                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9268.292595                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9268.292595                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9268.292595                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9268.292595                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9268.292595                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9268.292595                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9248.012497                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9248.012497                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9248.012497                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  9248.012497                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9248.012497                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  9248.012497                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued         9289                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified         9289                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued         9320                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified         9320                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage         1375                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage         1320                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2667.127708                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             178431                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3576                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            49.896812                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2670.271397                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             178475                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3578                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            49.881219                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   701.951887                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1376.042782                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   417.094048                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   172.038991                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.042844                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.083987                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.025457                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.010500                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.162789                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          260                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3316                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           83                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          158                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks   701.931689                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1376.006014                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   417.075318                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   175.258376                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.042843                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.083985                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.025456                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.010697                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.162980                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          264                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3314                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           86                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          163                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          751                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          747                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2290                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015869                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.202393                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3103812                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3103812                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        52962                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        64250                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         117212                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        64871                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        64871                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         8396                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         8396                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        52962                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        72646                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          125608                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        52962                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        72646                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         125608                       # number of overall hits
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.016113                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.202271                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3104422                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3104422                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        52983                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        64262                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         117245                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        64878                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        64878                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         8397                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         8397                       # number of ReadExReq hits
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+system.cpu.l2cache.demand_hits::cpu.data        72659                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          125642                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.data        72659                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         125642                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         1991                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          515                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         2506                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          240                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          240                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          513                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2504                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          239                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          239                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         1991                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          755                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          2746                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          752                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          2743                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         1991                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          755                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         2746                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    137421241                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     37855250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    175276491                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     18932508                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     18932508                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    137421241                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     56787758                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    194208999                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    137421241                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     56787758                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    194208999                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        54953                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        64765                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       119718                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        64871                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        64871                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data          752                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         2743                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    136350743                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     37619250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    173969993                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     18370509                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     18370509                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    136350743                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     55989759                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data     55989759                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    192340502                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        54974                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        64775                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       119749                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        64878                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        64878                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         8636                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         8636                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        54953                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data        73401                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       128354                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        54953                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data        73401                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       128354                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.036231                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.007952                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.020933                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027791                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.027791                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.036231                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.010286                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.021394                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.036231                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.010286                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.021394                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69021.215972                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73505.339806                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69942.733839                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78885.450000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78885.450000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69021.215972                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75215.573510                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70724.325929                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69021.215972                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75215.573510                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70724.325929                       # average overall miss latency
+system.cpu.l2cache.demand_accesses::cpu.inst        54974                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data        73411                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       128385                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        54974                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data        73411                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       128385                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.036217                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.007920                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.020910                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027675                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.027675                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.036217                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.010244                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.021365                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.036217                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.010244                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.021365                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68483.547464                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73331.871345                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69476.834265                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76864.054393                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76864.054393                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68483.547464                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74454.466755                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70120.489245                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68483.547464                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74454.466755                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70120.489245                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1043,116 +1043,116 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst            6
 system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1985                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          507                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2492                       # number of ReadReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1808                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total         1808                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          238                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          238                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          505                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2490                       # number of ReadReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1805                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total         1805                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          237                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          237                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         1985                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          745                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         2730                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          742                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         2727                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         1985                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          745                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1808                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         4538                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    120193759                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     33127750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    153321509                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     68601184                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     68601184                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     16505250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     16505250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    120193759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     49633000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    169826759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    120193759                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     49633000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     68601184                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    238427943                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.036122                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.007828                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.020816                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          742                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1805                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         4532                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    119139257                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     32909250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    152048507                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     70744400                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     70744400                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     15940250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     15940250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    119139257                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     48849500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    167988757                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    119139257                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     48849500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     70744400                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    238733157                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.036108                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.007796                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.020793                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027559                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027559                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.036122                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.010150                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.021269                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.036122                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.010150                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027443                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027443                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.036108                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.010107                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.021241                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.036108                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.010107                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.035355                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.012091                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65340.729783                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61525.485152                       # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37943.132743                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69349.789916                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69349.789916                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.012091                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66621.476510                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62207.604029                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.012091                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66621.476510                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52540.313574                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.035300                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60019.776826                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65166.831683                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61063.657430                       # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39193.573407                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67258.438819                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67258.438819                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60019.776826                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65834.905660                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61602.037770                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60019.776826                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65834.905660                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52677.219109                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         119718                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        119718                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        64871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq         2155                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         119749                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        119749                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        64878                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq         2153                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         8636                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         8636                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       109906                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       211673                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            321579                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3516992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8849408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           12366400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                        2155                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       195380                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.011030                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.104442                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       109948                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       211700                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            321648                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3518336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8850496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           12368832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                        2153                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       195416                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.011018                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.104385                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3             193225     98.90%     98.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4               2155      1.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3             193263     98.90%     98.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4               2153      1.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         195380                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      161483500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         195416                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      161509500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      82836732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      82870477                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     110205232                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     110219231                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                3602                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3602                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               238                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              238                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       245760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  245760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq                3605                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3605                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               237                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              237                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7684                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7684                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       245888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  245888                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3840                       # Request fanout histogram
+system.membus.snoop_fanout::samples              3842                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3840    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3842    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3840                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4975502                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                3842                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             4969720                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20238053                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20244552                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------