diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-16 10:44:12 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-16 10:44:12 -0400 |
| commit | 10e64501206b72901c266855fde2909523b875e0 (patch) | |
| tree | df5db553cf78ff00467b4ca87614a5721439b2ec /tests/long/se | |
| parent | b10ff075b102b2a2e4abf5d22735b919a8fda1a9 (diff) | |
| download | gem5-10e64501206b72901c266855fde2909523b875e0.tar.xz | |
test: update stats
Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
Diffstat (limited to 'tests/long/se')
61 files changed, 1971 insertions, 1973 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 108881308..e070ad588 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 9be633e93..f7ab26f15 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:20:51 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 01:59:02 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 14bb680f9..5d8366912 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026877 # Nu sim_ticks 26877484000 # Number of ticks simulated final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190344 # Simulator instruction rate (inst/s) -host_op_rate 191711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56473959 # Simulator tick rate (ticks/s) -host_mem_usage 375760 # Number of bytes of host memory used -host_seconds 475.93 # Real time elapsed on the host +host_inst_rate 158705 # Simulator instruction rate (inst/s) +host_op_rate 159844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47086787 # Simulator tick rate (ticks/s) +host_mem_usage 380172 # Number of bytes of host memory used +host_seconds 570.81 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory @@ -333,8 +333,8 @@ system.cpu.rename.LSQFullEvents 4597767 # Nu system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536314240 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5726 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 499912232 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 925 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 5b842e86b..11900168b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 14639c3c6..0a86dbd97 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:21:35 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:42:09 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -18,12 +16,12 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 -info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 simplex iterations : 2663 +info: Increasing stack size by one page. flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 65501881000 because target called exit() +Exiting @ tick 65497052500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 9d42f660f..3b6f53bfa 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065502 # Number of seconds simulated -sim_ticks 65501881000 # Number of ticks simulated -final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065497 # Number of seconds simulated +sim_ticks 65497052500 # Number of ticks simulated +final_tick 65497052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73961 # Simulator instruction rate (inst/s) -host_op_rate 130234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30664297 # Simulator tick rate (ticks/s) -host_mem_usage 385548 # Number of bytes of host memory used -host_seconds 2136.10 # Real time elapsed on the host +host_inst_rate 99498 # Simulator instruction rate (inst/s) +host_op_rate 175200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41248682 # Simulator tick rate (ticks/s) +host_mem_usage 388584 # Number of bytes of host memory used +host_seconds 1587.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory -system.physmem.bytes_written::total 10432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30408 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 971209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28739572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29710780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 971209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 971209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 159263 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 159263 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 159263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30410 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 163 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 30410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 163 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 1946112 # Total number of bytes read from memory -system.physmem.bytesWritten 10432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q +system.physmem.bytes_read::cpu.inst 63296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882240 # Number of bytes read from this memory +system.physmem.bytes_read::total 1945536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9984 # Number of bytes written to this memory +system.physmem.bytes_written::total 9984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29410 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30399 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 966395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28737782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29704176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 966395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 966395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 152434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 152434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 152434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 966395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28737782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29856611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30400 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 156 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 30400 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 156 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 1945536 # Total number of bytes read from memory +system.physmem.bytesWritten 9984 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1945536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9984 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1924 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2025 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1939 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1932 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1818 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1820 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 13 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis @@ -78,23 +78,23 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65501859000 # Total gap between requests +system.physmem.totGap 65497035500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30410 # Categorize read packet sizes +system.physmem.readPktSize::6 30400 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 163 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see +system.physmem.writePktSize::6 156 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 365 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -125,8 +125,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see @@ -143,11 +143,11 @@ system.physmem.wrQLenPdf::14 7 # Wh system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,332 +157,331 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 552 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3503.884058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 832.064707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3839.690246 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 138 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 47 8.51% 33.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 28 5.07% 38.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 12 2.17% 40.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 14 2.54% 43.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11 1.99% 45.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8 1.45% 46.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 4 0.72% 47.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.63% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.27% 50.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.72% 51.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 1.27% 52.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 2 0.36% 52.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 2 0.36% 53.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.54% 53.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.18% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.18% 56.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.36% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.18% 56.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.18% 57.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.36% 57.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.36% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.18% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.18% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.18% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.18% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.18% 59.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.18% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.36% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.18% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 215 38.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 552 # Bytes accessed per row activation -system.physmem.totQLat 7596000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 583088500 # Sum of mem lat for all requests -system.physmem.totBusLat 151800000 # Total cycles spent in databus access -system.physmem.totBankLat 423692500 # Total cycles spent in bank access -system.physmem.avgQLat 250.20 # Average queueing delay per request -system.physmem.avgBankLat 13955.62 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3610.915888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 887.471357 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3852.235562 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 128 23.93% 23.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 47 8.79% 32.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 24 4.49% 37.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 2.24% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 11 2.06% 41.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11 2.06% 43.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.50% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 3 0.56% 45.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.68% 47.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.87% 49.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2 0.37% 49.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 7 1.31% 50.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1 0.19% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 3 0.56% 51.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.56% 52.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.19% 52.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 9 1.68% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.37% 54.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.19% 54.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.19% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.19% 54.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.37% 55.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.19% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.19% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.37% 56.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.19% 56.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.37% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.19% 56.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.19% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.19% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.37% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.19% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.19% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.19% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.19% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.19% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.37% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.19% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.37% 59.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.19% 59.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.19% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 215 40.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 535 # Bytes accessed per row activation +system.physmem.totQLat 5969250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 581474250 # Sum of mem lat for all requests +system.physmem.totBusLat 151785000 # Total cycles spent in databus access +system.physmem.totBankLat 423720000 # Total cycles spent in bank access +system.physmem.avgQLat 196.64 # Average queueing delay per request +system.physmem.avgBankLat 13957.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19205.81 # Average memory access latency -system.physmem.avgRdBW 29.71 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.71 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 19154.54 # Average memory access latency +system.physmem.avgRdBW 29.70 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 12.43 # Average write queue length over time -system.physmem.readRowHits 29868 # Number of row buffer hits during reads -system.physmem.writeRowHits 101 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.39 # Average write queue length over time +system.physmem.readRowHits 29864 # Number of row buffer hits during reads +system.physmem.writeRowHits 96 # Number of row buffer hits during writes system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.96 # Row buffer hit rate for writes -system.physmem.avgGap 2142474.05 # Average gap between requests -system.membus.throughput 29869066 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1406 # Transaction distribution -system.membus.trans_dist::ReadResp 1403 # Transaction distribution -system.membus.trans_dist::Writeback 163 # Transaction distribution -system.membus.trans_dist::ReadExReq 29004 # Transaction distribution -system.membus.trans_dist::ReadExResp 29004 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1956480 # Total data (bytes) +system.physmem.writeRowHitRate 61.54 # Row buffer hit rate for writes +system.physmem.avgGap 2143508.17 # Average gap between requests +system.membus.throughput 29855634 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1399 # Transaction distribution +system.membus.trans_dist::ReadResp 1397 # Transaction distribution +system.membus.trans_dist::Writeback 156 # Transaction distribution +system.membus.trans_dist::ReadExReq 29001 # Transaction distribution +system.membus.trans_dist::ReadExResp 29001 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60954 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1955456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1955456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1955456 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1955456 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35091000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 35006500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284259500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284183250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.branchPred.lookups 33859772 # Number of BP lookups -system.cpu.branchPred.condPredicted 33859772 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19298286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19204033 # Number of BTB hits +system.cpu.branchPred.lookups 33858224 # Number of BP lookups +system.cpu.branchPred.condPredicted 33858224 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774589 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19295548 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19203800 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.511599 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017180 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5379 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.524512 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5017950 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5443 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131003766 # number of cpu cycles simulated +system.cpu.numCycles 130994109 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26135908 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182273755 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33859772 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221213 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55461769 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5355546 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44756866 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26134025 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182258914 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33858224 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24221750 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55458228 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5352681 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44757241 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 354 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25575264 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 165870 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 130900361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.454854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25574362 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166199 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 130892614 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.454818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314961 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77915453 59.52% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1959993 1.50% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2942167 2.25% 63.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3834775 2.93% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7768215 5.93% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757692 3.63% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2664580 2.04% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316041 1.01% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27741445 21.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77910684 59.52% 59.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1961091 1.50% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2941416 2.25% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3833946 2.93% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7767539 5.93% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757616 3.63% 75.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2666164 2.04% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316720 1.01% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27737438 21.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 130900361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258464 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.391363 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36822089 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36980976 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43893831 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8658090 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4545375 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318858939 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4545375 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42309692 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9552635 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46756316 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27728938 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 315018359 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 180 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26669 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25876041 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 477 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 317189446 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836531493 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 836530400 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1093 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 130892614 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258471 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.391352 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36819659 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36980368 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43894473 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8655405 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4542709 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318839804 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4542709 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42306626 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9548363 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7363 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46754553 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27733000 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 314999780 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25879667 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 317173158 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836491506 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 515038229 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37976699 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 479 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 477 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62612991 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101555768 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34778786 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39638216 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5865755 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311479938 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1623 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300277679 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89964 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32707513 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46093052 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 130900361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.293941 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.699121 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37960411 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 483 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62657657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101560400 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34776362 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39636404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5873969 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311477073 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1619 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300261813 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90477 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32704303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46143152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1174 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 130892614 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.293955 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24175636 18.47% 18.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23209060 17.73% 36.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25458730 19.45% 55.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25817772 19.72% 75.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18910783 14.45% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8235477 6.29% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3954804 3.02% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 956290 0.73% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181809 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24143436 18.45% 18.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23235636 17.75% 36.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25474582 19.46% 55.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25828603 19.73% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18887958 14.43% 89.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8220714 6.28% 96.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3961121 3.03% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 955436 0.73% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 185128 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 130900361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 130892614 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31412 1.53% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1912178 93.02% 94.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111979 5.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31366 1.52% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1915737 93.06% 94.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111488 5.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169839925 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11359 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97303672 32.40% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33091082 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169828970 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11213 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97302750 32.41% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33087237 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300277679 # Type of FU issued -system.cpu.iq.rate 2.292130 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2055569 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006846 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733600907 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344221068 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298025850 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302301800 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54184658 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300261813 # Type of FU issued +system.cpu.iq.rate 2.292178 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2058591 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733564971 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344215080 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298003281 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 337 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 435 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 126 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302288959 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54190051 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10776383 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30894 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33570 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3339034 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10781015 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32177 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33336 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3336610 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3237 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8568 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3220 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4545375 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2618322 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 161863 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311481561 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197279 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101555768 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34778786 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73457 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33570 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427979 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821632 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298876380 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891177 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1401299 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4542709 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2622554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162089 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311478692 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 196017 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101560400 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34776362 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 469 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2626 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33336 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393441 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427689 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821130 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298856938 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96890588 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1404875 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129818452 # number of memory reference insts executed -system.cpu.iew.exec_branches 30820594 # Number of branches executed -system.cpu.iew.exec_stores 32927275 # Number of stores executed -system.cpu.iew.exec_rate 2.281433 # Inst execution rate -system.cpu.iew.wb_sent 298395371 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298025973 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218267458 # num instructions producing a value -system.cpu.iew.wb_consumers 296778027 # num instructions consuming a value +system.cpu.iew.exec_refs 129814899 # number of memory reference insts executed +system.cpu.iew.exec_branches 30818444 # Number of branches executed +system.cpu.iew.exec_stores 32924311 # Number of stores executed +system.cpu.iew.exec_rate 2.281453 # Inst execution rate +system.cpu.iew.wb_sent 298373185 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298003407 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218253384 # num instructions producing a value +system.cpu.iew.wb_consumers 296750864 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.274942 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735457 # average fanout of values written-back +system.cpu.iew.wb_rate 2.274937 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33301924 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33298978 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774937 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126354986 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.201674 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.972574 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774634 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126349905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.201762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.972659 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58072502 45.96% 45.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19158205 15.16% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11637077 9.21% 70.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9445238 7.48% 77.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1852713 1.47% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2072442 1.64% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1294957 1.02% 81.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 693229 0.55% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22128623 17.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58072656 45.96% 45.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19155409 15.16% 61.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11632100 9.21% 70.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9445412 7.48% 77.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1855076 1.47% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2067896 1.64% 80.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1301136 1.03% 81.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 691741 0.55% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22128479 17.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126354986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126349905 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -491,92 +490,94 @@ system.cpu.commit.loads 90779385 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 29309705 # Number of branches committed system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. +system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22128623 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22128479 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415720751 # The number of ROB reads -system.cpu.rob.rob_writes 627537958 # The number of ROB writes -system.cpu.timesIdled 13918 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 103405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415712868 # The number of ROB reads +system.cpu.rob.rob_writes 627529396 # The number of ROB writes +system.cpu.timesIdled 13705 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101495 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.829198 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829198 # CPI: Total CPI of All Threads -system.cpu.ipc 1.205985 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.205985 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 590807496 # number of integer regfile reads -system.cpu.int_regfile_writes 298603166 # number of integer regfile writes -system.cpu.fp_regfile_reads 109 # number of floating regfile reads -system.cpu.fp_regfile_writes 74 # number of floating regfile writes -system.cpu.misc_regfile_reads 191829835 # number of misc regfile reads +system.cpu.cpi 0.829137 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829137 # CPI: Total CPI of All Threads +system.cpu.ipc 1.206074 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.206074 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 483722109 # number of integer regfile reads +system.cpu.int_regfile_writes 234582139 # number of integer regfile writes +system.cpu.fp_regfile_reads 117 # number of floating regfile reads +system.cpu.fp_regfile_writes 75 # number of floating regfile writes +system.cpu.cc_regfile_reads 107053198 # number of cc regfile reads +system.cpu.cc_regfile_writes 64000024 # number of cc regfile writes +system.cpu.misc_regfile_reads 191821503 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4049183259 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Transaction distribution +system.cpu.toL2Bus.throughput 4049501312 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995296 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265164480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265229120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 82299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82299 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265166016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265230400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265230400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138743500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1707500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1699750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3122104250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 57 # number of replacements -system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 55 # number of replacements +system.cpu.icache.tags.tagsinuse 816.683247 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25573067 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1006 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25420.543738 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25573967 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25573967 # number of overall hits -system.cpu.icache.overall_hits::total 25573967 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses -system.cpu.icache.overall_misses::total 1297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86393250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86393250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86393250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86393250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86393250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86393250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25575264 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25575264 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25575264 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25575264 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25575264 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25575264 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 816.683247 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.398771 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.398771 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25573067 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25573067 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25573067 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25573067 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25573067 # number of overall hits +system.cpu.icache.overall_hits::total 25573067 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses +system.cpu.icache.overall_misses::total 1295 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85604250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85604250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85604250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85604250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85604250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85604250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25574362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25574362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25574362 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25574362 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25574362 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25574362 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66610.061681 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66610.061681 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66610.061681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66103.667954 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66103.667954 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66103.667954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66103.667954 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -585,120 +586,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 287 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 287 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 287 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 287 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 287 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1010 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1010 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1010 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68485500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68485500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68485500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68485500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68485500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68485500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 289 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 289 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 289 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 289 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1006 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1006 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1006 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1006 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1006 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1006 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67541250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67541250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67541250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67541250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67541250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67541250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67807.425743 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67807.425743 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67138.419483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67138.419483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 474 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 461 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014632 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014632 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54527.047523 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55347.560976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54767.512509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.365884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.365884 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072469 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 2072493 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.881910 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71371808 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076589 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.369732 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20650704250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.881910 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341699 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71377775 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71377775 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71377775 # number of overall hits -system.cpu.dcache.overall_hits::total 71377775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2626397 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2626397 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98053 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98053 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2724450 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2724450 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2724450 # number of overall misses -system.cpu.dcache.overall_misses::total 2724450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31390082250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31390082250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2686066747 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2686066747 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34076148997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34076148997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34076148997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34076148997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42662473 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42662473 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 40030061 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40030061 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341747 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71371808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71371808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71371808 # number of overall hits +system.cpu.dcache.overall_hits::total 71371808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2626396 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2626396 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98005 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98005 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2724401 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2724401 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2724401 # number of overall misses +system.cpu.dcache.overall_misses::total 2724401 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31387330250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31387330250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2685755248 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2685755248 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34073085498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34073085498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34073085498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34073085498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42656457 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42656457 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74102225 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74102225 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74102225 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74102225 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061562 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061562 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036766 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036766 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036766 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11951.765955 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11951.765955 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27394.029219 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27394.029219 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12507.533262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12507.533262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32680 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74096209 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74096209 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74096209 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74096209 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061571 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061571 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003117 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003117 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11950.722682 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11950.722682 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27404.267619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27404.267619 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12506.633751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12506.633751 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32988 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9460 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.476080 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks system.cpu.dcache.writebacks::total 2066630 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632021 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 632021 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15861 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15861 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647882 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647882 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647882 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647882 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994376 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994376 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82192 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82192 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076568 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076568 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076568 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076568 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397806497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397806497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392651497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24392651497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392651497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24392651497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046748 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046748 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631996 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631996 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15814 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15814 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647810 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647810 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647810 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647810 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994400 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994400 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82191 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82191 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076591 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076591 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076591 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076591 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994515250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994515250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397679498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397679498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392194748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24392194748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392194748 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24392194748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046755 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046755 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028023 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028023 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.434458 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.434458 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29173.234585 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29173.234585 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028026 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028026 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.136407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.136407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29172.044360 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29172.044360 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 670a5ba2d..98402c27f 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:52:30 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:43:36 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index fcf1f6acc..d28c1e1a8 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 992711 # Simulator instruction rate (inst/s) -host_op_rate 1748005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1061587108 # Simulator tick rate (ticks/s) -host_mem_usage 424044 # Number of bytes of host memory used -host_seconds 159.15 # Real time elapsed on the host +host_inst_rate 1229454 # Simulator instruction rate (inst/s) +host_op_rate 2164871 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1314755229 # Simulator tick rate (ticks/s) +host_mem_usage 378084 # Number of bytes of host memory used +host_seconds 128.50 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 8475189 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186175 # number of integer instructions +system.cpu.num_int_insts 278169482 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read -system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written system.cpu.num_mem_refs 122219137 # number of memory refs system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 2c70ca6cf..033910815 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:32:00 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:48:06 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 2b38a25ba..fa71cbd3c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 324809 # Simulator instruction rate (inst/s) -host_op_rate 571936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 752437231 # Simulator tick rate (ticks/s) -host_mem_usage 382748 # Number of bytes of host memory used -host_seconds 486.40 # Real time elapsed on the host +host_inst_rate 746941 # Simulator instruction rate (inst/s) +host_op_rate 1315244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1730329772 # Simulator tick rate (ticks/s) +host_mem_usage 386536 # Number of bytes of host memory used +host_seconds 211.51 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory @@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 8475189 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186175 # number of integer instructions +system.cpu.num_int_insts 278169482 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read -system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written system.cpu.num_mem_refs 122219137 # number of memory refs system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 7756821bd..01aecce27 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 27bb412f8..cb7300a3e 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 07:58:36 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:08:48 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d58d3f98b..76f42f35e 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202350 # Nu sim_ticks 202349747500 # Number of ticks simulated final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95439 # Simulator instruction rate (inst/s) -host_op_rate 107602 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38223736 # Simulator tick rate (ticks/s) -host_mem_usage 246676 # Number of bytes of host memory used -host_seconds 5293.82 # Real time elapsed on the host +host_inst_rate 125600 # Simulator instruction rate (inst/s) +host_op_rate 141606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50303215 # Simulator tick rate (ticks/s) +host_mem_usage 251352 # Number of bytes of host memory used +host_seconds 4022.61 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory @@ -416,8 +416,8 @@ system.cpu.rename.LSQFullEvents 8947899 # Nu system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500482489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3242011448 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 6ab0a9e51..60a82514d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 29b59675c..5d75453d9 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,28 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 02:08:50 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. -**************************************** +**********************************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +****** 58924 words stored in 3784810 bytes @@ -21,18 +34,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,11 +75,9 @@ info: Increasing stack size by one page. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love -info: Increasing stack size by one page. -info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 458275427000 because target called exit() +Exiting @ tick 458276279000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 7e5dfb93e..c15724aa4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458275 # Number of seconds simulated -sim_ticks 458275427000 # Number of ticks simulated -final_tick 458275427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458276 # Number of seconds simulated +sim_ticks 458276279000 # Number of ticks simulated +final_tick 458276279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66021 # Simulator instruction rate (inst/s) -host_op_rate 122081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36590577 # Simulator tick rate (ticks/s) -host_mem_usage 346580 # Number of bytes of host memory used -host_seconds 12524.41 # Real time elapsed on the host +host_inst_rate 81967 # Simulator instruction rate (inst/s) +host_op_rate 151565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45427941 # Simulator tick rate (ticks/s) +host_mem_usage 343960 # Number of bytes of host memory used +host_seconds 10087.98 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24473408 # Number of bytes read from this memory -system.physmem.bytes_read::total 24676160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18786624 # Number of bytes written to this memory -system.physmem.bytes_written::total 18786624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293541 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293541 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53403274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53845697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40994177 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40994177 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40994177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53403274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94839875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385565 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 293541 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 385565 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 293541 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 24676160 # Total number of bytes read from memory -system.physmem.bytesWritten 18786624 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24676160 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18786624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 130355 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24409 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23617 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23994 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18975 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16955 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17829 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475520 # Number of bytes read from this memory +system.physmem.bytes_read::total 24678208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18791744 # Number of bytes written to this memory +system.physmem.bytes_written::total 18791744 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382430 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385597 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293621 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293621 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53407783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53850066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41005273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41005273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41005273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53407783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94855339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385597 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 293621 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 385597 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 293621 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 24678208 # Total number of bytes read from memory +system.physmem.bytesWritten 18791744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24678208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18791744 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 129454 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24819 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23151 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22850 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23921 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18532 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18410 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18967 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18561 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18114 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17718 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17686 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17818 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry -system.physmem.totGap 458275318500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry +system.physmem.totGap 458276251500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385565 # Categorize read packet sizes +system.physmem.readPktSize::6 385597 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293541 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293621 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,346 +125,346 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 125751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.531089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.070662 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 668.026506 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 53960 42.91% 42.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23382 18.59% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10554 8.39% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6402 5.09% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 3989 3.17% 78.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2874 2.29% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2122 1.69% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1769 1.41% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1442 1.15% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1166 0.93% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1242 0.99% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1075 0.85% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 727 0.58% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 689 0.55% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 609 0.48% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 572 0.45% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 523 0.42% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 500 0.40% 90.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 598 0.48% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 763 0.61% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 633 0.50% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 692 0.55% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6202 4.93% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 529 0.42% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 343 0.27% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 283 0.23% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 212 0.17% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 156 0.12% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 148 0.12% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 111 0.09% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 101 0.08% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 82 0.07% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 91 0.07% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 56 0.04% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 46 0.04% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 44 0.03% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 29 0.02% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 32 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 22 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 18 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 15 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 25 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 22 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 13 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 18 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 10 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 6 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 12 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 10 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 13 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 9 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 10 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 9 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 5 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 10 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 7 0.01% 99.57% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 125846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.334329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.235120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 666.634247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 53836 42.78% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23576 18.73% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10431 8.29% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6405 5.09% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4091 3.25% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2950 2.34% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2205 1.75% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1721 1.37% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1423 1.13% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1129 0.90% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1178 0.94% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1088 0.86% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 719 0.57% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 691 0.55% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 593 0.47% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 590 0.47% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 543 0.43% 89.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 555 0.44% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 625 0.50% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 694 0.55% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 625 0.50% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 735 0.58% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6224 4.95% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 501 0.40% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 329 0.26% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 262 0.21% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 235 0.19% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 154 0.12% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 168 0.13% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 127 0.10% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 91 0.07% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 78 0.06% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 63 0.05% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 57 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 48 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.04% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 32 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.03% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 24 0.02% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 22 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 28 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 15 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 11 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 26 0.02% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 10 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 12 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 9 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 11 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 10 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 11 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 9 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 4 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 11 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 5 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 10 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 3 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 8 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 12 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 8 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 6 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 10 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 9 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 378 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 125751 # Bytes accessed per row activation -system.physmem.totQLat 3033779750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11207673500 # Sum of mem lat for all requests -system.physmem.totBusLat 1927035000 # Total cycles spent in databus access -system.physmem.totBankLat 6246858750 # Total cycles spent in bank access -system.physmem.avgQLat 7871.63 # Average queueing delay per request -system.physmem.avgBankLat 16208.47 # Average bank access latency per request +system.physmem.bytesPerActivate::8192-8193 376 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 125846 # Bytes accessed per row activation +system.physmem.totQLat 3013395500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11189631750 # Sum of mem lat for all requests +system.physmem.totBusLat 1927150000 # Total cycles spent in databus access +system.physmem.totBankLat 6249086250 # Total cycles spent in bank access +system.physmem.avgQLat 7818.27 # Average queueing delay per request +system.physmem.avgBankLat 16213.28 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29080.10 # Average memory access latency +system.physmem.avgMemAccLat 29031.55 # Average memory access latency system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 40.99 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.19 # Average write queue length over time -system.physmem.readRowHits 346237 # Number of row buffer hits during reads -system.physmem.writeRowHits 206945 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.50 # Row buffer hit rate for writes -system.physmem.avgGap 674821.48 # Average gap between requests -system.membus.throughput 94839875 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178718 # Transaction distribution -system.membus.trans_dist::ReadResp 178718 # Transaction distribution -system.membus.trans_dist::Writeback 293541 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130355 # Transaction distribution -system.membus.trans_dist::UpgradeResp 130355 # Transaction distribution -system.membus.trans_dist::ReadExReq 206847 # Transaction distribution -system.membus.trans_dist::ReadExResp 206847 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1325381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1325381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1325381 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43462784 # Total data (bytes) +system.physmem.avgWrQLen 10.13 # Average write queue length over time +system.physmem.readRowHits 346215 # Number of row buffer hits during reads +system.physmem.writeRowHits 206987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.49 # Row buffer hit rate for writes +system.physmem.avgGap 674711.58 # Average gap between requests +system.membus.throughput 94855339 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178753 # Transaction distribution +system.membus.trans_dist::ReadResp 178753 # Transaction distribution +system.membus.trans_dist::Writeback 293621 # Transaction distribution +system.membus.trans_dist::UpgradeReq 129454 # Transaction distribution +system.membus.trans_dist::UpgradeResp 129454 # Transaction distribution +system.membus.trans_dist::ReadExReq 206844 # Transaction distribution +system.membus.trans_dist::ReadExResp 206844 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1323723 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1323723 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1323723 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3388183000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3387419250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3900602651 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3898953053 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205585963 # Number of BP lookups -system.cpu.branchPred.condPredicted 205585963 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9896898 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117084329 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114697569 # Number of BTB hits +system.cpu.branchPred.lookups 205598458 # Number of BP lookups +system.cpu.branchPred.condPredicted 205598458 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9896380 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117174051 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114692881 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.961503 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25058112 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1791626 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.882492 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25059076 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1793638 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916710548 # number of cpu cycles simulated +system.cpu.numCycles 916711426 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167348410 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131642862 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205585963 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139755681 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352231951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71067415 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303674725 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248698 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162008096 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2545258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884470252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380434 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325121 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167358741 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131763090 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205598458 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139751957 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352259726 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71078928 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303625713 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47908 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254198 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162013852 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2539166 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884476430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325214 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536305374 60.64% 60.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23381398 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25249677 2.85% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27894624 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17755657 2.01% 71.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22913193 2.59% 73.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29422157 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26648623 3.01% 80.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174899549 19.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536284008 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23384253 2.64% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25253496 2.86% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27902300 3.15% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17749201 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22913352 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29416028 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26647385 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174926407 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884470252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224265 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.234460 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222591066 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258702766 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295279341 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46977961 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60919118 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071200226 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 884476430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224278 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222500802 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258763432 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295392395 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46889742 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60930059 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071354254 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60919118 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256021570 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114401726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17692 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306707585 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146402561 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035040457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18320 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24691093 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106444419 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 265 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2137898681 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150156292 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5150048563 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 107729 # Number of floating rename lookups +system.cpu.rename.SquashCycles 60930059 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255984410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114277740 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18348 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306680368 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146585505 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035184371 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 17660 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24877077 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106438010 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138008878 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150477195 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273486109 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 27867 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523857827 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1226 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1159 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 345797829 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495831912 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194432339 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195703509 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55003285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975319588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13057 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772061886 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 486216 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441442603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734769754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12505 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884470252 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003529 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883234 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523968024 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1260 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1188 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346256555 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495848123 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194451746 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195373810 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54752041 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975440933 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14060 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772196947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 491373 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441593338 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734714175 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13508 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884476430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268041211 30.31% 30.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151493171 17.13% 47.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137403926 15.54% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131820403 14.90% 77.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91692561 10.37% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55993839 6.33% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34399481 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11841951 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1783709 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267871954 30.29% 30.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151795933 17.16% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137193879 15.51% 62.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131984117 14.92% 77.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91584837 10.35% 88.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55972472 6.33% 94.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34407043 3.89% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11912621 1.35% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1753574 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884470252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884476430 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4921151 32.49% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7620621 50.31% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2606942 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4900873 32.33% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7664927 50.56% 82.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2594883 17.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2621205 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165737036 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353398 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880807 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2622931 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165806661 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 353241 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880883 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429244538 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170224897 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429278261 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170254965 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772061886 # Type of FU issued -system.cpu.iq.rate 1.933066 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15148714 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008549 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444213917 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2416999842 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744830269 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15037 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 32010 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3518 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784582309 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172513794 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772196947 # Type of FU issued +system.cpu.iq.rate 1.933211 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15160683 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008555 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444507102 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417272272 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744936391 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15278 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33048 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3640 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784727445 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7254 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172555642 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111729755 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 382662 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328443 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45273076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111746790 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 385650 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328822 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45291560 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15362 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 587 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15317 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60919118 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66781934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7163097 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975332645 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 792462 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495831912 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194433262 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3156 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4458880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328443 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5899350 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4421061 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10320411 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752917873 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424115674 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19144013 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60930059 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66792766 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7181188 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975454993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 789344 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495848947 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194451746 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4469390 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83563 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328822 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5897715 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4420728 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10318443 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753033326 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424140898 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19163621 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590898440 # number of memory reference insts executed -system.cpu.iew.exec_branches 167466606 # Number of branches executed -system.cpu.iew.exec_stores 166782766 # Number of stores executed -system.cpu.iew.exec_rate 1.912183 # Inst execution rate -system.cpu.iew.wb_sent 1749674904 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744833787 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325104556 # num instructions producing a value -system.cpu.iew.wb_consumers 1945968985 # num instructions consuming a value +system.cpu.iew.exec_refs 590949993 # number of memory reference insts executed +system.cpu.iew.exec_branches 167484534 # Number of branches executed +system.cpu.iew.exec_stores 166809095 # Number of stores executed +system.cpu.iew.exec_rate 1.912307 # Inst execution rate +system.cpu.iew.wb_sent 1749784390 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744940031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325078811 # num instructions producing a value +system.cpu.iew.wb_consumers 1946006295 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903364 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680948 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903478 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680922 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446372129 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446495753 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9924639 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823551134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856580 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.437034 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9924967 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823546371 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436968 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331597809 40.26% 40.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193248476 23.47% 63.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63098135 7.66% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92588887 11.24% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24967401 3.03% 85.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27517381 3.34% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9278594 1.13% 90.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11386387 1.38% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69868064 8.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331540397 40.26% 40.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193316161 23.47% 63.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63109500 7.66% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92579702 11.24% 82.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24975285 3.03% 85.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27432624 3.33% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9320772 1.13% 90.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11449898 1.39% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69822032 8.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823551134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823546371 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,228 +577,230 @@ system.cpu.commit.loads 384102157 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. +system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69868064 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69822032 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729043900 # The number of ROB reads -system.cpu.rob.rob_writes 4011801822 # The number of ROB writes -system.cpu.timesIdled 3353209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32240296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2729208793 # The number of ROB reads +system.cpu.rob.rob_writes 4012058416 # The number of ROB writes +system.cpu.timesIdled 3349890 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32234996 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108642 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108642 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313398089 # number of integer regfile reads -system.cpu.int_regfile_writes 1825851160 # number of integer regfile writes -system.cpu.fp_regfile_reads 3505 # number of floating regfile reads -system.cpu.fp_regfile_writes 24 # number of floating regfile writes -system.cpu.misc_regfile_reads 964629229 # number of misc regfile reads +system.cpu.cpi 1.108643 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108643 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902004 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902004 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716444328 # number of integer regfile reads +system.cpu.int_regfile_writes 1420478428 # number of integer regfile writes +system.cpu.fp_regfile_reads 3628 # number of floating regfile reads +system.cpu.fp_regfile_writes 22 # number of floating regfile writes +system.cpu.cc_regfile_reads 597234249 # number of cc regfile reads +system.cpu.cc_regfile_writes 405441134 # number of cc regfile writes +system.cpu.misc_regfile_reads 964696527 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698744583 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1900899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1900898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 131758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 131758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771773 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 145540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7662191 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311340864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311778752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311778752 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8438720 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4901666269 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698612009 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1899997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1899996 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 130874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 130874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771776 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 144643 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7660372 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7805015 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311337920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311775616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311775616 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8381696 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4900939314 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 208719992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 207374491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3959172045 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3958743651 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5320 # number of replacements -system.cpu.icache.tags.tagsinuse 1038.062732 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161865564 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23448.582355 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5318 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.794557 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161872030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6894 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23480.131999 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1038.062732 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506867 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506867 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161867461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161867461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161867461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161867461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161867461 # number of overall hits -system.cpu.icache.overall_hits::total 161867461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 140635 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 140635 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 140635 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 140635 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 140635 # number of overall misses -system.cpu.icache.overall_misses::total 140635 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 923937485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 923937485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 923937485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 923937485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 923937485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 923937485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162008096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162008096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162008096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162008096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162008096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162008096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000868 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000868 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000868 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000868 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000868 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000868 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6569.754933 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6569.754933 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6569.754933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6569.754933 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 708 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.794557 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506247 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161874097 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161874097 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161874097 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161874097 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161874097 # number of overall hits +system.cpu.icache.overall_hits::total 161874097 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 139755 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 139755 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 139755 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 139755 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 139755 # number of overall misses +system.cpu.icache.overall_misses::total 139755 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 916174482 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 916174482 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 916174482 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 916174482 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 916174482 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 916174482 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162013852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162013852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162013852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162013852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162013852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162013852 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000863 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000863 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000863 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000863 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000863 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000863 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6555.575700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6555.575700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6555.575700 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71840.748843 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -807,174 +809,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293541 # number of writebacks -system.cpu.l2cache.writebacks::total 293541 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989170 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989170 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64986.509940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.747656 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62524.196929 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.546616 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.546616 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56190.838851 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56190.838851 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293621 # number of writebacks +system.cpu.l2cache.writebacks::total 293621 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3168 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175586 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178754 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 129428 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 129428 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206870 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206870 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385624 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205953000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10947318958 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11153271958 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1297954472 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1297954472 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11628367526 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11628367526 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205953000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22575686484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22781639484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205953000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22575686484 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22781639484 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099641 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101046 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988951 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988951 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268044 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268044 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151772 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463158 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529878 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.353781 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396093197 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2533974 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.313047 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2529873 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.353795 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 396071280 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2533969 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.304706 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353781 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353795 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247361230 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247361230 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250205018 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250205018 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399385049 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399385049 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399385049 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399385049 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006170 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006170 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20060.731330 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20060.731330 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28079.579043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28079.579043 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22010.937385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22010.937385 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7195 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399365220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399365220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399365220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399365220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011460 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006164 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009482 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009482 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009482 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009482 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.853782 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.853782 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28085.185333 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28085.185333 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22003.838445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22003.838445 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7384 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 685 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 704 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.503650 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.488636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330727 # number of writebacks -system.cpu.dcache.writebacks::total 2330727 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1101143 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1101143 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16988 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16988 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118131 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118131 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118131 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118131 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762474 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762474 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 903258 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 903258 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2665732 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2665732 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2665732 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2665732 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30885946501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30885946501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23721964454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23721964454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54607910955 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54607910955 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54607910955 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54607910955 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330686 # number of writebacks +system.cpu.dcache.writebacks::total 2330686 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1104851 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1104851 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1121870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1121870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1121870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1121870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 902384 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 902384 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2664842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2664842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2664842 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2664842 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30865724250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30865724250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23705880099 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23705880099 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54571604349 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54571604349 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54571604349 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54571604349 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006056 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006056 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006675 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006675 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17524.199790 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17524.199790 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26262.667426 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26262.667426 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006050 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006050 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006673 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17512.884988 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17512.884988 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26270.279725 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26270.279725 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 7a734044e..abce0a0d4 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:21:35 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:44:23 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 0326dde96..87dac48c4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1006678 # Simulator instruction rate (inst/s) -host_op_rate 1861461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1077718973 # Simulator tick rate (ticks/s) -host_mem_usage 296180 # Number of bytes of host memory used -host_seconds 821.39 # Real time elapsed on the host +host_inst_rate 1293065 # Simulator instruction rate (inst/s) +host_op_rate 2391022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1384315331 # Simulator tick rate (ticks/s) +host_mem_usage 251216 # Number of bytes of host memory used +host_seconds 639.47 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317562 # number of integer instructions +system.cpu.num_int_insts 1526605510 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written system.cpu.num_mem_refs 533262343 # number of memory refs system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 5ef733649..59b399b0b 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:48:16 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:41:23 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 7c10a36f9..43f2a7587 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872849000 # Number of ticks simulated final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 418246 # Simulator instruction rate (inst/s) -host_op_rate 773383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 833516309 # Simulator tick rate (ticks/s) -host_mem_usage 254900 # Number of bytes of host memory used -host_seconds 1977.01 # Real time elapsed on the host +host_inst_rate 788676 # Simulator instruction rate (inst/s) +host_op_rate 1458350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1571742015 # Simulator tick rate (ticks/s) +host_mem_usage 258676 # Number of bytes of host memory used +host_seconds 1048.44 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory @@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317562 # number of integer instructions +system.cpu.num_int_insts 1526605510 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written system.cpu.num_mem_refs 533262343 # number of memory refs system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index dfa123161..14dada76e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index dc6d59bdf..58c019f98 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index a56a193ad..e492ac5d0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077522 # Nu sim_ticks 77521581000 # Number of ticks simulated final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226587 # Simulator instruction rate (inst/s) -host_op_rate 226587 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46769350 # Simulator tick rate (ticks/s) -host_mem_usage 233048 # Number of bytes of host memory used -host_seconds 1657.53 # Real time elapsed on the host +host_inst_rate 201802 # Simulator instruction rate (inst/s) +host_op_rate 201802 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41653613 # Simulator tick rate (ticks/s) +host_mem_usage 236024 # Number of bytes of host memory used +host_seconds 1861.10 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory @@ -350,8 +350,8 @@ system.cpu.rename.IQFullEvents 25268 # Nu system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306415899 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 273002223 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 413955402 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165462719 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index c6c5b71d8..dd0636ebe 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index d9d67c53c..d3e872fc3 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:27:24 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:05:47 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index cfe46b65a..8bc1d638d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068375 # Nu sim_ticks 68375005500 # Number of ticks simulated final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121198 # Simulator instruction rate (inst/s) -host_op_rate 154946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30350947 # Simulator tick rate (ticks/s) -host_mem_usage 251080 # Number of bytes of host memory used -host_seconds 2252.81 # Real time elapsed on the host +host_inst_rate 143200 # Simulator instruction rate (inst/s) +host_op_rate 183074 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35860683 # Simulator tick rate (ticks/s) +host_mem_usage 256516 # Number of bytes of host memory used +host_seconds 1906.68 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory @@ -362,8 +362,8 @@ system.cpu.rename.LSQFullEvents 10191603 # Nu system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1257645546 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072712885 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index cb1d4f78d..507dc65a9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 6fa75b847..091ca3b5c 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 15 2013 18:56:50 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 669d3dfc7..580dd6a6a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.631883 # Nu sim_ticks 631883288500 # Number of ticks simulated final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177291 # Simulator instruction rate (inst/s) -host_op_rate 177291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61450789 # Simulator tick rate (ticks/s) -host_mem_usage 236780 # Number of bytes of host memory used -host_seconds 10282.75 # Real time elapsed on the host +host_inst_rate 151695 # Simulator instruction rate (inst/s) +host_op_rate 151695 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52578725 # Simulator tick rate (ticks/s) +host_mem_usage 240040 # Number of bytes of host memory used +host_seconds 12017.85 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory @@ -370,8 +370,8 @@ system.cpu.rename.IQFullEvents 15191 # Nu system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3458491340 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120702169 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3493818421 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85375087 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index f5cd82b95..be78ce1bf 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 6bce28421..3ba2de45d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:57:23 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:40:46 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 5f69a496c..d3db51b2e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.640648 # Nu sim_ticks 640648369500 # Number of ticks simulated final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107808 # Simulator instruction rate (inst/s) -host_op_rate 146820 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49890421 # Simulator tick rate (ticks/s) -host_mem_usage 251704 # Number of bytes of host memory used -host_seconds 12841.11 # Real time elapsed on the host +host_inst_rate 92518 # Simulator instruction rate (inst/s) +host_op_rate 125998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42814979 # Simulator tick rate (ticks/s) +host_mem_usage 256100 # Number of bytes of host memory used +host_seconds 14963.18 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory @@ -363,8 +363,8 @@ system.cpu.rename.LSQFullEvents 52259250 # Nu system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 12321480350 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90240197 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 7b8dd0790..684c8c0e1 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 0840178d9..d12ffcc4f 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:57:43 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 5b9e2998f..f889e2dcc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.024977 # Nu sim_ticks 24977022500 # Number of ticks simulated final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124025 # Simulator instruction rate (inst/s) -host_op_rate 124025 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38920856 # Simulator tick rate (ticks/s) -host_mem_usage 235900 # Number of bytes of host memory used -host_seconds 641.74 # Real time elapsed on the host +host_inst_rate 179872 # Simulator instruction rate (inst/s) +host_op_rate 179872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56446381 # Simulator tick rate (ticks/s) +host_mem_usage 238148 # Number of bytes of host memory used +host_seconds 442.49 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory @@ -417,8 +417,8 @@ system.cpu.rename.IQFullEvents 2492 # Nu system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122850608 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 451670 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 122982558 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319719 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 19517f85f..a8a1f643c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index b38f95469..946783e23 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:04:25 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:08:44 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 06aaaa021..9aa909b09 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026765 # Nu sim_ticks 26765004500 # Number of ticks simulated final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102307 # Simulator instruction rate (inst/s) -host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38617115 # Simulator tick rate (ticks/s) -host_mem_usage 251228 # Number of bytes of host memory used -host_seconds 693.09 # Real time elapsed on the host +host_inst_rate 122306 # Simulator instruction rate (inst/s) +host_op_rate 173568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46166163 # Simulator tick rate (ticks/s) +host_mem_usage 255896 # Number of bytes of host memory used +host_seconds 579.75 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory @@ -432,8 +432,8 @@ system.cpu.rename.LSQFullEvents 4627273 # Nu system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 530166885 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7695 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 476867094 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3452 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 5c873ae8a..898bd1404 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index a9e5ff044..3d7fe8a25 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:05:25 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 15 2013 19:07:40 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 82bf88993..d01882912 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.694171 # Nu sim_ticks 694171131000 # Number of ticks simulated final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178600 # Simulator instruction rate (inst/s) -host_op_rate 178600 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71414604 # Simulator tick rate (ticks/s) -host_mem_usage 227828 # Number of bytes of host memory used -host_seconds 9720.30 # Real time elapsed on the host +host_inst_rate 145628 # Simulator instruction rate (inst/s) +host_op_rate 145628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58230614 # Simulator tick rate (ticks/s) +host_mem_usage 230068 # Number of bytes of host memory used +host_seconds 11921.07 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory @@ -424,8 +424,8 @@ system.cpu.rename.IQFullEvents 1826446 # Nu system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899178783 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1242537 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3900278198 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 168 # count of serializing insts renamed diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 67c7195c6..30ce01df4 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 4c68e7cbb..7f1aa9216 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:11:07 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:37:44 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index f9e4efd28..3c2739180 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.541686 # Nu sim_ticks 541686426500 # Number of ticks simulated final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146656 # Simulator instruction rate (inst/s) -host_op_rate 163606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51433162 # Simulator tick rate (ticks/s) -host_mem_usage 242412 # Number of bytes of host memory used -host_seconds 10531.85 # Real time elapsed on the host +host_inst_rate 133850 # Simulator instruction rate (inst/s) +host_op_rate 149320 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46941984 # Simulator tick rate (ticks/s) +host_mem_usage 248124 # Number of bytes of host memory used +host_seconds 11539.49 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory @@ -433,8 +433,8 @@ system.cpu.rename.LSQFullEvents 60088597 # Nu system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10669716841 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2754 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 9782199775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 333 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 862 # count of serializing insts renamed diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 09e2cbd6f..5a2f2668d 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 07:00:18 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:38:48 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 09bbb2360..256e15dc9 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114602 # Simulator instruction rate (inst/s) -host_op_rate 1736651 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1054547884 # Simulator tick rate (ticks/s) -host_mem_usage 286860 # Number of bytes of host memory used -host_seconds 2698.79 # Real time elapsed on the host +host_inst_rate 1357896 # Simulator instruction rate (inst/s) +host_op_rate 2115724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1284732870 # Simulator tick rate (ticks/s) +host_mem_usage 240864 # Number of bytes of host memory used +host_seconds 2215.25 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 33534539 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862527 # number of integer instructions +system.cpu.num_int_insts 4684368009 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written +system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read +system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written system.cpu.num_mem_refs 1677713084 # number of memory refs system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 842f4ca6e..2a7659f1c 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:22:01 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:55:52 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 776ec92d3..f740c02c8 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 645050 # Simulator instruction rate (inst/s) -host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1261455450 # Simulator tick rate (ticks/s) -host_mem_usage 245540 # Number of bytes of host memory used -host_seconds 4663.33 # Real time elapsed on the host +host_inst_rate 876676 # Simulator instruction rate (inst/s) +host_op_rate 1365940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1714420225 # Simulator tick rate (ticks/s) +host_mem_usage 249312 # Number of bytes of host memory used +host_seconds 3431.24 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 33534539 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862527 # number of integer instructions +system.cpu.num_int_insts 4684368009 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written +system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read +system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written system.cpu.num_mem_refs 1677713084 # number of memory refs system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 8c9cfc594..b1f130dee 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index f8802d4f7..2fe61da2d 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:24:35 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index b7d057d9f..758c8228e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023492 # Nu sim_ticks 23492267500 # Number of ticks simulated final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120531 # Simulator instruction rate (inst/s) -host_op_rate 120531 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33636905 # Simulator tick rate (ticks/s) -host_mem_usage 231740 # Number of bytes of host memory used -host_seconds 698.41 # Real time elapsed on the host +host_inst_rate 158745 # Simulator instruction rate (inst/s) +host_op_rate 158745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44301493 # Simulator tick rate (ticks/s) +host_mem_usage 233720 # Number of bytes of host memory used +host_seconds 530.28 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory @@ -346,8 +346,8 @@ system.cpu.rename.IQFullEvents 398899 # Nu system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147895466 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9699627 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 150534218 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7060874 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 733 # count of serializing insts renamed diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 271729e48..d981a43f0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 000af632b..5ce7704c2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:14:29 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:15:41 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index cd02e0594..a815317b1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074201 # Nu sim_ticks 74201024500 # Number of ticks simulated final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88798 # Simulator instruction rate (inst/s) -host_op_rate 97225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38240010 # Simulator tick rate (ticks/s) -host_mem_usage 245976 # Number of bytes of host memory used -host_seconds 1940.40 # Real time elapsed on the host +host_inst_rate 115322 # Simulator instruction rate (inst/s) +host_op_rate 126267 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49662501 # Simulator tick rate (ticks/s) +host_mem_usage 251448 # Number of bytes of host memory used +host_seconds 1494.11 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory @@ -358,8 +358,8 @@ system.cpu.rename.LSQFullEvents 3662384 # Nu system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1564582781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17300681 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 078b2c3e8..5e4a8f947 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index da55dd7a8..607420641 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:39:37 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index cd707d2d7..06f12379e 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.144337 # Nu sim_ticks 144337151000 # Number of ticks simulated final_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53269 # Simulator instruction rate (inst/s) -host_op_rate 89284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58216660 # Simulator tick rate (ticks/s) -host_mem_usage 281036 # Number of bytes of host memory used -host_seconds 2479.31 # Real time elapsed on the host +host_inst_rate 71990 # Simulator instruction rate (inst/s) +host_op_rate 120663 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78676444 # Simulator tick rate (ticks/s) +host_mem_usage 280564 # Number of bytes of host memory used +host_seconds 1834.57 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory @@ -215,14 +215,14 @@ system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% # system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation -system.physmem.totQLat 12663500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 119173500 # Sum of mem lat for all requests +system.physmem.totQLat 12694000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests system.physmem.totBusLat 26815000 # Total cycles spent in databus access system.physmem.totBankLat 79695000 # Total cycles spent in bank access -system.physmem.avgQLat 2361.27 # Average queueing delay per request +system.physmem.avgQLat 2366.96 # Average queueing delay per request system.physmem.avgBankLat 14860.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22221.42 # Average memory access latency +system.physmem.avgMemAccLat 22227.11 # Average memory access latency system.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s @@ -251,110 +251,109 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040 system.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 343040 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6992500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50918345 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18643049 # Number of BP lookups -system.cpu.branchPred.condPredicted 18643049 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18643050 # Number of BP lookups +system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11410311 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10785937 # Number of BTB hits +system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.527984 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 288958648 # number of cpu cycles simulated +system.cpu.numCycles 288958646 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206693383 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18643049 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12105441 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54202283 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15520862 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 177854698 # Number of cycles fetch has spent blocked +system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22344440 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223501 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269290807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757533 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216527174 80.41% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2635919 0.98% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31978830 11.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269290807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle system.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36876726 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 166835214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41579224 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10227847 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13771796 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 335978319 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13771796 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44930870 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116571073 # Number of cycles rename is blocking +system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 42705730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51278615 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329616563 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10879 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26000887 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22678374 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 382329747 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917574423 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 909394709 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8179714 # Number of floating rename lookups +system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122900297 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2069 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104883276 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84491863 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58238424 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322680217 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260554825 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118516 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100936987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 209936629 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269290807 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.967559 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143216984 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55392011 20.57% 73.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34136175 12.68% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19056796 7.08% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10890988 4.04% 97.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4174840 1.55% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1812715 0.67% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476750 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269290807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129590 4.77% 4.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available @@ -388,8 +387,8 @@ system.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162062843 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788599 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued @@ -417,25 +416,25 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65458478 25.12% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260554825 # Type of FU issued +system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued system.cpu.iq.rate 0.901703 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2717985 # FU busy when requested +system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788349726 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420314001 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255192171 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259602149 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18922789 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27842276 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed @@ -444,57 +443,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13771796 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85093935 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5458597 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322684485 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84491863 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2689496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258780587 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64687693 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1774238 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87035311 # number of memory reference insts executed +system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed system.cpu.iew.exec_branches 14266808 # Number of branches executed system.cpu.iew.exec_stores 22347618 # Number of stores executed system.cpu.iew.exec_rate 0.895563 # Inst execution rate -system.cpu.iew.wb_sent 258140928 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257541852 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206006710 # num instructions producing a value -system.cpu.iew.wb_consumers 369206768 # num instructions consuming a value +system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206006775 # num instructions producing a value +system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101393272 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255519011 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.866328 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.656610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156315570 61.18% 61.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12048530 4.72% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4172669 1.63% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048603 0.41% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6974170 2.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255519011 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -503,14 +502,14 @@ system.cpu.commit.loads 56649587 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 12326938 # Number of branches committed system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. -system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. +system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6974170 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571301497 # The number of ROB reads -system.cpu.rob.rob_writes 659310607 # The number of ROB writes -system.cpu.timesIdled 5931768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19667841 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571301422 # The number of ROB reads +system.cpu.rob.rob_writes 659310799 # The number of ROB writes +system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated @@ -518,11 +517,13 @@ system.cpu.cpi 2.187901 # CP system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554180321 # number of integer regfile reads -system.cpu.int_regfile_writes 293821719 # number of integer regfile writes +system.cpu.int_regfile_reads 451358394 # number of integer regfile reads +system.cpu.int_regfile_writes 233998694 # number of integer regfile writes system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes -system.cpu.misc_regfile_reads 133360565 # number of misc regfile reads +system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads +system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes +system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution @@ -547,50 +548,50 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 4647 # number of replacements -system.cpu.icache.tags.tagsinuse 1626.526470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22335617 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3378.042498 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526470 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22335617 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22335617 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22335617 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22335617 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22335617 # number of overall hits -system.cpu.icache.overall_hits::total 22335617 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits +system.cpu.icache.overall_hits::total 22335618 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses system.cpu.icache.overall_misses::total 8823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 351986000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 351986000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 351986000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 351986000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 351986000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 351986000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22344440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22344440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22344440 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22344440 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22344440 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22344440 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39894.140315 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39894.140315 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39894.140315 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39894.140315 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked @@ -611,34 +612,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6769 system.cpu.icache.demand_mshr_misses::total 6769 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6769 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6769 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262790750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 262790750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262790750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 262790750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262790750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 262790750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38822.684296 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38822.684296 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2554.250999 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2554.251018 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3246 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3834 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.846635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1.761986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158867 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330146 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158882 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330149 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068364 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.009532 # Average percentage of cache occupancy @@ -671,17 +672,17 @@ system.cpu.l2cache.demand_misses::total 5364 # nu system.cpu.l2cache.overall_misses::cpu.inst 3407 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1957 # number of overall misses system.cpu.l2cache.overall_misses::total 5364 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223798500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31028500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 254827000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223827000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31029500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 254856500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96683500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 96683500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 223798500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 127712000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 351510500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 223798500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 127712000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 351510500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 223827000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 127713000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 351540000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 223827000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 127713000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 351540000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6613 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 464 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7077 # number of ReadReq accesses(hits+misses) @@ -710,17 +711,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.622780 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.515197 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.978500 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.622780 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65687.848547 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72496.495327 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66447.718383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65696.213678 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72498.831776 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66455.410691 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63233.158927 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63233.158927 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65531.413125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65531.413125 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65536.912752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65536.912752 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,19 +743,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5364 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3407 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1957 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5364 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180903000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25684500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206587500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180933000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25685000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206618000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1550155 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1550155 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77075500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77075500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180903000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 283663000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180903000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 283663000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180933000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 283693500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180933000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 283693500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922414 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.541896 # mshr miss rate for ReadReq accesses @@ -768,37 +769,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.622780 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.622780 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53097.446434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60010.514019 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53868.970013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53106.251834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60011.682243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53876.923077 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50409.090909 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50409.090909 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 54 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.071362 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66125332 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33112.334502 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071362 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.349383 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45611086 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45611086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66125124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66125124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66125124 # number of overall hits -system.cpu.dcache.overall_hits::total 66125124 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits +system.cpu.dcache.overall_hits::total 66125123 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 915 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 915 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses @@ -807,22 +808,22 @@ system.cpu.dcache.demand_misses::cpu.data 2608 # n system.cpu.dcache.demand_misses::total 2608 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses system.cpu.dcache.overall_misses::total 2608 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55173302 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55173302 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106078655 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106078655 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 161251957 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161251957 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161251957 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 161251957 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45612001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45612001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55175302 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55175302 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 106081155 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 106081155 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 161256457 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66127732 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66127732 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66127732 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66127732 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses @@ -831,14 +832,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60298.690710 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60298.690710 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62657.209096 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62657.209096 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61829.738113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61829.738113 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -865,14 +866,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2156 system.cpu.dcache.demand_mshr_misses::total 2156 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2156 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31923750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31923750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101848595 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101848595 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133772345 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133772345 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133772345 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133772345 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses @@ -881,14 +882,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68653.225806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68653.225806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60229.801892 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60229.801892 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 8d9f2b3f2..61953e3fc 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:46:06 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 2bac376f2..30630542a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 399836 # Simulator instruction rate (inst/s) -host_op_rate 670162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 397783827 # Simulator tick rate (ticks/s) -host_mem_usage 267400 # Number of bytes of host memory used -host_seconds 330.31 # Real time elapsed on the host +host_inst_rate 1210449 # Simulator instruction rate (inst/s) +host_op_rate 2028822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1204235272 # Simulator tick rate (ticks/s) +host_mem_usage 265804 # Number of bytes of host memory used +host_seconds 109.11 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 1595632 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339554 # number of integer instructions +system.cpu.num_int_insts 219019986 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616959402 # number of times the integer registers were read -system.cpu.num_int_register_writes 257598047 # number of times the integer registers were written +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written system.cpu.num_mem_refs 77165304 # number of memory refs system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 04fae0566..b436e7f9e 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:51:48 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 3f7324a80..9cfd1bb27 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290889 # Simulator instruction rate (inst/s) -host_op_rate 487557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 552730735 # Simulator tick rate (ticks/s) -host_mem_usage 274892 # Number of bytes of host memory used -host_seconds 454.03 # Real time elapsed on the host +host_inst_rate 789102 # Simulator instruction rate (inst/s) +host_op_rate 1322606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1499404446 # Simulator tick rate (ticks/s) +host_mem_usage 274284 # Number of bytes of host memory used +host_seconds 167.37 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -50,16 +50,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 1595632 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339554 # number of integer instructions +system.cpu.num_int_insts 219019986 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616959402 # number of times the integer registers were read -system.cpu.num_int_register_writes 257598047 # number of times the integer registers were written +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written system.cpu.num_mem_refs 77165304 # number of memory refs system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions |