diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se')
39 files changed, 19688 insertions, 19119 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index df256055e..1f83c039b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061296 # Number of seconds simulated -sim_ticks 61295518500 # Number of ticks simulated -final_tick 61295518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061280 # Number of seconds simulated +sim_ticks 61279840500 # Number of ticks simulated +final_tick 61279840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265745 # Simulator instruction rate (inst/s) -host_op_rate 267069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 179784475 # Simulator tick rate (ticks/s) -host_mem_usage 446692 # Number of bytes of host memory used -host_seconds 340.94 # Real time elapsed on the host +host_inst_rate 263178 # Simulator instruction rate (inst/s) +host_op_rate 264489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 178002192 # Simulator tick rate (ticks/s) +host_mem_usage 447788 # Number of bytes of host memory used +host_seconds 344.26 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15453006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16261156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15453006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16261156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15456959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16265316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15456959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16265316 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61295424000 # Total gap between requests +system.physmem.totGap 61279747000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 651.693517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 447.533847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.021267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 238 15.59% 15.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 181 11.85% 27.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 5.50% 32.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.45% 37.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.65% 42.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 87 5.70% 47.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 52 3.41% 51.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 56 3.67% 54.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 690 45.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation -system.physmem.totQLat 75432750 # Total ticks spent queuing -system.physmem.totMemAccLat 367445250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 650.032658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 444.829113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.661041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 243 15.87% 15.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.15% 28.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 73 4.77% 32.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 4.25% 37.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 75 4.90% 41.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 100 6.53% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.81% 51.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 3.33% 54.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 695 45.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation +system.physmem.totQLat 71795500 # Total ticks spent queuing +system.physmem.totMemAccLat 363808000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4843.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4609.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23593.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23359.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14042 # Number of row buffer hits during reads +system.physmem.readRowHits 14039 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3935753.44 # Average gap between requests -system.physmem.pageHitRate 90.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 3934746.82 # Average gap between requests +system.physmem.pageHitRate 90.14 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6259680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3415500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2494246185 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34588236750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41159350290 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.511167 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57530940500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2046720000 # Time in different power states +system.physmem_0.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2491685460 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34581139500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41148640140 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.507037 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57518843500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2046200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1716061500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713017750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2575259145 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34517172750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41161458375 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.545560 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57412676250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046720000 # Time in different power states +system.physmem_1.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2548940535 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34530915750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41147955240 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.495861 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57435989500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2046200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1834237500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1796249000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20766617 # Number of BP lookups -system.cpu.branchPred.condPredicted 17069689 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20766613 # Number of BP lookups +system.cpu.branchPred.condPredicted 17069686 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8958723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8857106 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8958713 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8857097 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.865720 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62714 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.865730 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122591037 # number of cpu cycles simulated +system.cpu.numCycles 122559681 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2197459 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2197712 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.353059 # CPI: cycles per instruction -system.cpu.ipc 0.739066 # IPC: instructions per cycle -system.cpu.tickCycles 109335027 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13256010 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.352713 # CPI: cycles per instruction +system.cpu.ipc 0.739255 # IPC: instructions per cycle +system.cpu.tickCycles 109336366 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13223315 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946108 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.919530 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267744 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.962336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267632 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644321 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20526719250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.919530 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883037 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883037 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.644203 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20520732500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.962336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 254 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2248 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463926 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463926 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660805 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463928 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463928 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598652 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598652 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660698 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660698 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259462 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259462 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259970 # number of overall hits -system.cpu.dcache.overall_hits::total 26259970 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914937 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914937 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74176 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74176 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26259350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259858 # number of overall hits +system.cpu.dcache.overall_hits::total 26259858 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914943 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74283 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74283 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 989113 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989113 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989117 # number of overall misses -system.cpu.dcache.overall_misses::total 989117 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11917910744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11917910744 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566961500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2566961500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14484872244 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14484872244 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14484872244 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14484872244 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513594 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 989226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989230 # number of overall misses +system.cpu.dcache.overall_misses::total 989230 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918923000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918923000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2541568000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2541568000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14460491000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14460491000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14460491000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14460491000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513595 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248575 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248575 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27249087 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27249087 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015666 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015666 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 27248576 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248576 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27249088 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27249088 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036300 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036300 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14644.304790 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14644.245569 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.036304 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036304 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036303 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.956871 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.956871 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34214.665536 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34214.665536 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14617.985172 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14617.985172 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.926064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14617.926064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,14 +478,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks system.cpu.dcache.writebacks::total 943289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11503 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11503 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27409 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27409 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38912 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38912 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38912 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38912 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11509 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11509 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950201 system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412555256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412555256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464079000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464079000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876634256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11876634256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11876789756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11876789756 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865211000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865211000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480610000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480610000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345821000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12345821000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345977500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12345977500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses @@ -516,69 +516,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.568626 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.568626 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31659.289670 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31659.289670 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.852039 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.852039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.975719 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.975719 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 690.424253 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27792420 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.428077 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27792848 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34653.890274 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34654.423940 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.424253 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337121 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337121 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.428077 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337123 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337123 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55587246 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55587246 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27792420 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27792420 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27792420 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27792420 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27792420 # number of overall hits -system.cpu.icache.overall_hits::total 27792420 # number of overall hits +system.cpu.icache.tags.tag_accesses 55588102 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55588102 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27792848 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27792848 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27792848 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27792848 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27792848 # number of overall hits +system.cpu.icache.overall_hits::total 27792848 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60382998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60382998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60382998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60382998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60382998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60382998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27793222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27793222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27793222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27793222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27793222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27793222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59599500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59599500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59599500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59599500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59599500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59599500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27793650 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27793650 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27793650 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27793650 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27793650 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27793650 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75290.521197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75290.521197 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74313.591022 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74313.591022 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74313.591022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74313.591022 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58841002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58841002 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58841002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58841002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58841002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58841002 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58797500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 58797500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58797500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 58797500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58797500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 58797500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73367.832918 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73367.832918 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73313.591022 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73313.591022 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.234608 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831338 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10246.423743 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1834010 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.717940 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.889696 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.355364 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.450791 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.428453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9356.530979 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.454442 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.438322 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285539 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312660 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312696 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -632,78 +632,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15216684 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15216684 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903201 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 15238060 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15238060 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 943289 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943289 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903175 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 903175 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935398 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935424 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 935398 # number of overall hits system.cpu.l2cache.overall_hits::total 935424 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 776 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 79311250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073550250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1073550250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1095095500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1152861500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1095095500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1152861500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903437 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066648000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1066648000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57320500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57320500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21756000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21756000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1088404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1145724500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1088404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1145724500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 943289 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943289 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903437 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 903437 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967581 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74440.721649 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82233.778626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76407.755299 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73813.961084 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73813.961084 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73986.747529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73986.747529 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73339.383938 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73339.383938 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73866.623711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73866.623711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83038.167939 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83038.167939 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73528.719035 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73528.719035 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -712,93 +718,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # 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mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61922.803618 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70100.585938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63955.339806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61313.686056 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61313.686056 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63339.383938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63339.383938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63866.925065 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63866.925065 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73457.031250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73457.031250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2672 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843697 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845301 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903437 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846366 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2847973 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1894295 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1897118 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1894295 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1897118 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1894295 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1890436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1897118 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891848000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1372498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428685244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1425308994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) @@ -814,9 +827,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21690500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21740500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82133750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82134000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index cb0d7cfc4..37d15d84b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058203 # Number of seconds simulated -sim_ticks 58203290500 # Number of ticks simulated -final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058174 # Number of seconds simulated +sim_ticks 58174017500 # Number of ticks simulated +final_tick 58174017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131910 # Simulator instruction rate (inst/s) -host_op_rate 132567 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84750962 # Simulator tick rate (ticks/s) -host_mem_usage 445160 # Number of bytes of host memory used -host_seconds 686.76 # Real time elapsed on the host +host_inst_rate 129950 # Simulator instruction rate (inst/s) +host_op_rate 130597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83449704 # Simulator tick rate (ticks/s) +host_mem_usage 446256 # Number of bytes of host memory used +host_seconds 697.11 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 930624 # Number of bytes read from this memory -system.physmem.bytes_read::total 1023424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 25536 # Number of bytes written to this memory -system.physmem.bytes_written::total 25536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14541 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15991 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 399 # Number of write requests responded to by this memory -system.physmem.num_writes::total 399 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 765318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15989199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17583611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 765318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 765318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 438738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 438738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 438738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 765318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15989199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18022349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15991 # Number of read requests accepted -system.physmem.writeReqs 399 # Number of write requests accepted -system.physmem.readBursts 15991 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1010944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue -system.physmem.bytesWritten 24064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1023424 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 25536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1015 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 49984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 930560 # Number of bytes read from this memory +system.physmem.bytes_read::total 1025024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 26560 # Number of bytes written to this memory +system.physmem.bytes_written::total 26560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14540 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16016 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 415 # Number of write requests responded to by this memory +system.physmem.num_writes::total 415 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 859215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15996145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17619962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 456561 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 456561 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 456561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 859215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15996145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18076524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16016 # Number of read requests accepted +system.physmem.writeReqs 415 # Number of write requests accepted +system.physmem.readBursts 16016 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 415 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1011776 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 13248 # Total number of bytes read from write queue +system.physmem.bytesWritten 25088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1025024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 26560 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 207 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1014 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 963 # Per bank write bursts -system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::2 957 # Per bank write bursts +system.physmem.perBankRdBursts::3 1028 # Per bank write bursts system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1139 # Per bank write bursts -system.physmem.perBankRdBursts::6 1118 # Per bank write bursts -system.physmem.perBankRdBursts::7 1101 # Per bank write bursts -system.physmem.perBankRdBursts::8 1044 # Per bank write bursts +system.physmem.perBankRdBursts::5 1144 # Per bank write bursts +system.physmem.perBankRdBursts::6 1126 # Per bank write bursts +system.physmem.perBankRdBursts::7 1093 # Per bank write bursts +system.physmem.perBankRdBursts::8 1040 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 939 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 898 # Per bank write bursts -system.physmem.perBankRdBursts::14 928 # Per bank write bursts -system.physmem.perBankRdBursts::15 921 # Per bank write bursts -system.physmem.perBankWrBursts::0 32 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts +system.physmem.perBankRdBursts::11 903 # Per bank write bursts +system.physmem.perBankRdBursts::12 912 # Per bank write bursts +system.physmem.perBankRdBursts::13 888 # Per bank write bursts +system.physmem.perBankRdBursts::14 938 # Per bank write bursts +system.physmem.perBankRdBursts::15 925 # Per bank write bursts +system.physmem.perBankWrBursts::0 43 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 16 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 9 # Per bank write bursts -system.physmem.perBankWrBursts::5 45 # Per bank write bursts -system.physmem.perBankWrBursts::6 72 # Per bank write bursts -system.physmem.perBankWrBursts::7 35 # Per bank write bursts -system.physmem.perBankWrBursts::8 36 # Per bank write bursts +system.physmem.perBankWrBursts::2 7 # Per bank write bursts +system.physmem.perBankWrBursts::3 6 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts +system.physmem.perBankWrBursts::5 44 # Per bank write bursts +system.physmem.perBankWrBursts::6 74 # Per bank write bursts +system.physmem.perBankWrBursts::7 25 # Per bank write bursts +system.physmem.perBankWrBursts::8 45 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 13 # Per bank write bursts -system.physmem.perBankWrBursts::11 2 # Per bank write bursts -system.physmem.perBankWrBursts::12 5 # Per bank write bursts -system.physmem.perBankWrBursts::13 37 # Per bank write bursts -system.physmem.perBankWrBursts::14 47 # Per bank write bursts -system.physmem.perBankWrBursts::15 27 # Per bank write bursts +system.physmem.perBankWrBursts::10 10 # Per bank write bursts +system.physmem.perBankWrBursts::11 5 # Per bank write bursts +system.physmem.perBankWrBursts::12 11 # Per bank write bursts +system.physmem.perBankWrBursts::13 32 # Per bank write bursts +system.physmem.perBankWrBursts::14 48 # Per bank write bursts +system.physmem.perBankWrBursts::15 32 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58203132500 # Total gap between requests +system.physmem.totGap 58173860500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15991 # Read request sizes (log2) +system.physmem.readPktSize::6 16016 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 399 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 415 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,94 +197,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 542.975328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 308.892213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 434.261771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 566 29.71% 29.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 241 12.65% 42.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 4.88% 47.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 55 2.89% 50.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 58 3.04% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 46 2.41% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 56 2.94% 58.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 2.26% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 747 39.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1905 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 21 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 751.047619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 33.268614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3285.704681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 20 95.24% 95.24% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 4.76% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 21 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 21 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.904762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.888741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.768424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 9.52% 9.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18 85.71% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 4.76% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 21 # Writes before turning the bus around for reads -system.physmem.totQLat 171453784 # Total ticks spent queuing -system.physmem.totMemAccLat 467628784 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10854.25 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.107772 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 304.077638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 432.159932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 590 30.57% 30.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 221 11.45% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 5.03% 47.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 3.58% 50.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 3.68% 54.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 49 2.54% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 2.64% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 42 2.18% 61.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 740 38.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1930 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 717.636364 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 31.597036 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3209.686449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 21 95.45% 95.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 4.55% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 22 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.818182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.808292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.588490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 9.09% 9.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20 90.91% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 22 # Writes before turning the bus around for reads +system.physmem.totQLat 169690298 # Total ticks spent queuing +system.physmem.totMemAccLat 466109048 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79045000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10733.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29604.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29483.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14158 # Number of row buffer hits during reads -system.physmem.writeRowHits 107 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 27.02 # Row buffer hit rate for writes -system.physmem.avgGap 3551136.82 # Average gap between requests -system.physmem.pageHitRate 88.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7854840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4285875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1354320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2465906355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32758411500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39103960890 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.860748 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54486158959 # Time in different power states -system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states +system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing +system.physmem.avgWrQLen 17.30 # Average write queue length when enqueuing +system.physmem.readRowHits 14150 # Number of row buffer hits during reads +system.physmem.writeRowHits 110 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.83 # Row buffer hit rate for writes +system.physmem.avgGap 3540494.22 # Average gap between requests +system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7832160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4273500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64506000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1289520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2476215945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32730681000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39084249885 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.881619 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54439969881 # Time in different power states +system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1772833541 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1788917619 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6546960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3572250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58468800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1082160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2423272635 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32795809500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39090238305 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.624974 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54548877915 # Time in different power states -system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states +system.physmem_1.actEnergy 6667920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3638250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58507800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1146960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2448182205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32755263750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39072858645 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.685955 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54482617084 # Time in different power states +system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1710114585 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1747288416 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28259243 # Number of BP lookups -system.cpu.branchPred.condPredicted 23281231 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11853879 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11785418 # Number of BTB hits +system.cpu.branchPred.lookups 28257086 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279263 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837830 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842064 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784394 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.422459 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75772 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.513007 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -403,128 +402,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116406582 # number of cpu cycles simulated +system.cpu.numCycles 116348036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748963 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134993544 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28259243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11861190 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114762985 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679231 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 807 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32304048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 578 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116353304 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 748817 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134985012 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860154 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114705506 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679063 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1007 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 831 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32301197 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116295692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58781536 50.52% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13944543 11.98% 62.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9221339 7.93% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34405886 29.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58725363 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13942075 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230802 7.94% 70.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34397452 29.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116353304 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242763 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.159673 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8844047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64088450 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33032847 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560591 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827369 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101287 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12347 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114434695 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1995559 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827369 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15306268 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49839660 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109196 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35408210 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14862601 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110902627 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415209 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132813 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1143128 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1515839 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 570040 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129962079 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483289738 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119478423 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 422 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116295692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242867 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.160183 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839821 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64036145 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034290 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558144 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827292 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101248 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114428571 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996975 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827292 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15280810 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49891272 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35424705 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14762264 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110897410 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415598 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11131669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144033 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1526935 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 476507 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129954934 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483266147 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119472382 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22649160 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22642015 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21571738 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26814245 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349583 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 611820 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 348925 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109694682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101389793 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1073874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18661898 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41702987 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116353304 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988581 # Number of insts issued each cycle +system.cpu.rename.skidInsts 21506426 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812625 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349337 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 517439 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253975 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109689181 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101387653 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074699 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18656398 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41685630 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116295692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989320 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54657362 46.98% 46.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31448211 27.03% 74.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 21997386 18.91% 92.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7054887 6.06% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195141 1.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54655211 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31361654 26.97% 73.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008607 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7072409 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197497 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 314 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116353304 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116295692 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9796132 48.71% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9605412 47.76% 96.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 708293 3.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9793566 48.69% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9616917 47.81% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 703878 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71985396 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71983899 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10709 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -546,90 +545,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 53 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24344165 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049339 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343332 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049532 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101389793 # Type of FU issued -system.cpu.iq.rate 0.870997 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20109899 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198342 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340316208 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128365476 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625945 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121499455 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 237 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 282715 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101387653 # Type of FU issued +system.cpu.iq.rate 0.871417 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20114424 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340259668 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128354519 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99625011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 453 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121501841 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 290489 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4338334 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1512 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1293 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336714 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1340 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604493 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7563 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130432 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827369 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8116840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 661308 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109715594 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827292 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8117300 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684188 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109710095 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26814245 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349583 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178503 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 319361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1293 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436568 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412973 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849541 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100128175 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23807340 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1261618 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26812625 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349337 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342189 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1340 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436578 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412874 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100126762 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806670 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1260891 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12666 # number of nop insts executed -system.cpu.iew.exec_refs 28725211 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624854 # Number of branches executed -system.cpu.iew.exec_stores 4917871 # Number of stores executed -system.cpu.iew.exec_rate 0.860159 # Inst execution rate -system.cpu.iew.wb_sent 99711063 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99626058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59706030 # num instructions producing a value -system.cpu.iew.wb_consumers 95562635 # num instructions consuming a value +system.cpu.iew.exec_nop 12667 # number of nop insts executed +system.cpu.iew.exec_refs 28724538 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624131 # Number of branches executed +system.cpu.iew.exec_stores 4917868 # Number of stores executed +system.cpu.iew.exec_rate 0.860580 # Inst execution rate +system.cpu.iew.wb_sent 99709725 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99625125 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703453 # num instructions producing a value +system.cpu.iew.wb_consumers 95545682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.855846 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624784 # average fanout of values written-back +system.cpu.iew.wb_rate 0.856268 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624868 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17389920 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17384546 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113660326 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801103 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737104 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825591 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113603530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801504 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.738080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77212273 67.93% 67.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18641375 16.40% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7152706 6.29% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3462873 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1652643 1.45% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 524647 0.46% 95.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 723706 0.64% 96.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178634 0.16% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4111469 3.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77180399 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18615023 16.39% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7150693 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3466326 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1641860 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 544762 0.48% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 180030 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120085 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113660326 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113603530 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -675,78 +674,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4111469 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217986682 # The number of ROB reads -system.cpu.rob.rob_writes 219580711 # The number of ROB writes -system.cpu.timesIdled 588 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53278 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120085 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217915896 # The number of ROB reads +system.cpu.rob.rob_writes 219569120 # The number of ROB writes +system.cpu.timesIdled 587 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284986 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284986 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778219 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778219 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108112805 # number of integer regfile reads -system.cpu.int_regfile_writes 58701882 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369068913 # number of cc regfile reads -system.cpu.cc_regfile_writes 58692415 # number of cc regfile writes -system.cpu.misc_regfile_reads 28415527 # number of misc regfile reads +system.cpu.cpi 1.284339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284339 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778610 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778610 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111439 # number of integer regfile reads +system.cpu.int_regfile_writes 58700930 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads +system.cpu.fp_regfile_writes 95 # number of floating regfile writes +system.cpu.cc_regfile_reads 369063438 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693153 # number of cc regfile writes +system.cpu.misc_regfile_reads 28414947 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5469565 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.787779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18297385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470077 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.344996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35255000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.787779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999586 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999586 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5470195 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.789215 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18252015 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336317 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35049500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.789215 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999588 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999588 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61924887 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61924887 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13934133 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13934133 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4354955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4354955 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61908703 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61908703 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13889937 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13889937 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353797 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353797 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18289088 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18289088 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18289610 # number of overall hits -system.cpu.dcache.overall_hits::total 18289610 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9549988 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9549988 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 380026 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 380026 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18243734 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18243734 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18244256 # number of overall hits +system.cpu.dcache.overall_hits::total 18244256 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585777 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585777 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381184 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381184 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9930014 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9930014 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9930021 # number of overall misses -system.cpu.dcache.overall_misses::total 9930021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88444420972 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88444420972 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962617493 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3962617493 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92407038465 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92407038465 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92407038465 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92407038465 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23484121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23484121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9966961 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9966961 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9966968 # number of overall misses +system.cpu.dcache.overall_misses::total 9966968 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88717689000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88717689000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3954782792 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3954782792 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92672471792 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92672471792 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92672471792 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92672471792 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23475714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23475714 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -755,302 +754,298 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28219102 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28219102 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28219631 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28219631 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080259 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28210695 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28210695 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28211224 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28211224 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408327 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080504 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.351890 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.351890 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.351883 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.351883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.207550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.207550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10427.227329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10427.227329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.831640 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9305.831640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.825080 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9305.825080 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 306116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 36058 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120736 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535416 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.828797 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.353304 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353304 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353298 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353298 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.138003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.138003 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10374.996831 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10374.996831 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9297.966731 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9297.966731 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9297.960201 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9297.960201 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 330068 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 99317 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121445 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12837 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.736777 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5437967 # number of writebacks -system.cpu.dcache.writebacks::total 5437967 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4312992 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4312992 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146947 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 146947 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5436552 # number of writebacks +system.cpu.dcache.writebacks::total 5436552 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337556 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337556 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158702 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158702 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4459939 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4459939 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4459939 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4459939 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5236996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233079 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 233079 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496258 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496258 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496258 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496258 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248221 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248221 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222482 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222482 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470075 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470075 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470079 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470079 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40520727758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40520727758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2294964437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2294964437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42815692195 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42815692195 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42815905195 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42815905195 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 5470703 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470703 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470707 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470707 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43246268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43246268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2278267197 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2278267197 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45524535697 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45524535697 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45524750197 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45524750197 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223560 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223560 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193843 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193843 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193839 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193839 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.399028 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.399028 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9846.294334 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9846.294334 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.258711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.258711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.291927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.291927 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.176719 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.176719 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10240.231556 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10240.231556 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8321.514748 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8321.514748 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8321.547873 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8321.547873 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 449 # number of replacements -system.cpu.icache.tags.tagsinuse 428.262881 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32302878 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35575.856828 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 451 # number of replacements +system.cpu.icache.tags.tagsinuse 428.509106 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32300030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35494.538462 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.262881 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836451 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836451 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.509106 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836932 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836932 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64608978 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64608978 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32302878 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32302878 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32302878 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32302878 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32302878 # number of overall hits -system.cpu.icache.overall_hits::total 32302878 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses -system.cpu.icache.overall_misses::total 1157 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62067238 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62067238 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62067238 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62067238 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62067238 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62067238 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32304035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32304035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32304035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32304035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32304035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32304035 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64603278 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64603278 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32300030 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32300030 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32300030 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32300030 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32300030 # number of overall hits +system.cpu.icache.overall_hits::total 32300030 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61388483 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61388483 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61388483 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61388483 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61388483 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61388483 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32301184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32301184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32301184 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32301184 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32301184 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32301184 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53644.976664 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53644.976664 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53644.976664 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53644.976664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53644.976664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53644.976664 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18268 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 226 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53196.259099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53196.259099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53196.259099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53196.259099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53196.259099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53196.259099 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19635 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 227 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.831858 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.497797 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49773732 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49773732 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49773732 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49773732 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49773732 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49773732 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50524487 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50524487 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50524487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50524487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50524487 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50524487 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54816.885463 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54816.885463 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54816.885463 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54816.885463 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54816.885463 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54816.885463 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55521.414286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55521.414286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55521.414286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55521.414286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55521.414286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55521.414286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4492873 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15999 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 665.806613 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074393 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 580 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12072.245633 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10689052 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 16020 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 667.231710 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11108.777118 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 571.857159 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 208.039641 # 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number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25379758 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25379758 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41955257 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48552508 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 90507765 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41955257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48552508 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 829862007 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 920369772 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 415 # number of writebacks +system.cpu.l2cache.writebacks::total 415 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 169 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 169 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 46 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 46 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 217 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20231 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 20231 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 340 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 340 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 695 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 695 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 441 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 441 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 781 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 781 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21707 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 860658985 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 860658985 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26049500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26049500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43944500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43944500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25180500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25180500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43944500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51230000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 95174500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43944500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51230000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 860658985 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 955833485 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001454 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001454 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000138 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000265 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000138 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001501 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001501 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.763736 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.003962 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60280.541667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55837.951807 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58621.068407 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41027.438918 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74866.542773 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74866.542773 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60280.541667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64393.246684 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62419.148276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60280.541667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64393.246684 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42458.355492 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003967 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 42541.593841 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76616.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76616.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63229.496403 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63229.496403 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 57098.639456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 57098.639456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63229.496403 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65595.390525 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64481.368564 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63229.496403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65595.390525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44033.421707 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5237776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5237776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5437967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22114 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 233209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 233209 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1816 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16378127 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16379943 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698114944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 22116 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.002023 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 5245099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5436967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 31344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22118 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244189 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408706 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698064576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 698122816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22698 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10964961 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.002070 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045451 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10908954 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 22114 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10942263 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 22698 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1495005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10964961 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10907683500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1366996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8205165681 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206064991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 15652 # Transaction distribution -system.membus.trans_dist::ReadResp 15652 # Transaction distribution -system.membus.trans_dist::Writeback 399 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 339 # Transaction distribution -system.membus.trans_dist::ReadExResp 339 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32385 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32385 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1048960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1048960 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15676 # Transaction distribution +system.membus.trans_dist::Writeback 415 # Transaction distribution +system.membus.trans_dist::CleanEvict 117 # Transaction distribution +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15676 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32564 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1051584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1051584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16392 # Request fanout histogram +system.membus.snoop_fanout::samples 16548 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16392 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16548 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16392 # Request fanout histogram -system.membus.reqLayer0.occupancy 27168735 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16548 # Request fanout histogram +system.membus.reqLayer0.occupancy 27912645 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 83645045 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 83778508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b81c12b39..86fbc3533 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488530500 # Number of ticks simulated -final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488535500 # Number of ticks simulated +final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1163469 # Simulator instruction rate (inst/s) -host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1724927568 # Simulator tick rate (ticks/s) -host_mem_usage 425840 # Number of bytes of host memory used -host_seconds 209.57 # Real time elapsed on the host +host_inst_rate 1224088 # Simulator instruction rate (inst/s) +host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1814798992 # Simulator tick rate (ticks/s) +host_mem_usage 426288 # Number of bytes of host memory used +host_seconds 199.19 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 2606821 # To system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977061 # number of cpu cycles simulated +system.cpu.numCycles 722977071 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,24 +206,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -284,34 +284,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy @@ -323,78 +323,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits system.cpu.l2cache.overall_hits::total 924850 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,84 +409,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1875719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1875719 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1036 # Transaction distribution system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) @@ -496,9 +508,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1d5681a17..6f4514f73 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062108 # Number of seconds simulated -sim_ticks 62108139000 # Number of ticks simulated -final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062104 # Number of seconds simulated +sim_ticks 62103992500 # Number of ticks simulated +final_tick 62103992500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114338 # Simulator instruction rate (inst/s) -host_op_rate 201331 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44948395 # Simulator tick rate (ticks/s) -host_mem_usage 455560 # Number of bytes of host memory used -host_seconds 1381.77 # Real time elapsed on the host +host_inst_rate 108853 # Simulator instruction rate (inst/s) +host_op_rate 191673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42789284 # Simulator tick rate (ticks/s) +host_mem_usage 455804 # Number of bytes of host memory used +host_seconds 1451.39 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1886080 # Number of bytes read from this memory -system.physmem.bytes_read::total 1951040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 13952 # Number of bytes written to this memory -system.physmem.bytes_written::total 13952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29470 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30485 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 218 # Number of write requests responded to by this memory -system.physmem.num_writes::total 218 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1045918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30367679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31413596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1045918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1045918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 224640 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 224640 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 224640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1045918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30367679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31638237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30485 # Number of read requests accepted -system.physmem.writeReqs 218 # Number of write requests accepted -system.physmem.readBursts 30485 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 218 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 12736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1951040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 13952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883648 # Number of bytes read from this memory +system.physmem.bytes_read::total 1948480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11776 # Number of bytes written to this memory +system.physmem.bytes_written::total 11776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29432 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 184 # Number of write requests responded to by this memory +system.physmem.num_writes::total 184 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1043926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30330546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31374472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 189617 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 189617 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 189617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30330546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31564090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30446 # Number of read requests accepted +system.physmem.writeReqs 184 # Number of write requests accepted +system.physmem.readBursts 30446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 184 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue +system.physmem.bytesWritten 10368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1948544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1926 # Per bank write bursts -system.physmem.perBankRdBursts::1 2065 # Per bank write bursts -system.physmem.perBankRdBursts::2 2030 # Per bank write bursts -system.physmem.perBankRdBursts::3 1931 # Per bank write bursts -system.physmem.perBankRdBursts::4 2028 # Per bank write bursts -system.physmem.perBankRdBursts::5 1903 # Per bank write bursts -system.physmem.perBankRdBursts::6 1964 # Per bank write bursts -system.physmem.perBankRdBursts::7 1862 # Per bank write bursts +system.physmem.perBankRdBursts::0 1927 # Per bank write bursts +system.physmem.perBankRdBursts::1 2069 # Per bank write bursts +system.physmem.perBankRdBursts::2 2026 # Per bank write bursts +system.physmem.perBankRdBursts::3 1929 # Per bank write bursts +system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::5 1901 # Per bank write bursts +system.physmem.perBankRdBursts::6 1959 # Per bank write bursts +system.physmem.perBankRdBursts::7 1865 # Per bank write bursts system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1938 # Per bank write bursts -system.physmem.perBankRdBursts::10 1804 # Per bank write bursts -system.physmem.perBankRdBursts::11 1795 # Per bank write bursts +system.physmem.perBankRdBursts::9 1937 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::11 1796 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts system.physmem.perBankRdBursts::14 1819 # Per bank write bursts -system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 14 # Per bank write bursts -system.physmem.perBankWrBursts::1 89 # Per bank write bursts -system.physmem.perBankWrBursts::2 33 # Per bank write bursts -system.physmem.perBankWrBursts::3 21 # Per bank write bursts -system.physmem.perBankWrBursts::4 13 # Per bank write bursts -system.physmem.perBankWrBursts::5 7 # Per bank write bursts +system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankWrBursts::0 25 # Per bank write bursts +system.physmem.perBankWrBursts::1 94 # Per bank write bursts +system.physmem.perBankWrBursts::2 8 # Per bank write bursts +system.physmem.perBankWrBursts::3 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 7 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts system.physmem.perBankWrBursts::6 13 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 6 # Per bank write bursts +system.physmem.perBankWrBursts::9 5 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts @@ -82,25 +82,25 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62107943500 # Total gap between requests +system.physmem.totGap 62103972000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30485 # Read request sizes (log2) +system.physmem.readPktSize::6 30446 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 218 # Write request sizes (log2) +system.physmem.writePktSize::6 184 # Write request sizes (log2) system.physmem.rdQLenPdf::0 29885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,225 +193,221 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2733 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 715.170143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 514.587482 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 389.057467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 358 13.10% 13.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 248 9.07% 22.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 120 4.39% 26.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 119 4.35% 30.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 123 4.50% 35.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 99 3.62% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 98 3.59% 42.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 77 2.82% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1491 54.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2733 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 11 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2756.545455 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.211839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 9104.288367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 10 90.91% 90.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 9.09% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 11 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 11 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.090909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.068275 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.943880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 9.09% 9.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 8 72.73% 81.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 9.09% 90.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 9.09% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 11 # Writes before turning the bus around for reads -system.physmem.totQLat 137229500 # Total ticks spent queuing -system.physmem.totMemAccLat 706742000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4517.99 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2720 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 718.117647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 516.851204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 389.329010 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 349 12.83% 12.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 252 9.26% 22.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 126 4.63% 26.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 106 3.90% 30.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 106 3.90% 34.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 118 4.34% 38.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 88 3.24% 42.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 74 2.72% 44.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1501 55.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2720 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3367.333333 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 25.147360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10062.626521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 9 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads +system.physmem.totQLat 131808750 # Total ticks spent queuing +system.physmem.totMemAccLat 701190000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4340.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23267.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23090.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.38 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.79 # Average write queue length when enqueuing -system.physmem.readRowHits 27693 # Number of row buffer hits during reads -system.physmem.writeRowHits 139 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 2022862.38 # Average gap between requests -system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10893960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5944125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1134000 # Energy for write commands per rank (pJ) +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 13.82 # Average write queue length when enqueuing +system.physmem.readRowHits 27697 # Number of row buffer hits during reads +system.physmem.writeRowHits 108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.70 # Row buffer hit rate for writes +system.physmem.avgGap 2027553.77 # Average gap between requests +system.physmem.pageHitRate 91.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 10848600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5919375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122421000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 997920 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2882954835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34733126250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41812553730 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.273290 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57766447750 # Time in different power states +system.physmem_0.actBackEnergy 2874471525 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34740567750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41811500730 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.256335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57777967000 # Time in different power states system.physmem_0.memoryStateTime::REF 2073760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2264083750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2251676750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9699480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5292375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114270000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114371400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3028786200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34605195750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41819570205 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.386420 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57553191500 # Time in different power states +system.physmem_1.actBackEnergy 3081237030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34559194500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41826144555 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.492132 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57475856750 # Time in different power states system.physmem_1.memoryStateTime::REF 2073760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2477594500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2554341750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37389273 # Number of BP lookups -system.cpu.branchPred.condPredicted 37389273 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 796060 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21398380 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21281300 # Number of BTB hits +system.cpu.branchPred.lookups 37407153 # Number of BP lookups +system.cpu.branchPred.condPredicted 37407153 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 797525 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21397569 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21291133 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.452856 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5538224 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5409 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.502579 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5522199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5378 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 124216279 # number of cpu cycles simulated +system.cpu.numCycles 124207986 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28231712 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 201414270 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37389273 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26819524 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 95072949 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1663625 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 802 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13794 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 27828273 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190340 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 124151097 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.859474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.368729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28243826 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 201531916 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37407153 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26813332 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 95053081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1666271 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 14570 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.CacheLines 27854872 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208775 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 124145503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.860655 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.369153 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 63239379 50.94% 50.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3665567 2.95% 53.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3524262 2.84% 56.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5966051 4.81% 61.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7629037 6.14% 67.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5460577 4.40% 72.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3340077 2.69% 74.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2074079 1.67% 76.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29252068 23.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 63227150 50.93% 50.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3664165 2.95% 53.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3505505 2.82% 56.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5966108 4.81% 61.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7642313 6.16% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5450974 4.39% 72.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3347715 2.70% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2079081 1.67% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29262492 23.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 124151097 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.301001 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.621480 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13268959 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63731322 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 36520631 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9798373 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 831812 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 334996047 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 831812 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18591577 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8853243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16711 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40784813 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55072941 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328614087 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 765426 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48317500 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4996682 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 330544508 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 872885571 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537662987 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 823 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 124145503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.301165 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.622536 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13298609 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63688691 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 36532978 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9792090 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 833135 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 335053232 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 833135 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18606460 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8830273 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16174 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40807487 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55051974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328692220 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2265 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 765831 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48323645 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4961410 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 330669691 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 873156420 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537756143 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 567 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51331761 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 491 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 491 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66256508 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106310670 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36525048 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49788623 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8449867 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 325445308 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307970327 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51339 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 47254612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68858955 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1323 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 124151097 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.480609 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.128122 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 51456944 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 481 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66169497 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106330183 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36531613 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49817317 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8395275 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 325507363 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2500 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 308019505 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47317399 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68952386 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2055 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 124145503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.481117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.143684 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30600533 24.65% 24.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19593175 15.78% 40.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16755552 13.50% 53.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17045170 13.73% 67.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15962727 12.86% 80.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12649852 10.19% 90.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5781799 4.66% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4158736 3.35% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1603553 1.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30872061 24.87% 24.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19525697 15.73% 40.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16787256 13.52% 54.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17357634 13.98% 68.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14846406 11.96% 80.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12689504 10.22% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6302474 5.08% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3917362 3.16% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1847109 1.49% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 124151097 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 124145503 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 316480 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3709774 87.98% 95.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 190338 4.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 329941 8.31% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3456308 87.04% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 184474 4.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 175386232 56.95% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11196 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 347 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 45 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 175410718 56.95% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11212 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 340 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued @@ -437,84 +433,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98505322 31.99% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34033845 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98529790 31.99% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34034069 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307970327 # Type of FU issued -system.cpu.iq.rate 2.479307 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4216592 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013692 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 744358969 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372741153 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 305973250 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 713 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1268 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 215 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 312153240 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 339 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58265174 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 308019505 # Type of FU issued +system.cpu.iq.rate 2.479869 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3970723 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 744205245 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 372866875 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 306008038 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 524 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 864 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 311956642 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 248 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58273942 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15531285 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58585 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41983 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5085296 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15550798 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41716 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5091861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 124310 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3678 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 142532 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 831812 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5699246 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3054980 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 325447076 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 123578 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106310670 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36525048 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3058247 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41983 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 401587 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 444043 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 845630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 306900581 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98149248 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1069746 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 833135 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5706209 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3030570 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 325509863 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125935 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106330183 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36531613 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 471 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2800 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3033928 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41716 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 402612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445047 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847659 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 306958421 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98183223 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1061084 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131968833 # number of memory reference insts executed -system.cpu.iew.exec_branches 31535132 # Number of branches executed -system.cpu.iew.exec_stores 33819585 # Number of stores executed -system.cpu.iew.exec_rate 2.470695 # Inst execution rate -system.cpu.iew.wb_sent 306301702 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 305973465 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231572201 # num instructions producing a value -system.cpu.iew.wb_consumers 336082865 # num instructions consuming a value +system.cpu.iew.exec_refs 132003276 # number of memory reference insts executed +system.cpu.iew.exec_branches 31537655 # Number of branches executed +system.cpu.iew.exec_stores 33820053 # Number of stores executed +system.cpu.iew.exec_rate 2.471326 # Inst execution rate +system.cpu.iew.wb_sent 306335531 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 306008206 # cumulative count of insts written-back +system.cpu.iew.wb_producers 231609196 # num instructions producing a value +system.cpu.iew.wb_consumers 336109097 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.463232 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689033 # average fanout of values written-back +system.cpu.iew.wb_rate 2.463676 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689089 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 47355755 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 47420049 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 796864 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117707358 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.363425 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.086682 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 798401 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117693042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.363712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.086908 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 53343112 45.32% 45.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15934290 13.54% 58.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11043478 9.38% 68.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8763951 7.45% 75.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880549 1.60% 77.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1728612 1.47% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 852753 0.72% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 687313 0.58% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23473300 19.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 53351319 45.33% 45.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15952359 13.55% 58.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10962553 9.31% 68.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8763534 7.45% 75.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1923790 1.63% 77.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1729278 1.47% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 853123 0.72% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 692579 0.59% 80.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23464507 19.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117707358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117693042 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -560,324 +556,330 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23473300 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 419782277 # The number of ROB reads -system.cpu.rob.rob_writes 657549499 # The number of ROB writes -system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23464507 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 419841048 # The number of ROB reads +system.cpu.rob.rob_writes 657686557 # The number of ROB writes +system.cpu.timesIdled 566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 62483 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.786236 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.786236 # CPI: Total CPI of All Threads -system.cpu.ipc 1.271883 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.271883 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 493639930 # number of integer regfile reads -system.cpu.int_regfile_writes 240886983 # number of integer regfile writes -system.cpu.fp_regfile_reads 187 # number of floating regfile reads -system.cpu.fp_regfile_writes 111 # number of floating regfile writes -system.cpu.cc_regfile_reads 107695799 # number of cc regfile reads -system.cpu.cc_regfile_writes 64567771 # number of cc regfile writes -system.cpu.misc_regfile_reads 196286158 # number of misc regfile reads +system.cpu.cpi 0.786183 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.786183 # CPI: Total CPI of All Threads +system.cpu.ipc 1.271968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.271968 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 493729388 # number of integer regfile reads +system.cpu.int_regfile_writes 240917610 # number of integer regfile writes +system.cpu.fp_regfile_reads 146 # number of floating regfile reads +system.cpu.fp_regfile_writes 96 # number of floating regfile writes +system.cpu.cc_regfile_reads 107705980 # number of cc regfile reads +system.cpu.cc_regfile_writes 64576396 # number of cc regfile writes +system.cpu.misc_regfile_reads 196329384 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072438 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.873358 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68418587 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076534 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.948455 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19755616250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.873358 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993133 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993133 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072430 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.090496 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68424035 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076526 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.951206 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19739908500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.090496 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993186 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993186 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 606 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3373 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144472022 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144472022 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37072750 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37072750 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345837 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345837 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68418587 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68418587 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68418587 # number of overall hits -system.cpu.dcache.overall_hits::total 68418587 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2685242 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2685242 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93915 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93915 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2779157 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2779157 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2779157 # number of overall misses -system.cpu.dcache.overall_misses::total 2779157 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32132974500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32132974500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2979596244 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2979596244 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35112570744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35112570744 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35112570744 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35112570744 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39757992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39757992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 144493228 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 144493228 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37078222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37078222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345813 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345813 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68424035 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68424035 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68424035 # number of overall hits +system.cpu.dcache.overall_hits::total 68424035 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2690377 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2690377 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93939 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93939 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2784316 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2784316 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2784316 # number of overall misses +system.cpu.dcache.overall_misses::total 2784316 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32316565000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32316565000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2955969494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2955969494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35272534494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35272534494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35272534494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35272534494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39768599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39768599 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71197744 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71197744 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71197744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71197744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067540 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039034 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039034 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039034 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039034 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11966.509722 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11966.509722 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31726.521259 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31726.521259 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12634.252309 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12634.252309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12634.252309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12634.252309 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 199012 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 71208351 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71208351 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71208351 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71208351 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067651 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067651 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039101 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039101 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039101 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039101 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12011.909483 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12011.909483 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31466.903991 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31466.903991 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12668.294293 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12668.294293 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221313 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39951 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43094 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.981402 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135587 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066723 # number of writebacks -system.cpu.dcache.writebacks::total 2066723 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690734 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 690734 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11889 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11889 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 702623 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 702623 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 702623 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 702623 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82026 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82026 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076534 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076534 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076534 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076534 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23036962750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23036962750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2767409747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2767409747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25804372497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25804372497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25804372497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25804372497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029166 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029166 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029166 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029166 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11550.198219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11550.198219 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33738.201875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33738.201875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12426.655425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12426.655425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12426.655425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12426.655425 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2066711 # number of writebacks +system.cpu.dcache.writebacks::total 2066711 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 695911 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 695911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11877 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11877 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 707788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 707788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 707788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 707788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994466 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994466 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82062 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24203306500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24203306500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2798613994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2798613994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27001920494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27001920494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27001920494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27001920494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12135.231435 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12135.231435 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34103.653262 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34103.653262 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 61 # number of replacements -system.cpu.icache.tags.tagsinuse 828.295860 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27826925 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 64 # number of replacements +system.cpu.icache.tags.tagsinuse 833.320748 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27853507 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26964.074612 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 26989.832364 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 828.295860 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.404441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.404441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 971 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 833.320748 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.406895 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.406895 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 968 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55657578 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55657578 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27826925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27826925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27826925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27826925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27826925 # number of overall hits -system.cpu.icache.overall_hits::total 27826925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses -system.cpu.icache.overall_misses::total 1348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101838000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101838000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101838000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101838000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101838000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101838000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27828273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27828273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27828273 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27828273 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27828273 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27828273 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75547.477745 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75547.477745 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75547.477745 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75547.477745 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75547.477745 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75547.477745 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.472656 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55710776 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55710776 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27853507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27853507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27853507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27853507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27853507 # number of overall hits +system.cpu.icache.overall_hits::total 27853507 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1365 # number of overall misses +system.cpu.icache.overall_misses::total 1365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98783500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98783500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98783500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98783500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98783500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98783500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27854872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27854872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27854872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27854872 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27854872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27854872 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72368.864469 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72368.864469 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72368.864469 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72368.864469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72368.864469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72368.864469 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.714286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 316 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 316 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 316 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 316 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 316 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 333 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 333 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 333 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 333 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1032 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1032 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1032 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78148000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78148000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78148000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78148000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77158.914729 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77158.914729 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77158.914729 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77158.914729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77158.914729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77158.914729 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.806202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.806202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.806202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.806202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.806202 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 683.118816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 253.452964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.602576 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.631158 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29933 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1394 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2150702500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2227097000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 76394500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2150702500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2227097000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 2066711 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066711 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82092 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82092 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1032 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1032 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994436 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1994436 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076534 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077566 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076528 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077560 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076534 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077566 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983527 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000234 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000743 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353411 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983527 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014192 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014673 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983527 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014192 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014673 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77250.492611 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74201.820128 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76289.811066 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73376.202462 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73376.202462 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77250.492611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73389.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73517.844842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77250.492611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73389.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73517.844842 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 2076528 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077560 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353213 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353213 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.981589 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.981589 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000219 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000219 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014174 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014655 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014174 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014655 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73022.899710 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73022.899710 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75414.116486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75414.116486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76271.167048 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76271.167048 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75414.116486 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.127646 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73149.083623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75414.116486 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.127646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73149.083623 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,107 +888,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 218 # number of writebacks -system.cpu.l2cache.writebacks::total 218 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1015 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1482 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29003 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1015 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29470 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1015 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29470 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30485 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65734750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28861750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94596500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1765566500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1765566500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65734750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1794428250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1860163000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65734750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1794428250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1860163000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000234 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000743 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014673 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014673 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64763.300493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61802.462527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63830.296896 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60875.306003 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60875.306003 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64763.300493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60889.998303 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61018.960144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64763.300493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60889.998303 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61018.960144 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 184 # number of writebacks +system.cpu.l2cache.writebacks::total 184 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1013 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1013 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30446 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827412000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827412000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66264500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66264500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28980500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28980500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66264500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856392500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922657000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66264500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856392500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922657000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353213 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353213 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.981589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000219 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000219 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014174 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014655 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014174 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014655 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63022.899710 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63022.899710 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65414.116486 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65414.116486 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66316.933638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66316.933638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65414.116486 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63071.807155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63149.740524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65414.116486 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63071.807155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63149.740524 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1995500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066723 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82066 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221855 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 1995466 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6085 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82092 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82092 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994436 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6227603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265168448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265167168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265233216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 495 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4150549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.000119 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4144289 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4150054 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 495 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4150549 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4141738000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1740500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1548000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121586499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3114789000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1482 # Transaction distribution -system.membus.trans_dist::ReadResp 1482 # Transaction distribution -system.membus.trans_dist::Writeback 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 29003 # Transaction distribution -system.membus.trans_dist::ReadExResp 29003 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61188 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1964992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1964992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1964992 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1448 # Transaction distribution +system.membus.trans_dist::Writeback 184 # Transaction distribution +system.membus.trans_dist::CleanEvict 34 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1450 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61108 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1960192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1960192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1960192 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30703 # Request fanout histogram +system.membus.snoop_fanout::samples 30664 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30703 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30703 # Request fanout histogram -system.membus.reqLayer0.occupancy 42842500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30664 # Request fanout histogram +system.membus.reqLayer0.occupancy 42854000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160650000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 160427250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 02993075a..d40f8a71c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989065500 # Number of ticks simulated -final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365988859500 # Number of ticks simulated +final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 678113 # Simulator instruction rate (inst/s) -host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1570885616 # Simulator tick rate (ticks/s) -host_mem_usage 451452 # Number of bytes of host memory used -host_seconds 232.98 # Real time elapsed on the host +host_inst_rate 643347 # Simulator instruction rate (inst/s) +host_op_rate 1132831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1490347920 # Simulator tick rate (ticks/s) +host_mem_usage 451472 # Number of bytes of host memory used +host_seconds 245.57 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory -system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory -system.physmem.bytes_written::total 6400 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory +system.physmem.bytes_written::total 6528 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory -system.physmem.num_writes::total 100 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory +system.physmem.num_writes::total 102 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5113336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5253756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5113336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5271592 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978131 # number of cpu cycles simulated +system.cpu.numCycles 731977719 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles +system.cpu.num_busy_cycles 731977718.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -100,12 +100,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.488591 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 126079705500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488591 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498474000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498474000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598457000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598457000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28096931000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28096931000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28096931000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28096931000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.221389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.221389 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -172,8 +172,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks -system.cpu.dcache.writebacks::total 2062484 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks +system.cpu.dcache.writebacks::total 2062482 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses @@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23537754000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23537754000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492348000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492348000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26030102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26030102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26030102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26030102000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -198,22 +198,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.632473 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632473 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44233500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44233500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44233500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44233500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44233500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44233500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54744.430693 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54744.430693 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -273,117 +273,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43425500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43425500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43425500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43425500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43425500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43425500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53744.430693 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53744.430693 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 313 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20041.891909 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19329.043320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.394677 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 156.453912 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589876 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.611630 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42159500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 42159500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11392500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11392500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42159500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1535183500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1577343000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42159500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1535183500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1577343000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 2062482 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2062482 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.490660 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.490660 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.098389 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.098389 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,107 +398,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks -system.cpu.l2cache.writebacks::total 100 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks +system.cpu.l2cache.writebacks::total 102 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1233551000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1233551000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34129500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34129500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9222500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9222500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1242773500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1276903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34129500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1242773500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1276903000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 313 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.000076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.008704 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4130394 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 313 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1025 # Transaction distribution -system.membus.trans_dist::ReadResp 1025 # Transaction distribution -system.membus.trans_dist::Writeback 100 # Transaction distribution +system.membus.trans_dist::ReadResp 1020 # Transaction distribution +system.membus.trans_dist::Writeback 102 # Transaction distribution +system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::samples 30160 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30149 # Request fanout histogram -system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30160 # Request fanout histogram +system.membus.reqLayer0.occupancy 30601000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150253000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index c17d6c2b8..721b096f0 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.413311 # Number of seconds simulated -sim_ticks 413311471500 # Number of ticks simulated -final_tick 413311471500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.412968 # Number of seconds simulated +sim_ticks 412968287500 # Number of ticks simulated +final_tick 412968287500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320750 # Simulator instruction rate (inst/s) -host_op_rate 320750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216651718 # Simulator tick rate (ticks/s) -host_mem_usage 298932 # Number of bytes of host memory used -host_seconds 1907.72 # Real time elapsed on the host +host_inst_rate 309752 # Simulator instruction rate (inst/s) +host_op_rate 309752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209049423 # Simulator tick rate (ticks/s) +host_mem_usage 299216 # Number of bytes of host memory used +host_seconds 1975.46 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 170944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24150272 # Number of bytes read from this memory -system.physmem.bytes_read::total 24321216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724096 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377348 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380019 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292564 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292564 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 413596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58431168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58844764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 413596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 413596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45302628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45302628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45302628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 413596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58431168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104147392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380019 # Number of read requests accepted -system.physmem.writeReqs 292564 # Number of write requests accepted -system.physmem.readBursts 380019 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292564 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24298816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22400 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24321216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 350 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24125568 # Number of bytes read from this memory +system.physmem.bytes_read::total 24296576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18781376 # Number of bytes written to this memory +system.physmem.bytes_written::total 18781376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 376962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379634 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293459 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293459 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 414095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58419905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58833999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 414095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 414095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45478979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45478979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45478979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 414095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58419905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104312978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 379634 # Number of read requests accepted +system.physmem.writeReqs 293459 # Number of write requests accepted +system.physmem.readBursts 379634 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293459 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24275200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21376 # Total number of bytes read from write queue +system.physmem.bytesWritten 18779968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24296576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18781376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 334 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23743 # Per bank write bursts -system.physmem.perBankRdBursts::1 23222 # Per bank write bursts -system.physmem.perBankRdBursts::2 23516 # Per bank write bursts -system.physmem.perBankRdBursts::3 24520 # Per bank write bursts -system.physmem.perBankRdBursts::4 25462 # Per bank write bursts -system.physmem.perBankRdBursts::5 23584 # Per bank write bursts -system.physmem.perBankRdBursts::6 23675 # Per bank write bursts -system.physmem.perBankRdBursts::7 23980 # Per bank write bursts -system.physmem.perBankRdBursts::8 23177 # Per bank write bursts -system.physmem.perBankRdBursts::9 23949 # Per bank write bursts -system.physmem.perBankRdBursts::10 24669 # Per bank write bursts -system.physmem.perBankRdBursts::11 22747 # Per bank write bursts -system.physmem.perBankRdBursts::12 23729 # Per bank write bursts -system.physmem.perBankRdBursts::13 24425 # Per bank write bursts -system.physmem.perBankRdBursts::14 22797 # Per bank write bursts -system.physmem.perBankRdBursts::15 22474 # Per bank write bursts -system.physmem.perBankWrBursts::0 17756 # Per bank write bursts -system.physmem.perBankWrBursts::1 17433 # Per bank write bursts -system.physmem.perBankWrBursts::2 17901 # Per bank write bursts -system.physmem.perBankWrBursts::3 18770 # Per bank write bursts -system.physmem.perBankWrBursts::4 19442 # Per bank write bursts -system.physmem.perBankWrBursts::5 18538 # Per bank write bursts -system.physmem.perBankWrBursts::6 18680 # Per bank write bursts -system.physmem.perBankWrBursts::7 18573 # Per bank write bursts -system.physmem.perBankWrBursts::8 18350 # Per bank write bursts -system.physmem.perBankWrBursts::9 18834 # Per bank write bursts -system.physmem.perBankWrBursts::10 19126 # Per bank write bursts -system.physmem.perBankWrBursts::11 17963 # Per bank write bursts -system.physmem.perBankWrBursts::12 18227 # Per bank write bursts -system.physmem.perBankWrBursts::13 18693 # Per bank write bursts -system.physmem.perBankWrBursts::14 17147 # Per bank write bursts -system.physmem.perBankWrBursts::15 17105 # Per bank write bursts +system.physmem.perBankRdBursts::0 23720 # Per bank write bursts +system.physmem.perBankRdBursts::1 23189 # Per bank write bursts +system.physmem.perBankRdBursts::2 23443 # Per bank write bursts +system.physmem.perBankRdBursts::3 24493 # Per bank write bursts +system.physmem.perBankRdBursts::4 25427 # Per bank write bursts +system.physmem.perBankRdBursts::5 23582 # Per bank write bursts +system.physmem.perBankRdBursts::6 23638 # Per bank write bursts +system.physmem.perBankRdBursts::7 23957 # Per bank write bursts +system.physmem.perBankRdBursts::8 23144 # Per bank write bursts +system.physmem.perBankRdBursts::9 23961 # Per bank write bursts +system.physmem.perBankRdBursts::10 24713 # Per bank write bursts +system.physmem.perBankRdBursts::11 22767 # Per bank write bursts +system.physmem.perBankRdBursts::12 23721 # Per bank write bursts +system.physmem.perBankRdBursts::13 24378 # Per bank write bursts +system.physmem.perBankRdBursts::14 22727 # Per bank write bursts +system.physmem.perBankRdBursts::15 22440 # Per bank write bursts +system.physmem.perBankWrBursts::0 17784 # Per bank write bursts +system.physmem.perBankWrBursts::1 17460 # Per bank write bursts +system.physmem.perBankWrBursts::2 17942 # Per bank write bursts +system.physmem.perBankWrBursts::3 18842 # Per bank write bursts +system.physmem.perBankWrBursts::4 19508 # Per bank write bursts +system.physmem.perBankWrBursts::5 18590 # Per bank write bursts +system.physmem.perBankWrBursts::6 18730 # Per bank write bursts +system.physmem.perBankWrBursts::7 18662 # Per bank write bursts +system.physmem.perBankWrBursts::8 18408 # Per bank write bursts +system.physmem.perBankWrBursts::9 18932 # Per bank write bursts +system.physmem.perBankWrBursts::10 19251 # Per bank write bursts +system.physmem.perBankWrBursts::11 18034 # Per bank write bursts +system.physmem.perBankWrBursts::12 18264 # Per bank write bursts +system.physmem.perBankWrBursts::13 18730 # Per bank write bursts +system.physmem.perBankWrBursts::14 17177 # Per bank write bursts +system.physmem.perBankWrBursts::15 17123 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 413311383000 # Total gap between requests +system.physmem.totGap 412968199500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380019 # Read request sizes (log2) +system.physmem.readPktSize::6 379634 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292564 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293459 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 377911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,47 +144,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -193,128 +193,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142426 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.052266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.083619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.600685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 51194 35.94% 35.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38668 27.15% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13205 9.27% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8199 5.76% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5653 3.97% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3753 2.64% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3030 2.13% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2604 1.83% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16120 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142426 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17258 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.998378 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.944233 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17248 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 4 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.814019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.682339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.904056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50781 35.72% 35.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38739 27.25% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13305 9.36% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8117 5.71% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5703 4.01% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3753 2.64% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3029 2.13% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2502 1.76% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16252 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142181 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17324 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.893847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 236.830288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17315 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17258 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17258 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.950863 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.879940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.817078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17053 98.81% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 148 0.86% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.19% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17258 # Writes before turning the bus around for reads -system.physmem.totQLat 4042656250 # Total ticks spent queuing -system.physmem.totMemAccLat 11161450000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10647.84 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17324 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.938178 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.866265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.087562 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 17274 99.71% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 36 0.21% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 4 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::328-335 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17324 # Writes before turning the bus around for reads +system.physmem.totQLat 4037980750 # Total ticks spent queuing +system.physmem.totMemAccLat 11149855750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1896500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10645.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29397.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29395.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.48 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.55 # Average write queue length when enqueuing -system.physmem.readRowHits 314442 # Number of row buffer hits during reads -system.physmem.writeRowHits 215335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.60 # Row buffer hit rate for writes -system.physmem.avgGap 614513.57 # Average gap between requests -system.physmem.pageHitRate 78.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 549347400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299743125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1495252200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 953162640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62649847125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 193029983250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285972717660 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.908567 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 320566103500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13801320000 # Time in different power states +system.physmem.avgWrQLen 20.84 # Average write queue length when enqueuing +system.physmem.readRowHits 314187 # Number of row buffer hits during reads +system.physmem.writeRowHits 216366 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes +system.physmem.avgGap 613538.10 # Average gap between requests +system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 547268400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 298608750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1493302200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 955858320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62129952405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 193280474250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285678469605 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.770048 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320991140250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13789880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78943046000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78186381000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 527378040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 287755875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1466010000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 942483600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59502215925 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195791063250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 285512288610 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.794563 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 325183887500 # Time in different power states -system.physmem_1.memoryStateTime::REF 13801320000 # Time in different power states +system.physmem_1.actEnergy 527582160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 287867250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465152000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 945535680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59078125665 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195957550500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285234818535 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.695650 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 325462585000 # Time in different power states +system.physmem_1.memoryStateTime::REF 13789880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74324788750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73715009750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 124207419 # Number of BP lookups -system.cpu.branchPred.condPredicted 87899229 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6403012 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71682632 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67406446 # Number of BTB hits +system.cpu.branchPred.lookups 124207922 # Number of BP lookups +system.cpu.branchPred.condPredicted 87898525 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6402854 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71417252 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67405039 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.034558 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15055625 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126618 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.382012 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15056477 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126637 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149439695 # DTB read hits -system.cpu.dtb.read_misses 564071 # DTB read misses +system.cpu.dtb.read_hits 149440392 # DTB read hits +system.cpu.dtb.read_misses 563754 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150003766 # DTB read accesses -system.cpu.dtb.write_hits 57327469 # DTB write hits -system.cpu.dtb.write_misses 66798 # DTB write misses +system.cpu.dtb.read_accesses 150004146 # DTB read accesses +system.cpu.dtb.write_hits 57327101 # DTB write hits +system.cpu.dtb.write_misses 66835 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57394267 # DTB write accesses -system.cpu.dtb.data_hits 206767164 # DTB hits -system.cpu.dtb.data_misses 630869 # DTB misses +system.cpu.dtb.write_accesses 57393936 # DTB write accesses +system.cpu.dtb.data_hits 206767493 # DTB hits +system.cpu.dtb.data_misses 630589 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207398033 # DTB accesses -system.cpu.itb.fetch_hits 226566802 # ITB hits +system.cpu.dtb.data_accesses 207398082 # DTB accesses +system.cpu.itb.fetch_hits 226564860 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226566850 # ITB accesses +system.cpu.itb.fetch_accesses 226564908 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,82 +325,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 826622943 # number of cpu cycles simulated +system.cpu.numCycles 825936575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13262321 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13262650 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.350908 # CPI: cycles per instruction -system.cpu.ipc 0.740243 # IPC: instructions per cycle -system.cpu.tickCycles 740977624 # Number of cycles that the object actually ticked -system.cpu.idleCycles 85645319 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535493 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.640549 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202664153 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539589 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.801949 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1642835250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.640549 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997959 # Average percentage of cache occupancy +system.cpu.cpi 1.349787 # CPI: cycles per instruction +system.cpu.ipc 0.740858 # IPC: instructions per cycle +system.cpu.tickCycles 740975160 # Number of cycles that the object actually ticked +system.cpu.idleCycles 84961415 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535462 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.659006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202664910 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539558 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.803222 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1636438500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.659006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997964 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414772189 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414772189 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146997943 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146997943 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666210 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666210 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202664153 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202664153 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202664153 # number of overall hits -system.cpu.dcache.overall_hits::total 202664153 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543824 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543824 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452147 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452147 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452147 # number of overall misses -system.cpu.dcache.overall_misses::total 3452147 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37798959500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37798959500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48016494500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48016494500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 85815454000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 85815454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 85815454000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 85815454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148906266 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148906266 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414773666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414773666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146998717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146998717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666193 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666193 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202664910 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202664910 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202664910 # number of overall hits +system.cpu.dcache.overall_hits::total 202664910 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543841 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543841 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452144 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452144 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452144 # number of overall misses +system.cpu.dcache.overall_misses::total 3452144 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37694000500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37694000500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 47697864000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 47697864000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85391864500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85391864500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85391864500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85391864500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148907020 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148907020 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206116300 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206116300 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206116300 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206116300 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012816 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012816 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 206117054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206117054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206117054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206117054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012815 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016749 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016749 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016749 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016749 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.422276 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.422276 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31102.311209 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31102.311209 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24858.574678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24858.574678 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016748 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016748 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016748 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016748 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19752.628644 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19752.628644 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30895.580568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30895.580568 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.892970 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24735.892970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.892970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24735.892970 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,32 +409,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340079 # number of writebacks -system.cpu.dcache.writebacks::total 2340079 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143534 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143534 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769024 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769024 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912558 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912558 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912558 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912558 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764789 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764789 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774800 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774800 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539589 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539589 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539589 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539589 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32332751000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32332751000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23008045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23008045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55340796000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55340796000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55340796000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55340796000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2339794 # number of writebacks +system.cpu.dcache.writebacks::total 2339794 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769057 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769057 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912586 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912586 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764774 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774784 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774784 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539558 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539558 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539558 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539558 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33188844000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33188844000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23330038500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23330038500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56518882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56518882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56518882500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56518882500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011852 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011852 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -446,69 +443,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012321 system.cpu.dcache.demand_mshr_miss_rate::total 0.012321 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012321 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18321.029313 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18321.029313 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29695.463345 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29695.463345 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18806.285677 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18806.285677 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30111.667897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30111.667897 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22255.401334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22255.401334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22255.401334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22255.401334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3154 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.871500 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226561819 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4983 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45466.951435 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3160 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.196292 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226559871 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4989 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45411.880337 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.871500 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545836 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545836 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.196292 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545506 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1588 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453138587 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453138587 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226561819 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226561819 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226561819 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226561819 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 226561819 # number of overall hits -system.cpu.icache.overall_hits::total 226561819 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4983 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77298.839820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79489.546692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79474.127712 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,105 +645,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292564 # number of writebacks -system.cpu.l2cache.writebacks::total 292564 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096924 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265534 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265534 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149345 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149345 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65819.730438 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68314.464405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68276.035629 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66260.998345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66260.998345 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293459 # number of writebacks +system.cpu.l2cache.writebacks::total 293459 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 739 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 739 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206263 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206263 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2672 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2672 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170699 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170699 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12051969500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26194918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26374741000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179822500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26194918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26374741000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265073 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265073 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.535578 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.096910 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.096910 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148436 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149195 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148436 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149195 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68567.552106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68567.552106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67298.839820 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67298.839820 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70603.632710 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70603.632710 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67298.839820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69489.546692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.127712 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67298.839820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69489.546692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69474.127712 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340079 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778138 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778138 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9966 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312298752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312617664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1766410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2633253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 252293 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4989 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761421 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7627716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312278528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312597824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 346924 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5430093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.063889 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.244555 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884651 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5083169 93.61% 93.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 346924 6.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884651 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5430093 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4881378500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8026500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7483500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891673000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3809337000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173397 # Transaction distribution -system.membus.trans_dist::ReadResp 173397 # Transaction distribution -system.membus.trans_dist::Writeback 292564 # Transaction distribution -system.membus.trans_dist::ReadExReq 206622 # Transaction distribution -system.membus.trans_dist::ReadExResp 206622 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052602 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43045312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43045312 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 173371 # Transaction distribution +system.membus.trans_dist::Writeback 293459 # Transaction distribution +system.membus.trans_dist::CleanEvict 51814 # Transaction distribution +system.membus.trans_dist::ReadExReq 206263 # Transaction distribution +system.membus.trans_dist::ReadExResp 206263 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 173371 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1104541 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43077952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43077952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672583 # Request fanout histogram +system.membus.snoop_fanout::samples 724907 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 724907 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672583 # Request fanout histogram -system.membus.reqLayer0.occupancy 1984973000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 724907 # Request fanout histogram +system.membus.reqLayer0.occupancy 2020096000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2011061250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2009057000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 41f3b60e2..9049068c3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366030 # Number of seconds simulated -sim_ticks 366029674500 # Number of ticks simulated -final_tick 366029674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365934 # Number of seconds simulated +sim_ticks 365934171500 # Number of ticks simulated +final_tick 365934171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 241467 # Simulator instruction rate (inst/s) -host_op_rate 261540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174471263 # Simulator tick rate (ticks/s) -host_mem_usage 317880 # Number of bytes of host memory used -host_seconds 2097.94 # Real time elapsed on the host +host_inst_rate 236242 # Simulator instruction rate (inst/s) +host_op_rate 255881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170651382 # Simulator tick rate (ticks/s) +host_mem_usage 317968 # Number of bytes of host memory used +host_seconds 2144.34 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9008192 # Number of bytes read from this memory -system.physmem.bytes_read::total 9229632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6182144 # Number of bytes written to this memory -system.physmem.bytes_written::total 6182144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144213 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96596 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96596 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 604978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24610551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25215529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 604978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 604978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16889734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16889734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16889734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 604978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24610551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42105264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144213 # Number of read requests accepted -system.physmem.writeReqs 96596 # Number of write requests accepted -system.physmem.readBursts 144213 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96596 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9221696 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue -system.physmem.bytesWritten 6180992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9229632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6182144 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 218560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8996480 # Number of bytes read from this memory +system.physmem.bytes_read::total 9215040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6186432 # Number of bytes written to this memory +system.physmem.bytes_written::total 6186432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3415 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140570 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143985 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96663 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96663 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 597266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24584968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25182234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16905860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16905860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16905860 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24584968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42088095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143985 # Number of read requests accepted +system.physmem.writeReqs 96663 # Number of write requests accepted +system.physmem.readBursts 143985 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96663 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9208192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 6184704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9215040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6186432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9409 # Per bank write bursts -system.physmem.perBankRdBursts::1 9017 # Per bank write bursts -system.physmem.perBankRdBursts::2 8952 # Per bank write bursts -system.physmem.perBankRdBursts::3 8679 # Per bank write bursts +system.physmem.perBankRdBursts::0 9335 # Per bank write bursts +system.physmem.perBankRdBursts::1 8992 # Per bank write bursts +system.physmem.perBankRdBursts::2 8932 # Per bank write bursts +system.physmem.perBankRdBursts::3 8655 # Per bank write bursts system.physmem.perBankRdBursts::4 9455 # Per bank write bursts -system.physmem.perBankRdBursts::5 9348 # Per bank write bursts -system.physmem.perBankRdBursts::6 8942 # Per bank write bursts -system.physmem.perBankRdBursts::7 8103 # Per bank write bursts -system.physmem.perBankRdBursts::8 8564 # Per bank write bursts -system.physmem.perBankRdBursts::9 8678 # Per bank write bursts -system.physmem.perBankRdBursts::10 8771 # Per bank write bursts -system.physmem.perBankRdBursts::11 9482 # Per bank write bursts -system.physmem.perBankRdBursts::12 9373 # Per bank write bursts -system.physmem.perBankRdBursts::13 9523 # Per bank write bursts -system.physmem.perBankRdBursts::14 8716 # Per bank write bursts -system.physmem.perBankRdBursts::15 9077 # Per bank write bursts -system.physmem.perBankWrBursts::0 6225 # Per bank write bursts -system.physmem.perBankWrBursts::1 6098 # Per bank write bursts -system.physmem.perBankWrBursts::2 6004 # Per bank write bursts -system.physmem.perBankWrBursts::3 5808 # Per bank write bursts -system.physmem.perBankWrBursts::4 6164 # Per bank write bursts -system.physmem.perBankWrBursts::5 6178 # Per bank write bursts -system.physmem.perBankWrBursts::6 6016 # Per bank write bursts -system.physmem.perBankWrBursts::7 5497 # Per bank write bursts -system.physmem.perBankWrBursts::8 5725 # Per bank write bursts -system.physmem.perBankWrBursts::9 5821 # Per bank write bursts -system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6450 # Per bank write bursts -system.physmem.perBankWrBursts::12 6306 # Per bank write bursts -system.physmem.perBankWrBursts::13 6280 # Per bank write bursts -system.physmem.perBankWrBursts::14 5998 # Per bank write bursts -system.physmem.perBankWrBursts::15 6047 # Per bank write bursts +system.physmem.perBankRdBursts::5 9355 # Per bank write bursts +system.physmem.perBankRdBursts::6 8940 # Per bank write bursts +system.physmem.perBankRdBursts::7 8097 # Per bank write bursts +system.physmem.perBankRdBursts::8 8569 # Per bank write bursts +system.physmem.perBankRdBursts::9 8673 # Per bank write bursts +system.physmem.perBankRdBursts::10 8766 # Per bank write bursts +system.physmem.perBankRdBursts::11 9474 # Per bank write bursts +system.physmem.perBankRdBursts::12 9347 # Per bank write bursts +system.physmem.perBankRdBursts::13 9510 # Per bank write bursts +system.physmem.perBankRdBursts::14 8717 # Per bank write bursts +system.physmem.perBankRdBursts::15 9061 # Per bank write bursts +system.physmem.perBankWrBursts::0 6192 # Per bank write bursts +system.physmem.perBankWrBursts::1 6097 # Per bank write bursts +system.physmem.perBankWrBursts::2 6005 # Per bank write bursts +system.physmem.perBankWrBursts::3 5812 # Per bank write bursts +system.physmem.perBankWrBursts::4 6185 # Per bank write bursts +system.physmem.perBankWrBursts::5 6187 # Per bank write bursts +system.physmem.perBankWrBursts::6 6017 # Per bank write bursts +system.physmem.perBankWrBursts::7 5496 # Per bank write bursts +system.physmem.perBankWrBursts::8 5731 # Per bank write bursts +system.physmem.perBankWrBursts::9 5829 # Per bank write bursts +system.physmem.perBankWrBursts::10 5965 # Per bank write bursts +system.physmem.perBankWrBursts::11 6464 # Per bank write bursts +system.physmem.perBankWrBursts::12 6313 # Per bank write bursts +system.physmem.perBankWrBursts::13 6284 # Per bank write bursts +system.physmem.perBankWrBursts::14 6001 # Per bank write bursts +system.physmem.perBankWrBursts::15 6058 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366029646000 # Total gap between requests +system.physmem.totGap 365934145500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144213 # Read request sizes (log2) +system.physmem.readPktSize::6 143985 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96596 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96663 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,41 +144,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -193,112 +193,107 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.682213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.342104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.346143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24838 38.01% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18259 27.94% 65.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6996 10.71% 76.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7952 12.17% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2091 3.20% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1098 1.68% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 757 1.16% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 602 0.92% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2759 4.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65352 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.850018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.983730 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5570 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.897316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.545884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.443874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24707 37.87% 37.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18339 28.11% 65.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7015 10.75% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7835 12.01% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2110 3.23% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1145 1.75% 93.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 725 1.11% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 601 0.92% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2772 4.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65249 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.778176 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.924168 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5576 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5574 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.326516 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.224346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.427330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2648 47.51% 47.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2778 49.84% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 56 1.00% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 28 0.50% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 12 0.22% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 6 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 9 0.16% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 4 0.07% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 7 0.13% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5574 # Writes before turning the bus around for reads -system.physmem.totQLat 1545997750 # Total ticks spent queuing -system.physmem.totMemAccLat 4247666500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720445000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10729.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5581 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5581 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.315176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.217549 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.442698 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2634 47.20% 47.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2799 50.15% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 58 1.04% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 19 0.34% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 9 0.16% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 9 0.16% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::74-75 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-93 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5581 # Writes before turning the bus around for reads +system.physmem.totQLat 1559327000 # Total ticks spent queuing +system.physmem.totMemAccLat 4257039500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10837.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29479.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.89 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29587.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing -system.physmem.readRowHits 110923 # Number of row buffer hits during reads -system.physmem.writeRowHits 64387 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.66 # Row buffer hit rate for writes -system.physmem.avgGap 1519999.86 # Average gap between requests -system.physmem.pageHitRate 72.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248708880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135704250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560640600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310761360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47751629445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177727049250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250641390825 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.767505 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295355626000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12222340000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.48 # Average write queue length when enqueuing +system.physmem.readRowHits 110804 # Number of row buffer hits during reads +system.physmem.writeRowHits 64456 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.68 # Row buffer hit rate for writes +system.physmem.avgGap 1520619.93 # Average gap between requests +system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248300640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135481500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 559572000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310819680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47511748935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 177881418000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250548135075 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.687479 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 295615195000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12219220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58446120250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58096250000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245064960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133716000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562816800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314753040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47056905180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178336456500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250556609520 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.535877 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296372694500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12222340000 # Time in different power states +system.physmem_1.actEnergy 244785240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133563375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562356600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315174240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46698412230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178594871250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250449957255 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.419183 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296806540250 # Time in different power states +system.physmem_1.memoryStateTime::REF 12219220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57429294500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 56906569250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132485545 # Number of BP lookups -system.cpu.branchPred.condPredicted 98435425 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6553959 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68727443 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64816198 # Number of BTB hits +system.cpu.branchPred.lookups 132492243 # Number of BP lookups +system.cpu.branchPred.condPredicted 98438822 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6555205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68897926 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64816869 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.309049 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10006764 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17617 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.076662 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10008233 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17907 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,98 +412,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 732059349 # number of cpu cycles simulated +system.cpu.numCycles 731868343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13911652 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13915585 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.445095 # CPI: cycles per instruction -system.cpu.ipc 0.691996 # IPC: instructions per cycle -system.cpu.tickCycles 695000552 # Number of cycles that the object actually ticked -system.cpu.idleCycles 37058797 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139856 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.933719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171285318 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143952 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.731211 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.933719 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993880 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy +system.cpu.cpi 1.444718 # CPI: cycles per instruction +system.cpu.ipc 0.692177 # IPC: instructions per cycle +system.cpu.tickCycles 695013398 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36854945 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139741 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.950270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171285752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143837 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.746644 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4896340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.950270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993884 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993884 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3503 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346825504 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346825504 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114766819 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114766819 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538648 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538648 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2769 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2769 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346825855 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346825855 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114767186 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114767186 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538711 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538711 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168305467 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168305467 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168308236 # number of overall hits -system.cpu.dcache.overall_hits::total 168308236 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854784 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854784 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700658 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700658 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555442 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555442 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555458 # number of overall misses -system.cpu.dcache.overall_misses::total 1555458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14034932732 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14034932732 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22036201250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22036201250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36071133982 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36071133982 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36071133982 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36071133982 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115621603 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115621603 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168305897 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168305897 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168308670 # number of overall hits +system.cpu.dcache.overall_hits::total 168308670 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854648 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854648 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700595 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700595 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 14 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 14 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555243 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555243 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555257 # number of overall misses +system.cpu.dcache.overall_misses::total 1555257 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022869000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14022869000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21909880500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21909880500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35932749500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35932749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35932749500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35932749500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115621834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115621834 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2785 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2785 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2787 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2787 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169860909 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169860909 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169863694 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169863694 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005745 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005745 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16419.274029 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16419.274029 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31450.723820 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31450.723820 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23190.279022 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23190.279022 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23190.040478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23190.040478 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 169861140 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169861140 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169863927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169863927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005023 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005023 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009156 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009156 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16407.771387 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16407.771387 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31273.247026 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31273.247026 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23104.266986 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23104.266986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23104.059008 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23104.059008 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,111 +512,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068580 # number of writebacks -system.cpu.dcache.writebacks::total 1068580 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67006 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 67006 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344497 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344497 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411503 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411503 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411503 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411503 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787778 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787778 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356161 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356161 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143939 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143939 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143952 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143952 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11938933765 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11938933765 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970217000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970217000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1208500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1208500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22909150765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22909150765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22910359265 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22910359265 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1068492 # number of writebacks +system.cpu.dcache.writebacks::total 1068492 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66944 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66944 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344474 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344474 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787704 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356121 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356121 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143825 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143825 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143837 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143837 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12336256500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12336256500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11129164500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11129164500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1374500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1374500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23465421000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23465421000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23466795500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23466795500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004668 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004668 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15155.200786 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15155.200786 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30801.286497 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30801.286497 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 92961.538462 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92961.538462 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20026.549287 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20026.549287 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20027.378129 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20027.378129 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004306 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004306 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15661.030666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15661.030666 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31251.076179 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31251.076179 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 114541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 114541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20514.869845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20514.869845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20515.856280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20515.856280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17693 # number of replacements -system.cpu.icache.tags.tagsinuse 1189.692945 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200785966 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19565 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10262.507846 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17695 # number of replacements +system.cpu.icache.tags.tagsinuse 1189.845505 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200793682 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19567 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10261.853222 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1189.692945 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580905 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1189.845505 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580979 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580979 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1410 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1411 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401630627 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401630627 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200785966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200785966 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200785966 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200785966 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200785966 # number of overall hits -system.cpu.icache.overall_hits::total 200785966 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19565 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19565 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19565 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19565 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19565 # number of overall misses -system.cpu.icache.overall_misses::total 19565 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 492369746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 492369746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 492369746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 492369746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 492369746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 492369746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200805531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200805531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200805531 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200805531 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200805531 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200805531 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 401646065 # Number of tag accesses +system.cpu.icache.tags.data_accesses 401646065 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200793682 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200793682 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200793682 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200793682 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200793682 # number of overall hits +system.cpu.icache.overall_hits::total 200793682 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19567 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19567 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19567 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19567 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19567 # number of overall misses +system.cpu.icache.overall_misses::total 19567 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 488802000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 488802000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 488802000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 488802000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 488802000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 488802000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200813249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200813249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200813249 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200813249 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200813249 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200813249 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79095.697981 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79095.697981 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82629.299507 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82629.299507 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79095.697981 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79670.007469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79656.379773 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79095.697981 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79670.007469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79656.379773 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,114 +755,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96596 # number of writebacks -system.cpu.l2cache.writebacks::total 96596 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 96663 # number of writebacks +system.cpu.l2cache.writebacks::total 96663 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39847 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43307 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100906 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100906 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144213 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144213 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229496250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2794594500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3024090750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6671817000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6671817000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229496250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9466411500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9695907750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229496250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9466411500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9695907750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283115 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283115 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123946 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123946 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66328.395954 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70133.121690 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69829.144249 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66119.130676 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66119.130676 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1183 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1183 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100813 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100813 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3415 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3415 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39757 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39757 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3415 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 143985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3415 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 143985 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6905945500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6905945500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 235984000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 235984000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2887628500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2887628500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 235984000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9793574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10029558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 235984000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9793574000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10029558000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174529 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050487 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050487 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122893 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123762 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122893 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123762 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68502.529436 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68502.529436 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69102.196193 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69102.196193 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72631.951606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72631.951606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69102.196193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69670.441773 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69656.964267 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69102.196193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69670.441773 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69656.964267 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068580 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356414 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141602048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142854208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 807030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1165155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787463 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3422797 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3479390 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142841344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 111231 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2432071 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.045735 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.208910 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2232097 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2320840 95.43% 95.43% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 111231 4.57% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232097 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184628500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2432071 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2228912000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30040746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29351498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744732235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1715762985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43307 # Transaction distribution -system.membus.trans_dist::ReadResp 43307 # Transaction distribution -system.membus.trans_dist::Writeback 96596 # Transaction distribution -system.membus.trans_dist::ReadExReq 100906 # Transaction distribution -system.membus.trans_dist::ReadExResp 100906 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385022 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15411776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15411776 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 43172 # Transaction distribution +system.membus.trans_dist::Writeback 96663 # Transaction distribution +system.membus.trans_dist::CleanEvict 13165 # Transaction distribution +system.membus.trans_dist::ReadExReq 100813 # Transaction distribution +system.membus.trans_dist::ReadExResp 100813 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43172 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397798 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15401472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15401472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240809 # Request fanout histogram +system.membus.snoop_fanout::samples 253813 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240809 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253813 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240809 # Request fanout histogram -system.membus.reqLayer0.occupancy 679106500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 253813 # Request fanout histogram +system.membus.reqLayer0.occupancy 683218000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765494750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 764295250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 12498d68b..7cef0aacd 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233457 # Number of seconds simulated -sim_ticks 233457400500 # Number of ticks simulated -final_tick 233457400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233283 # Number of seconds simulated +sim_ticks 233282768000 # Number of ticks simulated +final_tick 233282768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140578 # Simulator instruction rate (inst/s) -host_op_rate 152296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64957541 # Simulator tick rate (ticks/s) -host_mem_usage 319412 # Number of bytes of host memory used -host_seconds 3594.00 # Real time elapsed on the host +host_inst_rate 136250 # Simulator instruction rate (inst/s) +host_op_rate 147606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62910352 # Simulator tick rate (ticks/s) +host_mem_usage 320784 # Number of bytes of host memory used +host_seconds 3708.18 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 691264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9218304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16465984 # Number of bytes read from this memory -system.physmem.bytes_read::total 26375552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 691264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 691264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18705216 # Number of bytes written to this memory -system.physmem.bytes_written::total 18705216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10801 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257281 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412118 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292269 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292269 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2960986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39486022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70531000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 112978008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2960986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2960986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80122609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80122609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80122609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2960986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39486022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70531000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193100617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412118 # Number of read requests accepted -system.physmem.writeReqs 292269 # Number of write requests accepted -system.physmem.readBursts 412118 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292269 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26236672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 138880 # Total number of bytes read from write queue -system.physmem.bytesWritten 18703040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26375552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18705216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2170 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 683136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9221056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16463744 # Number of bytes read from this memory +system.physmem.bytes_read::total 26367936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 683136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 683136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18705728 # Number of bytes written to this memory +system.physmem.bytes_written::total 18705728 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10674 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144079 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257246 # Number of read requests responded to by this memory +system.physmem.num_reads::total 411999 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292277 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292277 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2928360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39527377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70574197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 113029935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2928360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2928360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80184782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80184782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80184782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2928360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39527377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70574197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193214717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411999 # Number of read requests accepted +system.physmem.writeReqs 292277 # Number of write requests accepted +system.physmem.readBursts 411999 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292277 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26229824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 138112 # Total number of bytes read from write queue +system.physmem.bytesWritten 18703872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26367936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18705728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2158 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26483 # Per bank write bursts -system.physmem.perBankRdBursts::1 25520 # Per bank write bursts -system.physmem.perBankRdBursts::2 25375 # Per bank write bursts -system.physmem.perBankRdBursts::3 24791 # Per bank write bursts -system.physmem.perBankRdBursts::4 27157 # Per bank write bursts -system.physmem.perBankRdBursts::5 26569 # Per bank write bursts -system.physmem.perBankRdBursts::6 25228 # Per bank write bursts -system.physmem.perBankRdBursts::7 24398 # Per bank write bursts -system.physmem.perBankRdBursts::8 25772 # Per bank write bursts -system.physmem.perBankRdBursts::9 24727 # Per bank write bursts -system.physmem.perBankRdBursts::10 25014 # Per bank write bursts -system.physmem.perBankRdBursts::11 25991 # Per bank write bursts -system.physmem.perBankRdBursts::12 26422 # Per bank write bursts -system.physmem.perBankRdBursts::13 25825 # Per bank write bursts -system.physmem.perBankRdBursts::14 25184 # Per bank write bursts -system.physmem.perBankRdBursts::15 25492 # Per bank write bursts -system.physmem.perBankWrBursts::0 18766 # Per bank write bursts -system.physmem.perBankWrBursts::1 18282 # Per bank write bursts -system.physmem.perBankWrBursts::2 18016 # Per bank write bursts -system.physmem.perBankWrBursts::3 18022 # Per bank write bursts -system.physmem.perBankWrBursts::4 18772 # Per bank write bursts -system.physmem.perBankWrBursts::5 18348 # Per bank write bursts -system.physmem.perBankWrBursts::6 17902 # Per bank write bursts -system.physmem.perBankWrBursts::7 17779 # Per bank write bursts -system.physmem.perBankWrBursts::8 18029 # Per bank write bursts -system.physmem.perBankWrBursts::9 17785 # Per bank write bursts -system.physmem.perBankWrBursts::10 18061 # Per bank write bursts -system.physmem.perBankWrBursts::11 18677 # Per bank write bursts -system.physmem.perBankWrBursts::12 18741 # Per bank write bursts -system.physmem.perBankWrBursts::13 18309 # Per bank write bursts -system.physmem.perBankWrBursts::14 18406 # Per bank write bursts -system.physmem.perBankWrBursts::15 18340 # Per bank write bursts +system.physmem.perBankRdBursts::0 26728 # Per bank write bursts +system.physmem.perBankRdBursts::1 25477 # Per bank write bursts +system.physmem.perBankRdBursts::2 25253 # Per bank write bursts +system.physmem.perBankRdBursts::3 24678 # Per bank write bursts +system.physmem.perBankRdBursts::4 27151 # Per bank write bursts +system.physmem.perBankRdBursts::5 26546 # Per bank write bursts +system.physmem.perBankRdBursts::6 25195 # Per bank write bursts +system.physmem.perBankRdBursts::7 24195 # Per bank write bursts +system.physmem.perBankRdBursts::8 25840 # Per bank write bursts +system.physmem.perBankRdBursts::9 24882 # Per bank write bursts +system.physmem.perBankRdBursts::10 24886 # Per bank write bursts +system.physmem.perBankRdBursts::11 26093 # Per bank write bursts +system.physmem.perBankRdBursts::12 26302 # Per bank write bursts +system.physmem.perBankRdBursts::13 26067 # Per bank write bursts +system.physmem.perBankRdBursts::14 24895 # Per bank write bursts +system.physmem.perBankRdBursts::15 25653 # Per bank write bursts +system.physmem.perBankWrBursts::0 18973 # Per bank write bursts +system.physmem.perBankWrBursts::1 18287 # Per bank write bursts +system.physmem.perBankWrBursts::2 17868 # Per bank write bursts +system.physmem.perBankWrBursts::3 17935 # Per bank write bursts +system.physmem.perBankWrBursts::4 18795 # Per bank write bursts +system.physmem.perBankWrBursts::5 18319 # Per bank write bursts +system.physmem.perBankWrBursts::6 17931 # Per bank write bursts +system.physmem.perBankWrBursts::7 17655 # Per bank write bursts +system.physmem.perBankWrBursts::8 18179 # Per bank write bursts +system.physmem.perBankWrBursts::9 17927 # Per bank write bursts +system.physmem.perBankWrBursts::10 17987 # Per bank write bursts +system.physmem.perBankWrBursts::11 18662 # Per bank write bursts +system.physmem.perBankWrBursts::12 18697 # Per bank write bursts +system.physmem.perBankWrBursts::13 18344 # Per bank write bursts +system.physmem.perBankWrBursts::14 18231 # Per bank write bursts +system.physmem.perBankWrBursts::15 18458 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233457328000 # Total gap between requests +system.physmem.totGap 233282750000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412118 # Read request sizes (log2) +system.physmem.readPktSize::6 411999 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292269 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 312558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292277 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 312898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -197,101 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 306919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.415804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.989110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 182.052610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 184181 60.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81968 26.71% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16622 5.42% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7343 2.39% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4784 1.56% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2292 0.75% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1776 0.58% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1536 0.50% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 306919 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.626628 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.525366 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17349 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 306889 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.413224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.997180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.093051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184151 60.01% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 82036 26.73% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16582 5.40% 92.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7394 2.41% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4756 1.55% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2254 0.73% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1661 0.54% 97.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1625 0.53% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6430 2.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 306889 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.673001 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.829793 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17311 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17350 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.843516 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.802727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.214220 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10753 61.98% 61.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 289 1.67% 63.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5387 31.05% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 614 3.54% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 106 0.61% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 63 0.36% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 46 0.27% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 45 0.26% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 29 0.17% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17350 # Writes before turning the bus around for reads -system.physmem.totQLat 9548241731 # Total ticks spent queuing -system.physmem.totMemAccLat 17234766731 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2049740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23291.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17312 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.881238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.838780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.240848 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10485 60.56% 60.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 306 1.77% 62.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5502 31.78% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 671 3.88% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 134 0.77% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 74 0.43% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 42 0.24% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 45 0.26% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.17% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17312 # Writes before turning the bus around for reads +system.physmem.totQLat 9036310212 # Total ticks spent queuing +system.physmem.totMemAccLat 16720828962 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22048.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42041.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 112.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 112.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40798.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 113.03 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing -system.physmem.readRowHits 299652 # Number of row buffer hits during reads -system.physmem.writeRowHits 95604 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.71 # Row buffer hit rate for writes -system.physmem.avgGap 331433.33 # Average gap between requests +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.78 # Average write queue length when enqueuing +system.physmem.readRowHits 299552 # Number of row buffer hits during reads +system.physmem.writeRowHits 95641 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes +system.physmem.avgGap 331237.68 # Average gap between requests system.physmem.pageHitRate 56.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1157927400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 631805625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1602907800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 945308880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15248154480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75190255245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74116872000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 168893231430 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.449687 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122769601530 # Time in different power states -system.physmem_0.memoryStateTime::REF 7795580000 # Time in different power states +system.physmem_0.actEnergy 1156763160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 631170375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1600435200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 944401680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74473770375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74637909000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168680907390 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.094931 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123643637069 # Time in different power states +system.physmem_0.memoryStateTime::REF 7789600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 102890225970 # Time in different power states +system.physmem_0.memoryStateTime::ACT 101845250931 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1162259280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 634169250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1594382400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 948263760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15248154480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74130386985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75046581000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 168764197155 # Total energy per rank (pJ) -system.physmem_1.averagePower 722.896972 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 124323822632 # Time in different power states -system.physmem_1.memoryStateTime::REF 7795580000 # Time in different power states +system.physmem_1.actEnergy 1163007720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 634577625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1595802000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 949158000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74040443550 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75018020250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168637466745 # Total energy per rank (pJ) +system.physmem_1.averagePower 722.908711 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124281047938 # Time in different power states +system.physmem_1.memoryStateTime::REF 7789600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101336607368 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101208398062 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175097732 # Number of BP lookups -system.cpu.branchPred.condPredicted 131341907 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444118 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90491460 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83879546 # Number of BTB hits +system.cpu.branchPred.lookups 175089811 # Number of BP lookups +system.cpu.branchPred.condPredicted 131337021 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444155 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90376647 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83876100 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.693328 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12111412 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104155 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.807271 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12110019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104160 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -410,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466914802 # number of cpu cycles simulated +system.cpu.numCycles 466565537 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7831702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731836126 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175097732 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95990958 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450721779 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14940955 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13551 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236729658 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34605 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 466043328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.700638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7838065 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731795546 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175089811 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95986119 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450385778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14940817 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14677 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236716672 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34578 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465715008 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179403 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94098707 20.19% 20.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132700679 28.47% 48.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57861600 12.42% 61.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181382342 38.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93791115 20.14% 20.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132693411 28.49% 48.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57855471 12.42% 61.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181375011 38.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 466043328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.375010 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.567387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32400238 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117626282 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 286962359 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22072426 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982023 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24050963 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496269 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715816443 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29997814 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982023 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63475472 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54498348 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40339589 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276580199 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24167697 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686605984 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13334781 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9429797 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386503 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1670701 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1903283 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831017415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019232506 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723934620 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465715008 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375274 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.568473 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32367511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117249871 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287084329 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22031549 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6981748 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24050134 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496459 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715800999 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30008433 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6981748 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63425626 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54212557 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40336788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276681526 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24076763 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686589929 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13340569 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9410638 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2384158 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1669115 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1841927 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831018421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019159141 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723918647 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176893664 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544707 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534925 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42378773 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143528821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67986057 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12870746 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11400164 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668175203 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610240343 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5850286 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123802591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319329527 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 466043328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309407 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101734 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176894670 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544698 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534992 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42289780 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143526215 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67981217 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12855514 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11197113 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668159255 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978326 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610231748 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5860169 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123786636 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319274742 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465715008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.310312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148928880 31.96% 31.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101192205 21.71% 53.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145640431 31.25% 84.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63360456 13.60% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6920872 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 484 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148574576 31.90% 31.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101171602 21.72% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145766544 31.30% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63282576 13.59% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6919220 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 490 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 466043328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465715008 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71964986 53.01% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44551194 32.82% 85.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19229314 14.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71921517 52.96% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44556516 32.81% 85.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19328890 14.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413153889 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351748 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413144323 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351745 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -560,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134217118 21.99% 89.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62517585 10.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134209580 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62526097 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610240343 # Type of FU issued -system.cpu.iq.rate 1.306963 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135745524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222446 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1828119531 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 794984388 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594979068 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610231748 # Type of FU issued +system.cpu.iq.rate 1.307923 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135806953 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222550 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1827845333 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 794952356 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594966802 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745985690 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746038524 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7282878 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7273046 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27644065 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25657 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28996 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11125580 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27641459 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25471 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28891 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11120740 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225352 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19393 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225190 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22470 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982023 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23078591 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 913703 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672641346 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6981748 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23001930 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 919984 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672625014 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143528821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67986057 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 257861 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 519542 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28996 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822175 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7553447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599393385 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129576774 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10846958 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143526215 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67981217 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489784 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258650 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 525178 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28891 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821630 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731398 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7553028 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599382547 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129570228 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10849201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487810 # number of nop insts executed -system.cpu.iew.exec_refs 190521112 # number of memory reference insts executed -system.cpu.iew.exec_branches 131377011 # Number of branches executed -system.cpu.iew.exec_stores 60944338 # Number of stores executed -system.cpu.iew.exec_rate 1.283732 # Inst execution rate -system.cpu.iew.wb_sent 596274130 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594979084 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349911288 # num instructions producing a value -system.cpu.iew.wb_consumers 570684699 # num instructions consuming a value +system.cpu.iew.exec_nop 1487433 # number of nop insts executed +system.cpu.iew.exec_refs 190523509 # number of memory reference insts executed +system.cpu.iew.exec_branches 131370037 # Number of branches executed +system.cpu.iew.exec_stores 60953281 # Number of stores executed +system.cpu.iew.exec_rate 1.284670 # Inst execution rate +system.cpu.iew.wb_sent 596261681 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594966818 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349901968 # num instructions producing a value +system.cpu.iew.wb_consumers 570648646 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.274278 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613143 # average fanout of values written-back +system.cpu.iew.wb_rate 1.275205 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110037784 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110016162 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6955664 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448925828 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.222239 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.888253 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6955495 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448601420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.223123 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.887905 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219983984 49.00% 49.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116251312 25.90% 74.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43736792 9.74% 84.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23204110 5.17% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11645207 2.59% 92.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7768175 1.73% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8255090 1.84% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4243904 0.95% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13837254 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219539851 48.94% 48.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116349885 25.94% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43748468 9.75% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23302371 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11552802 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7777273 1.73% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8275373 1.84% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4252092 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13803305 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448925828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448601420 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -683,380 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13837254 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1093814049 # The number of ROB reads -system.cpu.rob.rob_writes 1334612597 # The number of ROB writes -system.cpu.timesIdled 13893 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 871474 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13803305 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1093501968 # The number of ROB reads +system.cpu.rob.rob_writes 1334565325 # The number of ROB writes +system.cpu.timesIdled 13884 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850529 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.924149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.924149 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082077 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082077 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611066187 # number of integer regfile reads -system.cpu.int_regfile_writes 328122868 # number of integer regfile writes +system.cpu.cpi 0.923457 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923457 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082887 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082887 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611072880 # number of integer regfile reads +system.cpu.int_regfile_writes 328111730 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170174557 # number of cc regfile reads -system.cpu.cc_regfile_writes 376546263 # number of cc regfile writes -system.cpu.misc_regfile_reads 217961585 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170116632 # number of cc regfile reads +system.cpu.cc_regfile_writes 376537008 # number of cc regfile writes +system.cpu.misc_regfile_reads 217962216 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2821455 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.631544 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169406374 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821967 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.031309 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 498452500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.631544 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999280 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2820796 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.631791 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169351038 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821308 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.025718 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498038000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.631791 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356233951 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356233951 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114665404 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114665404 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51761034 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51761034 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 356237372 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356237372 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114646487 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114646487 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724617 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724617 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166426438 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166426438 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166429221 # number of overall hits -system.cpu.dcache.overall_hits::total 166429221 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4821321 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4821321 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2478272 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2478272 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166371104 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166371104 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166373887 # number of overall hits +system.cpu.dcache.overall_hits::total 166373887 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4842277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4842277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2514689 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2514689 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7299593 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7299593 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7299605 # number of overall misses -system.cpu.dcache.overall_misses::total 7299605 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56428314397 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56428314397 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18848897160 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18848897160 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1043750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1043750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75277211557 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75277211557 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75277211557 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75277211557 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119486725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119486725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7356966 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7356966 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7356978 # number of overall misses +system.cpu.dcache.overall_misses::total 7356978 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56244825000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56244825000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18846227941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18846227941 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1242500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1242500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75091052941 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75091052941 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75091052941 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75091052941 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119488764 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119488764 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173726031 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173726031 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173728826 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173728826 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040350 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040350 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045691 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045691 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173728070 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173728070 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173730865 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173730865 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040525 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040525 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046363 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046363 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042018 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042018 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042017 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042017 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11703.911521 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11703.911521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7605.661187 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7605.661187 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15814.393939 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15814.393939 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10312.521747 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10312.521747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10312.504794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10312.504794 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 711137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 220355 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 3.227233 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042347 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042347 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11615.367109 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11615.367109 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7494.456746 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7494.456746 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18825.757576 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18825.757576 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10206.796245 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10206.796245 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10206.779596 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10206.779596 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 911242 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221024 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.122819 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2352760 # number of writebacks -system.cpu.dcache.writebacks::total 2352760 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2518936 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2518936 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958671 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1958671 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2356243 # number of writebacks +system.cpu.dcache.writebacks::total 2356243 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540565 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540565 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995076 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995076 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4477607 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4477607 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4477607 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4477607 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302385 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2302385 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519601 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519601 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4535641 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4535641 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4535641 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4535641 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301712 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301712 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519613 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519613 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821986 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821986 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821996 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821996 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27643726875 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27643726875 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325979851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325979851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 667500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 667500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31969706726 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31969706726 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31970374226 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31970374226 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019269 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019269 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2821325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821325 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821335 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821335 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28710026000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28710026000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4575255494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4575255494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 657000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 657000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33285281494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33285281494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33285938494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33285938494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016244 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016244 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016244 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016244 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12006.561403 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12006.561403 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8325.580303 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8325.580303 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11328.797069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11328.797069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11328.993459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11328.993459 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12473.335500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12473.335500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8805.121300 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8805.121300 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65700 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65700 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.748042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.748042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.939094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.939094 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73478 # number of replacements -system.cpu.icache.tags.tagsinuse 466.210203 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236647479 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73990 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3198.371118 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115019212250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.210203 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910567 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910567 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73477 # number of replacements +system.cpu.icache.tags.tagsinuse 466.193561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236634038 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73989 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.232683 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114977932500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.193561 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910534 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910534 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473533098 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473533098 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236647479 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236647479 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236647479 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236647479 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236647479 # number of overall hits -system.cpu.icache.overall_hits::total 236647479 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 82060 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 82060 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 82060 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 82060 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 82060 # number of overall misses -system.cpu.icache.overall_misses::total 82060 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1575366023 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1575366023 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1575366023 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1575366023 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1575366023 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1575366023 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236729539 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236729539 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236729539 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236729539 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236729539 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236729539 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000347 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000347 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000347 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000347 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000347 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000347 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19197.733646 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19197.733646 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19197.733646 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19197.733646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19197.733646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19197.733646 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 189178 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 92 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6697 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 473507120 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473507120 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236634038 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236634038 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236634038 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236634038 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236634038 # number of overall hits +system.cpu.icache.overall_hits::total 236634038 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 82514 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 82514 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 82514 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 82514 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 82514 # number of overall misses +system.cpu.icache.overall_misses::total 82514 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1544948153 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1544948153 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1544948153 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1544948153 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1544948153 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1544948153 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236716552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236716552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236716552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236716552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236716552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236716552 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18723.466963 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18723.466963 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18723.466963 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18723.466963 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 193180 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6947 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.248171 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.807687 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8039 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8039 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8039 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8039 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8039 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8039 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74021 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 74021 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 74021 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 74021 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 74021 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 74021 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1246042756 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1246042756 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1246042756 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1246042756 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1246042756 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1246042756 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8497 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8497 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8497 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8497 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8497 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8497 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74017 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74017 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74017 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74017 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74017 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74017 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1266772756 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1266772756 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1266772756 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1266772756 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1266772756 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1266772756 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16833.638508 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16833.638508 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16833.638508 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16833.638508 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16833.638508 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16833.638508 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.619020 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17114.619020 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513000 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8515433 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 981 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8510429 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8512950 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 1055 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743879 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 401084 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15418.862546 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4557178 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417421 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.917462 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 34596581000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8463.110256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 474.072074 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4920.608759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1561.071458 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.516547 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028935 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.300330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095280 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15284 # Occupied blocks per task id +system.cpu.l2cache.prefetcher.pfSpanPage 742850 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 400878 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15418.113154 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5066482 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 417216 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.143547 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 34592827000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8451.219479 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 476.205325 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4934.937237 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1555.751112 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063682 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3676 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3676 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 140404 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 140404 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10675 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144080 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144080 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 274923 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 429678 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19117391245 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19117391245 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 33000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 33000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 289648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 289648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 715179500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 715179500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9979387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9979387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 715179500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10269035500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10984215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 715179500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10269035500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19117391245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30101606245 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.068966 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.068966 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007001 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007001 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145999 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051041 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053467 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145999 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051041 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007043 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007043 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144288 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.061063 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.061063 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053451 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148473 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65243.179133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68982.369582 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68715.208586 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69036.048362 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78076.288451 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78076.288451 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65243.179133 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69213.068496 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68936.117955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65243.179133 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69213.068496 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69000.061925 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148406 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2374087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2374086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2352760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317092 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521901 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521901 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148007 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996752 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8144759 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4735104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331182528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 335917632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 317126 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5565869 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.056971 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.231787 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 2373352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2648520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 622852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 320716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 74017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299336 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440541 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8661164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331363264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336098176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 721627 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6511219 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.110823 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.313913 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5248777 94.30% 94.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 317092 5.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5789625 88.92% 88.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 721594 11.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5565869 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4977148500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 112866029 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6511219 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5251055500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111049948 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4256213768 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4231992466 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 408465 # Transaction distribution -system.membus.trans_dist::ReadResp 408465 # Transaction distribution -system.membus.trans_dist::Writeback 292269 # Transaction distribution +system.membus.trans_dist::ReadResp 408324 # Transaction distribution +system.membus.trans_dist::Writeback 292277 # Transaction distribution +system.membus.trans_dist::CleanEvict 103036 # Transaction distribution system.membus.trans_dist::UpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3653 # Transaction distribution -system.membus.trans_dist::ReadExResp 3653 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116511 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1116511 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45080768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45080768 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3675 # Transaction distribution +system.membus.trans_dist::ReadExResp 3675 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 408324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219317 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1219317 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45073664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45073664 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 704390 # Request fanout histogram +system.membus.snoop_fanout::samples 807315 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 704390 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 807315 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 704390 # Request fanout histogram -system.membus.reqLayer0.occupancy 2099926272 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 807315 # Request fanout histogram +system.membus.reqLayer0.occupancy 2175050688 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178828981 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2177979128 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 5ab6bd474..7568a8b98 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707538 # Number of seconds simulated -sim_ticks 707538047500 # Number of ticks simulated -final_tick 707538047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707533 # Number of seconds simulated +sim_ticks 707533448500 # Number of ticks simulated +final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 813114 # Simulator instruction rate (inst/s) -host_op_rate 880566 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1139256199 # Simulator tick rate (ticks/s) -host_mem_usage 308656 # Number of bytes of host memory used -host_seconds 621.05 # Real time elapsed on the host +host_inst_rate 1147583 # Simulator instruction rate (inst/s) +host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1607870578 # Simulator tick rate (ticks/s) +host_mem_usage 316160 # Number of bytes of host memory used +host_seconds 440.04 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 177216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8952320 # Number of bytes read from this memory -system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 177216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 177216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory -system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139880 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory -system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 250469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12652775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 250469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 250469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 250469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12652775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 175360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8946752 # Number of bytes read from this memory +system.physmem.bytes_read::total 9122112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 175360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 175360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6146048 # Number of bytes written to this memory +system.physmem.bytes_written::total 6146048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139793 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415076095 # number of cpu cycles simulated +system.cpu.numCycles 1415066897 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986854 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415076094.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548302 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318385 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318385 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818699500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11818699500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20687471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20687471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20687471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20687471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.160777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.144829 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks -system.cpu.dcache.writebacks::total 1064905 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1064880 # number of writebacks +system.cpu.dcache.writebacks::total 1064880 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644714000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644714000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18979096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979149500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18979149500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.739532 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.739532 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.160777 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.160777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.193120 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.372130 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.372130 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266251500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266251500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266251500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266251500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266251500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266251500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23110.103290 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23110.103290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23110.103290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23110.103290 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,116 +415,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 248970000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 248970000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 248970000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 248970000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 248970000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 248970000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21610.103290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21610.103290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.388101 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338494305500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.672992 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.725951 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008779 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 109779 # 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number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 96032 # number of writebacks +system.cpu.l2cache.writebacks::total 96032 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 792 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 792 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39060 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39060 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2740 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 139793 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 142533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2740 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 139793 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142533 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237827 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.049907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.049907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123894 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123894 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141043072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 109779 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 41855 # Transaction distribution -system.membus.trans_dist::ReadResp 41855 # Transaction distribution -system.membus.trans_dist::Writeback 95953 # Transaction distribution -system.membus.trans_dist::ReadExReq 100794 # Transaction distribution -system.membus.trans_dist::ReadExResp 100794 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 41800 # Transaction distribution +system.membus.trans_dist::Writeback 96032 # Transaction distribution +system.membus.trans_dist::CleanEvict 12399 # Transaction distribution +system.membus.trans_dist::ReadExReq 100733 # Transaction distribution +system.membus.trans_dist::ReadExResp 100733 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41800 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393497 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 393497 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15268160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15268160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 238603 # Request fanout histogram +system.membus.snoop_fanout::samples 251058 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 251058 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 251058 # Request fanout histogram +system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 3384a1591..2dc4a1c77 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417996 # Number of seconds simulated -sim_ticks 417996021500 # Number of ticks simulated -final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417249 # Number of seconds simulated +sim_ticks 417248608500 # Number of ticks simulated +final_tick 417248608500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98610 # Simulator instruction rate (inst/s) -host_op_rate 182341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49848381 # Simulator tick rate (ticks/s) -host_mem_usage 430328 # Number of bytes of host memory used -host_seconds 8385.35 # Real time elapsed on the host +host_inst_rate 95567 # Simulator instruction rate (inst/s) +host_op_rate 176715 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48224052 # Simulator tick rate (ticks/s) +host_mem_usage 428536 # Number of bytes of host memory used +host_seconds 8652.29 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory -system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386930 # Number of read requests accepted -system.physmem.writeReqs 294035 # Number of write requests accepted -system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue -system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 222784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24527040 # Number of bytes read from this memory +system.physmem.bytes_read::total 24749824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18883520 # Number of bytes written to this memory +system.physmem.bytes_written::total 18883520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3481 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383235 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386716 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 533936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58782796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59316732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 533936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 533936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45257239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45257239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45257239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 533936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58782796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104573971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386716 # Number of read requests accepted +system.physmem.writeReqs 295055 # Number of write requests accepted +system.physmem.readBursts 386716 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24729280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue +system.physmem.bytesWritten 18881664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24749824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18883520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24110 # Per bank write bursts -system.physmem.perBankRdBursts::1 26511 # Per bank write bursts -system.physmem.perBankRdBursts::2 24689 # Per bank write bursts -system.physmem.perBankRdBursts::3 24586 # Per bank write bursts -system.physmem.perBankRdBursts::4 23301 # Per bank write bursts -system.physmem.perBankRdBursts::5 23773 # Per bank write bursts -system.physmem.perBankRdBursts::6 24463 # Per bank write bursts -system.physmem.perBankRdBursts::7 24300 # Per bank write bursts -system.physmem.perBankRdBursts::8 23625 # Per bank write bursts -system.physmem.perBankRdBursts::9 23952 # Per bank write bursts -system.physmem.perBankRdBursts::10 24787 # Per bank write bursts -system.physmem.perBankRdBursts::11 24070 # Per bank write bursts -system.physmem.perBankRdBursts::12 23353 # Per bank write bursts -system.physmem.perBankRdBursts::13 22981 # Per bank write bursts -system.physmem.perBankRdBursts::14 24097 # Per bank write bursts -system.physmem.perBankRdBursts::15 23979 # Per bank write bursts -system.physmem.perBankWrBursts::0 18543 # Per bank write bursts -system.physmem.perBankWrBursts::1 19847 # Per bank write bursts -system.physmem.perBankWrBursts::2 18947 # Per bank write bursts -system.physmem.perBankWrBursts::3 18939 # Per bank write bursts -system.physmem.perBankWrBursts::4 18047 # Per bank write bursts -system.physmem.perBankWrBursts::5 18457 # Per bank write bursts -system.physmem.perBankWrBursts::6 18996 # Per bank write bursts -system.physmem.perBankWrBursts::7 18981 # Per bank write bursts -system.physmem.perBankWrBursts::8 18548 # Per bank write bursts -system.physmem.perBankWrBursts::9 18168 # Per bank write bursts -system.physmem.perBankWrBursts::10 18839 # Per bank write bursts -system.physmem.perBankWrBursts::11 17728 # Per bank write bursts -system.physmem.perBankWrBursts::12 17372 # Per bank write bursts -system.physmem.perBankWrBursts::13 16973 # Per bank write bursts -system.physmem.perBankWrBursts::14 17820 # Per bank write bursts -system.physmem.perBankWrBursts::15 17811 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 188421 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24059 # Per bank write bursts +system.physmem.perBankRdBursts::1 26427 # Per bank write bursts +system.physmem.perBankRdBursts::2 24735 # Per bank write bursts +system.physmem.perBankRdBursts::3 24592 # Per bank write bursts +system.physmem.perBankRdBursts::4 23512 # Per bank write bursts +system.physmem.perBankRdBursts::5 23783 # Per bank write bursts +system.physmem.perBankRdBursts::6 24571 # Per bank write bursts +system.physmem.perBankRdBursts::7 24367 # Per bank write bursts +system.physmem.perBankRdBursts::8 23708 # Per bank write bursts +system.physmem.perBankRdBursts::9 23929 # Per bank write bursts +system.physmem.perBankRdBursts::10 24776 # Per bank write bursts +system.physmem.perBankRdBursts::11 24016 # Per bank write bursts +system.physmem.perBankRdBursts::12 23246 # Per bank write bursts +system.physmem.perBankRdBursts::13 22935 # Per bank write bursts +system.physmem.perBankRdBursts::14 23871 # Per bank write bursts +system.physmem.perBankRdBursts::15 23868 # Per bank write bursts +system.physmem.perBankWrBursts::0 18618 # Per bank write bursts +system.physmem.perBankWrBursts::1 19926 # Per bank write bursts +system.physmem.perBankWrBursts::2 18978 # Per bank write bursts +system.physmem.perBankWrBursts::3 19008 # Per bank write bursts +system.physmem.perBankWrBursts::4 18159 # Per bank write bursts +system.physmem.perBankWrBursts::5 18511 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19088 # Per bank write bursts +system.physmem.perBankWrBursts::8 18666 # Per bank write bursts +system.physmem.perBankWrBursts::9 18203 # Per bank write bursts +system.physmem.perBankWrBursts::10 18897 # Per bank write bursts +system.physmem.perBankWrBursts::11 17760 # Per bank write bursts +system.physmem.perBankWrBursts::12 17400 # Per bank write bursts +system.physmem.perBankWrBursts::13 16992 # Per bank write bursts +system.physmem.perBankWrBursts::14 17815 # Per bank write bursts +system.physmem.perBankWrBursts::15 17863 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417995980500 # Total gap between requests +system.physmem.totGap 417248585500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386930 # Read request sizes (log2) +system.physmem.readPktSize::6 386716 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294035 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295055 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,48 +144,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6571 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -193,246 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.740616 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.463963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.226581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54784 37.15% 37.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40098 27.19% 64.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13706 9.29% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7465 5.06% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5444 3.69% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3767 2.55% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3056 2.07% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2830 1.92% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16307 11.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.062525 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.476315 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17502 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17513 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17513 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.846114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.774956 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.557273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17320 98.90% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 139 0.79% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 5 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads -system.physmem.totQLat 4282714250 # Total ticks spent queuing -system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17513 # Writes before turning the bus around for reads +system.physmem.totQLat 4300099500 # Total ticks spent queuing +system.physmem.totMemAccLat 11545005750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1931975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11128.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29878.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.81 # Data bus utilization in percentage +system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing -system.physmem.readRowHits 318033 # Number of row buffer hits during reads -system.physmem.writeRowHits 215097 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 613828.88 # Average gap between requests -system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.167087 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing +system.physmem.readRowHits 318002 # Number of row buffer hits during reads +system.physmem.writeRowHits 215948 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.19 # Row buffer hit rate for writes +system.physmem.avgGap 612006.94 # Average gap between requests +system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569698920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310847625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1529026200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981072000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63410789430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194721715500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 288775354395 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.105150 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 323379971500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13932620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 79931501500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.276862 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states +system.physmem_1.actEnergy 544690440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297202125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1484246400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 930262320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61581182625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196326633750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288416422380 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.244901 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 326066613500 # Time in different power states +system.physmem_1.memoryStateTime::REF 13932620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77244604500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 230262495 # Number of BP lookups -system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups -system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits +system.cpu.branchPred.lookups 230038764 # Number of BP lookups +system.cpu.branchPred.condPredicted 230038764 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9737010 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131438605 # Number of BTB lookups +system.cpu.branchPred.BTBHits 128726788 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.936818 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27748214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1467706 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 835992044 # number of cpu cycles simulated +system.cpu.numCycles 834497218 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed -system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 185109509 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1269285801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 230038764 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156475002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638168020 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20207441 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 514 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 99542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 817516 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1330 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179424674 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2717056 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 834300207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.829871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.382747 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 426804407 51.16% 51.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33711236 4.04% 55.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32817404 3.93% 59.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33341418 4.00% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27188546 3.26% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27662073 3.32% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 36987842 4.43% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33698291 4.04% 78.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182088990 21.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 834300207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275662 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.521019 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127532754 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 374895763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240450543 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81317427 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10103720 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2225154931 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10103720 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159590885 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 159861387 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39705 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285625371 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219079139 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2175033402 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 169320 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 136042771 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24241877 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48673196 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2279253847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5500789642 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3498971898 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 55892 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 665212993 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3161 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2925 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 415266866 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528334914 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 209874644 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 239338770 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72144908 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2101019043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25133 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1826920514 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 398452 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 572055475 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 973771254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24581 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 834300207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.189764 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.073153 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 254789239 30.54% 30.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 125577373 15.05% 45.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119153367 14.28% 59.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111141032 13.32% 73.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 92244378 11.06% 84.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61717114 7.40% 91.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43107761 5.17% 96.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19155881 2.30% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7414062 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 834300207 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11334405 42.48% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12275528 46.01% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3069676 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718617 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211210104 66.30% 66.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 389740 0.02% 66.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881078 0.21% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 127 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 27 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 416 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued @@ -454,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435004125 23.81% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173716278 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued -system.cpu.iq.rate 2.185458 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1826920514 # Type of FU issued +system.cpu.iq.rate 2.189247 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26679609 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4515187521 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2673359658 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1796857140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31775 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70770 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6885 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1850866868 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14638 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185770181 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144235066 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213448 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 384677 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 60714458 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19450 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 994 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10103720 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 107027275 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6171947 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2101044176 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 397040 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528337223 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 209874644 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7154 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1885059 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3390398 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 384677 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5738634 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4563911 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10302545 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805509782 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 428792858 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21410732 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed -system.cpu.iew.exec_branches 171793179 # Number of branches executed -system.cpu.iew.exec_stores 170131277 # Number of stores executed -system.cpu.iew.exec_rate 2.159821 # Inst execution rate -system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1367992688 # num instructions producing a value -system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value +system.cpu.iew.exec_refs 598991015 # number of memory reference insts executed +system.cpu.iew.exec_branches 171766085 # Number of branches executed +system.cpu.iew.exec_stores 170198157 # Number of stores executed +system.cpu.iew.exec_rate 2.163590 # Inst execution rate +system.cpu.iew.wb_sent 1802110409 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1796864025 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1368049337 # num instructions producing a value +system.cpu.iew.wb_consumers 2090115063 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back +system.cpu.iew.wb_rate 2.153229 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572135204 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9825001 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756651956 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.020729 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548081 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 287953386 38.06% 38.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175292333 23.17% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57344837 7.58% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86221937 11.40% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27113369 3.58% 83.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27107052 3.58% 87.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9811804 1.30% 88.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8976581 1.19% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76830657 10.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756651956 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,338 +579,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2782646702 # The number of ROB reads -system.cpu.rob.rob_writes 4280772798 # The number of ROB writes -system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 76830657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2780945204 # The number of ROB reads +system.cpu.rob.rob_writes 4280083493 # The number of ROB writes +system.cpu.timesIdled 2292 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197011 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads -system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads -system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes -system.cpu.fp_regfile_reads 7563 # number of floating regfile reads -system.cpu.fp_regfile_writes 476 # number of floating regfile writes -system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads -system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes -system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads +system.cpu.cpi 1.009216 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.009216 # CPI: Total CPI of All Threads +system.cpu.ipc 0.990869 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.990869 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2762017076 # number of integer regfile reads +system.cpu.int_regfile_writes 1465005269 # number of integer regfile writes +system.cpu.fp_regfile_reads 7183 # number of floating regfile reads +system.cpu.fp_regfile_writes 481 # number of floating regfile writes +system.cpu.cc_regfile_reads 600929280 # number of cc regfile reads +system.cpu.cc_regfile_writes 409654003 # number of cc regfile writes +system.cpu.misc_regfile_reads 990121594 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534281 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2534273 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.021333 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 387553004 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538369 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 152.677961 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.021333 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3168 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits -system.cpu.dcache.overall_hits::total 387196758 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses -system.cpu.dcache.overall_misses::total 3775006 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 784232137 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 784232137 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 238902536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 238902536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148180257 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148180257 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387082793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387082793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387082793 # number of overall hits +system.cpu.dcache.overall_hits::total 387082793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784146 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784146 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 979945 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 979945 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3764091 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3764091 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3764091 # number of overall misses +system.cpu.dcache.overall_misses::total 3764091 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59451413500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59451413500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30841040499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30841040499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90292453999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90292453999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90292453999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90292453999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 241686682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 241686682 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 390846884 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 390846884 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 390846884 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 390846884 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011520 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011520 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006570 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009631 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009631 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009631 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009631 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21353.554555 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21353.554555 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31472.215787 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31472.215787 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23987.850984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23987.850984 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10871 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 28 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1128 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.637411 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks -system.cpu.dcache.writebacks::total 2332980 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332718 # number of writebacks +system.cpu.dcache.writebacks::total 2332718 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1016180 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1016180 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19269 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1035449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1035449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1035449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1035449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767966 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960676 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 960676 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2728642 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2728642 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2728642 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2728642 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33608501500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33608501500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29628930000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29628930000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63237431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63237431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63237431500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63237431500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006981 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006981 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19009.698999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19009.698999 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30841.751017 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30841.751017 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 7107 # number of replacements -system.cpu.icache.tags.tagsinuse 1054.726418 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 179314504 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8709 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20589.562981 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6996 # number of replacements +system.cpu.icache.tags.tagsinuse 1051.094157 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 179219973 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20825.002673 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1054.726418 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.515003 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.515003 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1602 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1051.094157 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.513230 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.513230 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 330 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1149 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 359258778 # Number of tag accesses -system.cpu.icache.tags.data_accesses 359258778 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 179317997 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179317997 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179317997 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179317997 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179317997 # number of overall hits -system.cpu.icache.overall_hits::total 179317997 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 208472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 208472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 208472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 208472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 208472 # number of overall misses -system.cpu.icache.overall_misses::total 208472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1336227738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1336227738 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1167 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 359048380 # Number of tag accesses +system.cpu.icache.tags.data_accesses 359048380 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 179223042 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179223042 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179223042 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179223042 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179223042 # number of overall hits +system.cpu.icache.overall_hits::total 179223042 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 201632 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 201632 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6362.266391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6362.266391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6362.266391 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 972 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60.750000 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248098000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12445958500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12445958500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248098000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26761368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27009466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 248098000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26761368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27009466000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990046 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990046 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268105 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268105 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.402869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151848 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21044.054613 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21044.054613 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69270.345011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69270.345011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71251.579552 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71251.579552 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70468.632691 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70468.632691 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 197098 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1966585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2627773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 256159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 190273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 190273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 199033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767553 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7980639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8194852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311749568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312302656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 544429 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5822983 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.060800 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.238964 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5468944 93.92% 93.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 354039 6.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5822983 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5095186894 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 298551493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179950 # Transaction distribution -system.membus.trans_dist::ReadResp 179949 # Transaction distribution -system.membus.trans_dist::Writeback 294035 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution -system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution -system.membus.trans_dist::ReadExReq 206980 # Transaction distribution -system.membus.trans_dist::ReadExResp 206980 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 3902690569 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadResp 180098 # Transaction distribution +system.membus.trans_dist::Writeback 295055 # Transaction distribution +system.membus.trans_dist::CleanEvict 57423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 188421 # Transaction distribution +system.membus.trans_dist::UpgradeResp 188421 # Transaction distribution +system.membus.trans_dist::ReadExReq 206618 # Transaction distribution +system.membus.trans_dist::ReadExResp 206618 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180098 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43633344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 876098 # Request fanout histogram +system.membus.snoop_fanout::samples 927615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 927615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 876098 # Request fanout histogram -system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 927615 # Request fanout histogram +system.membus.reqLayer0.occupancy 2233739536 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2422494891 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index d2da1780a..7244d6f89 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872738500 # Number of ticks simulated -final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.647861 # Number of seconds simulated +sim_ticks 1647861059500 # Number of ticks simulated +final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 720688 # Simulator instruction rate (inst/s) -host_op_rate 1332632 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1436248802 # Simulator tick rate (ticks/s) -host_mem_usage 323576 # Number of bytes of host memory used -host_seconds 1147.35 # Real time elapsed on the host +host_inst_rate 708384 # Simulator instruction rate (inst/s) +host_op_rate 1309882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1411719986 # Simulator tick rate (ticks/s) +host_mem_usage 323600 # Number of bytes of host memory used +host_seconds 1167.27 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory -system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 120384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24254848 # Number of bytes read from this memory +system.physmem.bytes_read::total 24375232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 120384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 120384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18763136 # Number of bytes written to this memory +system.physmem.bytes_written::total 18763136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 378982 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380863 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293174 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293174 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 73055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14718989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14792043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 73055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 73055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11386358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11386358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11386358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 73055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14718989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26178401 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745477 # number of cpu cycles simulated +system.cpu.numCycles 3295722119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3295722118.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -100,12 +100,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4086.415711 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 8211725500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415711 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29707934500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29707934500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18949311500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18949311500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48657246000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48657246000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48657246000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48657246000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) @@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19320.253107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19320.253107 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks -system.cpu.dcache.writebacks::total 2323523 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2323227 # number of writebacks +system.cpu.dcache.writebacks::total 2323227 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses @@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27980520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27980520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18158267500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18158267500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46138788000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46138788000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46138788000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46138788000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.348726 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.348726 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430346 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430346 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115655000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115655000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115655000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115655000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115655000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115655000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41099.857854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41099.857854 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -276,116 +276,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112841000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 112841000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112841000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 112841000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112841000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 112841000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 348182 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29285.938694 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3846845 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380537 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.108991 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 755943397500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.116925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8218.320163 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.638687 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004246 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.250803 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893736 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39930218 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39930218 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits -system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses -system.cpu.l2cache.overall_misses::total 381143 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.tag_accesses 41466677 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41466677 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 2323227 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2323227 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 584717 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 584717 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 933 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 933 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554759 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1554759 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 933 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2139476 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2140409 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 933 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2139476 # number of overall hits +system.cpu.l2cache.overall_hits::total 2140409 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 206327 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206327 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1881 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1881 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172655 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 172655 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1881 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 378982 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380863 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1881 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 378982 # number of overall misses +system.cpu.l2cache.overall_misses::total 380863 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10832173000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10832173000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 98817000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 98817000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9064428500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9064428500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 98817000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19896601500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19995418500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 98817000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19896601500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19995418500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 2323227 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2323227 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1727414 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1727414 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260829 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260829 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.668443 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.668443 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099950 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099950 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.668443 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150482 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151060 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.668443 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150482 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151060 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.026657 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.026657 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52534.290271 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52534.290271 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.237468 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.237468 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.291443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.291443 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,107 +400,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks -system.cpu.l2cache.writebacks::total 292286 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293174 # number of writebacks +system.cpu.l2cache.writebacks::total 293174 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 275 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 275 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206327 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206327 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1881 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1881 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172655 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172655 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1881 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 378982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1881 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 378982 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380863 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8768903000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8768903000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 80007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 80007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7337878500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7337878500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 80007000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16106781500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16186788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 80007000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16106781500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16186788500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260829 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260829 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.668443 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099950 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099950 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151060 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151060 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309867840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348182 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.064657 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.245920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4844795 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5036887 93.53% 93.53% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 348182 6.47% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 174452 # Transaction distribution -system.membus.trans_dist::ReadResp 174452 # Transaction distribution -system.membus.trans_dist::Writeback 292286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206691 # Transaction distribution -system.membus.trans_dist::ReadExResp 206691 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 174536 # Transaction distribution +system.membus.trans_dist::Writeback 293174 # Transaction distribution +system.membus.trans_dist::CleanEvict 53553 # Transaction distribution +system.membus.trans_dist::ReadExReq 206327 # Transaction distribution +system.membus.trans_dist::ReadExResp 206327 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174536 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108453 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108453 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108453 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43138368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43138368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43138368 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 673429 # Request fanout histogram +system.membus.snoop_fanout::samples 727623 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727623 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 673429 # Request fanout histogram -system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727623 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900350576 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904342076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 5e6582f7a..1a7177e69 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226051 # Number of seconds simulated -sim_ticks 226051212500 # Number of ticks simulated -final_tick 226051212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226045 # Number of seconds simulated +sim_ticks 226044973500 # Number of ticks simulated +final_tick 226044973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 313509 # Simulator instruction rate (inst/s) -host_op_rate 313509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177766322 # Simulator tick rate (ticks/s) -host_mem_usage 302576 # Number of bytes of host memory used -host_seconds 1271.62 # Real time elapsed on the host +host_inst_rate 304016 # Simulator instruction rate (inst/s) +host_op_rate 304016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172378586 # Simulator tick rate (ticks/s) +host_mem_usage 302856 # Number of bytes of host memory used +host_seconds 1311.33 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249344 # Nu system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1103042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1126258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2229300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1103042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1103042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1103042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1126258 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2229300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1103073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1126289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1103073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1103073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1103073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1126289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229362 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7874 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226051111000 # Total gap between requests +system.physmem.totGap 226044886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.964194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.457187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.645688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 541 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 357 22.83% 57.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 194 12.40% 69.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 101 6.46% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 65 4.16% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 3.52% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 2.24% 86.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34 2.17% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1564 # Bytes accessed per row activation -system.physmem.totQLat 54215500 # Total ticks spent queuing -system.physmem.totMemAccLat 201853000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1551 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.878788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.961760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.450478 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 540 34.82% 34.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 341 21.99% 56.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 198 12.77% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 6.77% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 4.38% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.77% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.13% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.32% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 12.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1551 # Bytes accessed per row activation +system.physmem.totQLat 53691750 # Total ticks spent queuing +system.physmem.totMemAccLat 201329250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6885.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6818.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25635.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25568.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6308 # Number of row buffer hits during reads +system.physmem.readRowHits 6316 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28708548.51 # Average gap between requests -system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6872040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3749625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28707757.94 # Average gap between requests +system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6811560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3716625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34210800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5850636750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130498264500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151158364635 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.692398 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217093450250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7548320000 # Time in different power states +system.physmem_0.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5854324365 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130490358000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151153426710 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.693587 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217080502500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7548060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1408913500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1414335000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4951800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2701875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 27042600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27011400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5592917520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 130724334000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151116461715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.507029 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 217471574500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7548320000 # Time in different power states +system.physmem_1.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5569701705 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130740027000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151108340715 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.494129 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 217498306250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7548060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1030789250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 997097750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46270925 # Number of BP lookups -system.cpu.branchPred.condPredicted 26727379 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1017826 # Number of conditional branches incorrect +system.cpu.branchPred.lookups 46270920 # Number of BP lookups +system.cpu.branchPred.condPredicted 26727376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1017825 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360644 # Number of BTB hits +system.cpu.branchPred.BTBHits 21360645 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.374580 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.374584 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341957 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95612151 # DTB read hits +system.cpu.dtb.read_hits 95612152 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95612267 # DTB read accesses -system.cpu.dtb.write_hits 73605971 # DTB write hits +system.cpu.dtb.read_accesses 95612268 # DTB read accesses +system.cpu.dtb.write_hits 73605970 # DTB write hits system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606829 # DTB write accesses +system.cpu.dtb.write_accesses 73606828 # DTB write accesses system.cpu.dtb.data_hits 169218122 # DTB hits system.cpu.dtb.data_misses 974 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 169219096 # DTB accesses -system.cpu.itb.fetch_hits 98739643 # ITB hits +system.cpu.itb.fetch_hits 98739640 # ITB hits system.cpu.itb.fetch_misses 1232 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98740875 # ITB accesses +system.cpu.itb.fetch_accesses 98740872 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 452102425 # number of cpu cycles simulated +system.cpu.numCycles 452089947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4488157 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4488161 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.134042 # CPI: cycles per instruction -system.cpu.ipc 0.881802 # IPC: instructions per cycle -system.cpu.tickCycles 448265843 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3836582 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.134011 # CPI: cycles per instruction +system.cpu.ipc 0.881826 # IPC: instructions per cycle +system.cpu.tickCycles 448265885 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3824062 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.681680 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168032891 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.715048 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168032888 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40344.031453 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40344.030732 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.681680 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803633 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.715048 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803641 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803641 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336084169 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336084169 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94518092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94518092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168032891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168032891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168032891 # number of overall hits -system.cpu.dcache.overall_hits::total 168032891 # number of overall hits +system.cpu.dcache.tags.tag_accesses 336084171 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336084171 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94518093 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94518093 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514795 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514795 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168032888 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168032888 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168032888 # number of overall hits +system.cpu.dcache.overall_hits::total 168032888 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7111 # number of overall misses -system.cpu.dcache.overall_misses::total 7111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88098000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88098000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 432683750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 432683750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 520781750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 520781750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 520781750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 520781750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94519272 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94519272 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5935 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5935 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7115 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7115 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7115 # number of overall misses +system.cpu.dcache.overall_misses::total 7115 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87916000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87916000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 428863500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 428863500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 516779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 516779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 516779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 516779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94519273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94519273 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168040002 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168040002 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168040002 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168040002 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168040003 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168040003 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168040003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168040003 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74659.322034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74659.322034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72952.916877 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72952.916877 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73236.077907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73236.077907 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74505.084746 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74505.084746 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72260.067397 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72260.067397 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72632.396346 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72632.396346 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2946 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2946 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2946 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2946 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2739 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2739 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2950 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2950 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2950 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69978250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 69978250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 238524000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 238524000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308502250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 308502250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308502250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 308502250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71088500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 71088500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239432500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 239432500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310521000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310521000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310521000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310521000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72216.976264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72216.976264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74632.040050 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74632.040050 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73362.745098 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73362.745098 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74916.301627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74916.301627 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3197 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.668517 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98734468 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1918.682192 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98734465 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19079.124251 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 19079.123671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668517 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.682192 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197484461 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197484461 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98734468 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98734468 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98734468 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98734468 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98734468 # number of overall hits -system.cpu.icache.overall_hits::total 98734468 # number of overall hits +system.cpu.icache.tags.tag_accesses 197484455 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197484455 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98734465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98734465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98734465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98734465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98734465 # number of overall hits +system.cpu.icache.overall_hits::total 98734465 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses system.cpu.icache.overall_misses::total 5175 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 322926000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 322926000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 322926000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 322926000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 322926000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 322926000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98739643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98739643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98739643 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98739643 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98739643 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98739643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 319209000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 319209000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 319209000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 319209000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 319209000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 319209000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98739640 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98739640 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98739640 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98739640 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98739640 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98739640 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62401.159420 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62401.159420 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62401.159420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62401.159420 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61682.898551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61682.898551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61682.898551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61682.898551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,116 +488,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5175 system.cpu.icache.demand_mshr_misses::total 5175 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5175 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5175 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 313513500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 313513500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 313513500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 313513500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 313513500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 313513500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 314034000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 314034000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 314034000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 314034000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 314034000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 314034000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60682.898551 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60682.898551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60682.898551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60682.898551 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.539250 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4426.586364 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4808 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.283276 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.911642 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.086855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.473471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 641.978924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 373.093241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.507533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.985590 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135089 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 88424 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 88424 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 114936 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114936 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1279 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1279 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 126 # 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number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 3896 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7874 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3896 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7874 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 294908500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 67534250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 362442750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234806000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 234806000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 294908500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 302340250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 597248750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 294908500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 302340250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 597248750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5175 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 6142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234115500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 234115500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 292841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 292841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 68160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 292841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 302276000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 595117000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 292841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 302276000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 595117000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5175 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5175 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 5175 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9340 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 5175 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9340 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752850 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.771247 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.752850 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.752850 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752850 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.843041 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752850 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843041 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75695.200205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80302.318668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76513.141229 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74850.494103 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74850.494103 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75850.742951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75850.742951 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74630.379343 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74630.379343 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75164.527721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75164.527721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81046.967895 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81046.967895 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75164.527721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75986.928105 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75580.010160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75164.527721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75986.928105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75580.010160 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,84 +612,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3896 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3896 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3896 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 202745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 202745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 253881000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 253881000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59750500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59750500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 253881000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262496000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 516377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 253881000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262496000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 516377000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63176.463039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67750.594530 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63988.547604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62350.015939 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62350.015939 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64630.379343 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64630.379343 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65164.527721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65164.527721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71046.967895 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71046.967895 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3314 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10350 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22648 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9994 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13308 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9994 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13308 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9994 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5651000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13308 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7308000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8587500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7762500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7035750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4737 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes) @@ -699,9 +711,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7874 # Request fanout histogram -system.membus.reqLayer0.occupancy 9179500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9183500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41811750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41813250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 1cb945d89..be9d713b1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.069793 # Number of seconds simulated -sim_ticks 69793219500 # Number of ticks simulated -final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069809 # Number of seconds simulated +sim_ticks 69809049000 # Number of ticks simulated +final_tick 69809049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237836 # Simulator instruction rate (inst/s) -host_op_rate 237836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44197170 # Simulator tick rate (ticks/s) -host_mem_usage 232228 # Number of bytes of host memory used -host_seconds 1579.13 # Real time elapsed on the host +host_inst_rate 246384 # Simulator instruction rate (inst/s) +host_op_rate 246384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45796096 # Simulator tick rate (ticks/s) +host_mem_usage 304152 # Number of bytes of host memory used +host_seconds 1524.35 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory -system.physmem.bytes_read::total 477248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7457 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3172801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3665227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6838028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3172801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3172801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3172801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3665227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6838028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7457 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255680 # Number of bytes read from this memory +system.physmem.bytes_read::total 477184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3995 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7456 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3172998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3662562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6835561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3172998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3172998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3172998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3662562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6835561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7456 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7457 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7456 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 477248 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 477248 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 527 # Per bank write bursts -system.physmem.perBankRdBursts::1 657 # Per bank write bursts -system.physmem.perBankRdBursts::2 455 # Per bank write bursts -system.physmem.perBankRdBursts::3 602 # Per bank write bursts +system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::2 454 # Per bank write bursts +system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 454 # Per bank write bursts +system.physmem.perBankRdBursts::5 455 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts -system.physmem.perBankRdBursts::7 522 # Per bank write bursts -system.physmem.perBankRdBursts::8 438 # Per bank write bursts +system.physmem.perBankRdBursts::7 525 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts system.physmem.perBankRdBursts::9 407 # Per bank write bursts -system.physmem.perBankRdBursts::10 339 # Per bank write bursts +system.physmem.perBankRdBursts::10 338 # Per bank write bursts system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 542 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 69793123000 # Total gap between requests +system.physmem.totGap 69808953500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7457 # Read request sizes (log2) +system.physmem.readPktSize::6 7456 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.047059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.039838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.646558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 428 31.47% 31.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 327 24.04% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 157 11.54% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 6.76% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 4.12% 77.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.87% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.43% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.84% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 203 14.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1360 # Bytes accessed per row activation -system.physmem.totQLat 67335750 # Total ticks spent queuing -system.physmem.totMemAccLat 207154500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37285000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9029.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 349.142435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.457712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.186854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 436 32.18% 32.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 321 23.69% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 135 9.96% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 7.60% 73.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 4.13% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 42 3.10% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.73% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 2.07% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 197 14.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1355 # Bytes accessed per row activation +system.physmem.totQLat 63176250 # Total ticks spent queuing +system.physmem.totMemAccLat 202976250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8473.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27779.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27223.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s @@ -214,72 +214,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6086 # Number of row buffer hits during reads +system.physmem.readRowHits 6090 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9359410.35 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem.avgGap 9362788.83 # Average gap between requests +system.physmem.pageHitRate 81.68 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32377800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 32370000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2111779035 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 40020613500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 46732002750 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.624038 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 66577889000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2330380000 # Time in different power states +system.physmem_0.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2097349200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 40042614750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46740583485 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.597578 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66614495250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2330900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 882777000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 861488750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4430160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2417250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25272000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25256400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2013356565 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 40106949000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 46710648255 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.318049 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 66719394750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2330380000 # Time in different power states +system.physmem_1.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1988059680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40138482750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46717839900 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.271757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66771998750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2330900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 738657750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 701106250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 51259743 # Number of BP lookups -system.cpu.branchPred.condPredicted 29683169 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233682 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26552604 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23664767 # Number of BTB hits +system.cpu.branchPred.lookups 51296431 # Number of BP lookups +system.cpu.branchPred.condPredicted 29722668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1234399 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27069453 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23684308 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.124091 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9366329 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 317 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.494594 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9353372 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 312 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103795078 # DTB read hits -system.cpu.dtb.read_misses 91880 # DTB read misses -system.cpu.dtb.read_acv 49322 # DTB read access violations -system.cpu.dtb.read_accesses 103886958 # DTB read accesses -system.cpu.dtb.write_hits 79431295 # DTB write hits -system.cpu.dtb.write_misses 1540 # DTB write misses +system.cpu.dtb.read_hits 103786850 # DTB read hits +system.cpu.dtb.read_misses 91978 # DTB read misses +system.cpu.dtb.read_acv 49358 # DTB read access violations +system.cpu.dtb.read_accesses 103878828 # DTB read accesses +system.cpu.dtb.write_hits 79421845 # DTB write hits +system.cpu.dtb.write_misses 1562 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79432835 # DTB write accesses -system.cpu.dtb.data_hits 183226373 # DTB hits -system.cpu.dtb.data_misses 93420 # DTB misses -system.cpu.dtb.data_acv 49324 # DTB access violations -system.cpu.dtb.data_accesses 183319793 # DTB accesses -system.cpu.itb.fetch_hits 51424924 # ITB hits -system.cpu.itb.fetch_misses 367 # ITB misses +system.cpu.dtb.write_accesses 79423407 # DTB write accesses +system.cpu.dtb.data_hits 183208695 # DTB hits +system.cpu.dtb.data_misses 93540 # DTB misses +system.cpu.dtb.data_acv 49360 # DTB access violations +system.cpu.dtb.data_accesses 183302235 # DTB accesses +system.cpu.itb.fetch_hits 51432488 # ITB hits +system.cpu.itb.fetch_misses 372 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51425291 # ITB accesses +system.cpu.itb.fetch_accesses 51432860 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,106 +293,106 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 139586442 # number of cpu cycles simulated +system.cpu.numCycles 139618100 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52218190 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457878359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51259743 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33031096 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85762697 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2573496 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 52215637 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 458041697 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51296431 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33037680 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85803922 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2575582 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13442 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51424924 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 558112 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139281263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.344389 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 177 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13927 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51432488 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569689 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139321507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344182 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58400466 41.93% 41.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519538 3.24% 45.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7300185 5.24% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5568881 4.00% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11993718 8.61% 63.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8035210 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5954127 4.27% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1896980 1.36% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35612158 25.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58400173 41.92% 41.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4522566 3.25% 45.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7306043 5.24% 50.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5576459 4.00% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12017776 8.63% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8032548 5.77% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5948759 4.27% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1886194 1.35% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35630989 25.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139281263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367226 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.280250 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45296559 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16238717 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71951122 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4512320 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1282545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9579038 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4257 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 452073358 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14179 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1282545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47196926 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5664651 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519192 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74460720 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10157229 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 448418638 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2532304 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2861217 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3565763 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 292805975 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 590541853 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 420605547 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169936305 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139321507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367405 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.280676 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45279858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16277373 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71952167 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4528520 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1283589 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9590263 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 452242919 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14142 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1283589 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47190225 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5719256 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74463142 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10145537 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 448534058 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439648 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2541243 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2902301 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3500431 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292850852 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 590664412 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 420646005 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 170018406 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33273646 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37923 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 33318523 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37911 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15988914 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106425467 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81691000 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12462225 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9670397 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 415046688 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 39472187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.924100 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.223091 # Number of insts issued each cycle +system.cpu.rename.skidInsts 16086321 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106433302 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81699514 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12490023 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9782021 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 415154479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 307 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407277518 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 483889 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 39579977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18549388 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 92 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139321507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.923293 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.222373 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24058662 17.27% 17.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19633951 14.10% 31.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22674806 16.28% 47.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18925755 13.59% 61.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19544360 14.03% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14234748 10.22% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9653364 6.93% 92.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6204842 4.45% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4350775 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24043039 17.26% 17.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19688824 14.13% 31.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22672553 16.27% 47.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18939258 13.59% 61.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19545668 14.03% 75.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14219061 10.21% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9684319 6.95% 92.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6188357 4.44% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4340428 3.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139281263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139321507 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 264805 1.33% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 265122 1.33% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 1.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 148480 0.74% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 91560 0.46% 2.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2226 0.01% 2.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3500111 17.53% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1672568 8.38% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 151057 0.76% 2.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 93335 0.47% 2.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3062 0.02% 2.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3506383 17.53% 20.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1668666 8.34% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available @@ -414,118 +414,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9323721 46.69% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4965817 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9341831 46.71% 75.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4968318 24.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153389569 37.66% 37.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128191 0.52% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153385991 37.66% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128232 0.52% 38.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37431648 9.19% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7537641 1.85% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2804878 0.69% 49.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16758896 4.11% 54.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1606846 0.39% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105464958 25.90% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80116078 19.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37448194 9.19% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7543709 1.85% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2805732 0.69% 49.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16759263 4.11% 54.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1610357 0.40% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105461195 25.89% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80101264 19.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407272286 # Type of FU issued -system.cpu.iq.rate 2.917707 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 266819247 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187775636 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19964423 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407277518 # Type of FU issued +system.cpu.iq.rate 2.917083 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19997775 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049101 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 626671270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 266840013 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237433052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347686937 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187970906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163426789 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246404368 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180837344 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19931279 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11670980 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 165408 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76048 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8170271 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11678815 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 164981 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76480 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8178785 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382447 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 381276 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3827 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1282545 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4525606 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 90420 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 440059104 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 152527 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106425467 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81691000 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 308 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7009 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82356 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76048 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1000879 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 421168 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1422047 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403473304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103936308 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3798982 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1283589 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4537578 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127300 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 440164979 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 164208 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106433302 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81699514 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 307 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 117247 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76480 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1004792 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 416739 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1421531 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403496390 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103928218 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3781128 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25012108 # number of nop insts executed -system.cpu.iew.exec_refs 183369178 # number of memory reference insts executed -system.cpu.iew.exec_branches 46997600 # Number of branches executed -system.cpu.iew.exec_stores 79432870 # Number of stores executed -system.cpu.iew.exec_rate 2.890491 # Inst execution rate -system.cpu.iew.wb_sent 401684713 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400846234 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198095133 # num instructions producing a value -system.cpu.iew.wb_consumers 284050882 # num instructions consuming a value +system.cpu.iew.exec_nop 25010193 # number of nop insts executed +system.cpu.iew.exec_refs 183351660 # number of memory reference insts executed +system.cpu.iew.exec_branches 47000418 # Number of branches executed +system.cpu.iew.exec_stores 79423442 # Number of stores executed +system.cpu.iew.exec_rate 2.890001 # Inst execution rate +system.cpu.iew.wb_sent 401708524 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400859841 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198115569 # num instructions producing a value +system.cpu.iew.wb_consumers 284128842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.871670 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697393 # average fanout of values written-back +system.cpu.iew.wb_rate 2.871117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697274 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 41395670 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 41501718 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1229479 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133482933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.986633 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.212859 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1230197 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133512631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.985969 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.212275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48683097 36.47% 36.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18109981 13.57% 50.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9618460 7.21% 57.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8715508 6.53% 63.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6449297 4.83% 68.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4412968 3.31% 71.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5003390 3.75% 75.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2633066 1.97% 77.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29857166 22.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48674660 36.46% 36.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18127731 13.58% 50.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9648746 7.23% 57.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8719124 6.53% 63.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6443109 4.83% 68.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4416607 3.31% 71.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5004547 3.75% 75.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2625621 1.97% 77.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29852486 22.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133482933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133512631 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,127 +571,127 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 543683043 # The number of ROB reads -system.cpu.rob.rob_writes 885930772 # The number of ROB writes -system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 305179 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29852486 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 543823469 # The number of ROB reads +system.cpu.rob.rob_writes 886153369 # The number of ROB writes +system.cpu.timesIdled 3159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 296593 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.371661 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.371661 # CPI: Total CPI of All Threads -system.cpu.ipc 2.690625 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.690625 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403591803 # number of integer regfile reads -system.cpu.int_regfile_writes 172078772 # number of integer regfile writes -system.cpu.fp_regfile_reads 157997982 # number of floating regfile reads -system.cpu.fp_regfile_writes 105636085 # number of floating regfile writes +system.cpu.cpi 0.371745 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.371745 # CPI: Total CPI of All Threads +system.cpu.ipc 2.690015 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.690015 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403553331 # number of integer regfile reads +system.cpu.int_regfile_writes 172072539 # number of integer regfile writes +system.cpu.fp_regfile_reads 158043337 # number of floating regfile reads +system.cpu.fp_regfile_writes 105673333 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 806 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.136243 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156944357 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4209 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37287.801616 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 795 # number of replacements +system.cpu.dcache.tags.tagsinuse 3296.035456 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156970312 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4197 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.598523 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.136243 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3296.035456 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313935887 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313935887 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83443297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83443297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501051 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501051 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156944348 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156944348 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156944348 # number of overall hits -system.cpu.dcache.overall_hits::total 156944348 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19678 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21482 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21482 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21482 # number of overall misses -system.cpu.dcache.overall_misses::total 21482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 122640500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 122640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1228413709 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1228413709 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1351054209 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1351054209 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1351054209 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1351054209 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83445101 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83445101 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313987939 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313987939 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83469338 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83469338 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500964 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500964 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156970302 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156970302 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156970302 # number of overall hits +system.cpu.dcache.overall_hits::total 156970302 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19765 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19765 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21559 # number of overall misses +system.cpu.dcache.overall_misses::total 21559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128871000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128871000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1185279954 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1185279954 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1314150954 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1314150954 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1314150954 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1314150954 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83471132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83471132 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156965830 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156965830 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156965830 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156965830 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156991861 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156991861 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156991861 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156991861 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62892.384741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62892.384741 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 51314 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 737 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71834.448161 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71834.448161 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.629092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.629092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60956.025511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60956.025511 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49421 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 88 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 747 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.625509 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 108 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.159304 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 88 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682 # number of writebacks -system.cpu.dcache.writebacks::total 682 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 803 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17273 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17273 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17273 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17273 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1001 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1001 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3208 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3208 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4209 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4209 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4209 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4209 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72824500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 72824500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 253362750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 253362750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 326187250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 326187250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 326187250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 326187250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 671 # number of writebacks +system.cpu.dcache.writebacks::total 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 799 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16563 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16563 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17362 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17362 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17362 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17362 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 995 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4197 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4197 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76593500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76593500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 246844000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 246844000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 323437500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 323437500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 323437500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 323437500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -700,198 +700,204 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76978.391960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76978.391960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77090.568395 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77090.568395 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77063.974267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77063.974267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77063.974267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77063.974267 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2160 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.206745 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 51419247 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4087 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12581.171275 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2157 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.216020 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51426803 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4084 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12592.263222 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.206745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.216020 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894637 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894637 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1348 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 293 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.847453 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.847453 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.868342 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.868342 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847453 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.951870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.900374 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847453 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.951870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.900374 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77036.889173 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77036.889173 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.090436 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.090436 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85225.115741 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85225.115741 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.090436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78807.759700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77442.730687 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.090436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78807.759700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77442.730687 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -900,102 +906,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 867 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4327 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 210540750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220205500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 270058750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 490264250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220205500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 270058750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 490264250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.975686 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.975686 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.898867 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.898867 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3461 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3461 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3995 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7456 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 209892500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 209892500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227966000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227966000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64994500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64994500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227966000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274887000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 502853000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227966000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274887000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 502853000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.847453 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.868342 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.868342 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900374 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900374 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67036.889173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67036.889173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65867.090436 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65867.090436 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75225.115741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75225.115741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3208 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9100 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 313024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 574592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 5079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4084 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 995 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 572928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 11233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8978 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11233 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8978 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5171000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11233 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 6287500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6830250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6126000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6882750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6295500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4327 # Transaction distribution -system.membus.trans_dist::ReadResp 4327 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14914 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14914 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 4325 # Transaction distribution +system.membus.trans_dist::ReadExReq 3131 # Transaction distribution +system.membus.trans_dist::ReadExResp 3131 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4325 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14912 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7457 # Request fanout histogram +system.membus.snoop_fanout::samples 7456 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7457 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7456 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7457 # Request fanout histogram -system.membus.reqLayer0.occupancy 9341500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7456 # Request fanout histogram +system.membus.reqLayer0.occupancy 9215500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39310250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39331250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 97440304f..8c86953a0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335093500 # Number of ticks simulated -final_tick 567335093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567335097500 # Number of ticks simulated +final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1360508 # Simulator instruction rate (inst/s) -host_op_rate 1360508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1936123010 # Simulator tick rate (ticks/s) -host_mem_usage 299124 # Number of bytes of host memory used -host_seconds 293.03 # Real time elapsed on the host +host_inst_rate 1293186 # Simulator instruction rate (inst/s) +host_op_rate 1293186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1840317995 # Simulator tick rate (ticks/s) +host_mem_usage 300812 # Number of bytes of host memory used +host_seconds 308.28 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670187 # number of cpu cycles simulated +system.cpu.numCycles 1134670195 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670187 # Number of busy cycles +system.cpu.num_busy_cycles 1134670195 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930570 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.930558 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930558 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 168787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 168787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214446000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 46134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 170388000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 170388000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216522000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 216522000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216522000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 216522000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -221,22 +221,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138960 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.138955 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138960 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138955 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id @@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182359500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182359500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182359500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182359500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182359500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182363500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182363500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182363500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182363500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182363500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182363500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49648.652328 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49648.652328 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49649.741356 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49649.741356 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176850000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176850000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176850000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176850000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176850000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176850000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178690500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 178690500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178690500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 178690500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178690500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 178690500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485298 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3772.485272 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540220 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469918 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475159 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540218 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475155 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy @@ -337,78 +337,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 75560 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 75560 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits system.cpu.l2cache.overall_hits::total 651 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 168263000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43417500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 211680500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 168263000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 168265000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 168265000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43417500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 43417500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 168265000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 376635500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 168263000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 376637500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 168265000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 376635500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::total 376637500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,84 +423,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 129802500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33493500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163296000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127251000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127251000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129802500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 290547000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129802500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160744500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 290547000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 136215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 136215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 136215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168682500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304897500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 136215000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168682500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 304897500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10358 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4032 # Transaction distribution system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) @@ -510,9 +522,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7174500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7176500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35870500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35872500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 572510825..454441ad4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216140 # Number of seconds simulated -sim_ticks 216139917000 # Number of ticks simulated -final_tick 216139917000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216071 # Number of seconds simulated +sim_ticks 216071083000 # Number of ticks simulated +final_tick 216071083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173188 # Simulator instruction rate (inst/s) -host_op_rate 207931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137097336 # Simulator tick rate (ticks/s) -host_mem_usage 323040 # Number of bytes of host memory used -host_seconds 1576.54 # Real time elapsed on the host +host_inst_rate 173126 # Simulator instruction rate (inst/s) +host_op_rate 207857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137004908 # Simulator tick rate (ticks/s) +host_mem_usage 323124 # Number of bytes of host memory used +host_seconds 1577.10 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013862 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1232387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2246249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1232387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2246249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7586 # Number of read requests accepted +system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1013889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1232779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2246668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1013889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1013889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1013889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1232779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2246668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7585 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 428 # Pe system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 541 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216139680500 # Total gap between requests +system.physmem.totGap 216070847500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7586 # Read request sizes (log2) +system.physmem.readPktSize::6 7585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.319107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.795582 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.243204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 551 36.18% 36.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 346 22.72% 58.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 176 11.56% 70.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 5.32% 75.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 75 4.92% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 50 3.28% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.10% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.84% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 184 12.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 53007250 # Total ticks spent queuing -system.physmem.totMemAccLat 195244750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6987.51 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.445847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.975712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.801659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 552 36.68% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 337 22.39% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 156 10.37% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 81 5.38% 74.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 75 4.98% 79.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 3.92% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 41 2.72% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.93% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation +system.physmem.totQLat 52368250 # Total ticks spent queuing +system.physmem.totMemAccLat 194587000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6904.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25737.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25654.19 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6060 # Number of row buffer hits during reads +system.physmem.readRowHits 6074 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28491916.75 # Average gap between requests -system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5004720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2730750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 30022200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28486598.22 # Average gap between requests +system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29959800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5648540400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124728404250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144531819360 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.699173 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 207494790250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7217340000 # Time in different power states +system.physmem_0.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5672899350 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124664991000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144488195730 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.714152 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 207389955000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7215000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1426657250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1464485500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6509160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3551625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29062800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6320160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3448500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5781551040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124611728250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144549519915 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.781068 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207298156250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7217340000 # Time in different power states +system.physmem_1.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5762856465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124586081250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144500238975 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.769890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207255387750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7215000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1623563250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1598323500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33139216 # Number of BP lookups -system.cpu.branchPred.condPredicted 17107199 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1560655 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17520877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15610870 # Number of BTB hits +system.cpu.branchPred.lookups 33111389 # Number of BP lookups +system.cpu.branchPred.condPredicted 17094855 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1552605 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17374125 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15590921 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.098679 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6611023 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 89.736439 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6603992 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,69 +377,69 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 432279834 # number of cpu cycles simulated +system.cpu.numCycles 432142166 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4207498 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4177938 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.583223 # CPI: cycles per instruction -system.cpu.ipc 0.631623 # IPC: instructions per cycle -system.cpu.tickCycles 428628441 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3651393 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.582719 # CPI: cycles per instruction +system.cpu.ipc 0.631824 # IPC: instructions per cycle +system.cpu.tickCycles 428506724 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3635442 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.737950 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168771151 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.759854 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168767138 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37413.245622 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37412.356019 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.737950 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.759854 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753359 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753359 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337561379 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337561379 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86638362 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86638362 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047459 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047459 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337553367 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337553367 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86634356 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86634356 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047452 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047452 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168685821 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168685821 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168749361 # number of overall hits -system.cpu.dcache.overall_hits::total 168749361 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168681808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168681808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168745348 # number of overall hits +system.cpu.dcache.overall_hits::total 168745348 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5218 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5218 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5225 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5225 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7277 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7277 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7283 # number of overall misses -system.cpu.dcache.overall_misses::total 7283 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 136967456 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 136967456 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400451000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400451000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 537418456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 537418456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 537418456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 537418456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86640421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86640421 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7284 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7284 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses +system.cpu.dcache.overall_misses::total 7290 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 134727000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 134727000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 395694000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 395694000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 530421000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 530421000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 530421000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 530421000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86636415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86636415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168693098 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168693098 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168756644 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168756644 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168689092 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168689092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168752638 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168752638 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73851.649856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73790.808183 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65433.220010 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65433.220010 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75730.909091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75730.909091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72820.016474 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72820.016474 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72760.082305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72760.082305 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2348 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2348 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2770 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2770 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2770 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2770 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2355 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2355 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507 system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108888792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 108888792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220256750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220256750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329145542 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329145542 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329466292 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329466292 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108637000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 108637000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329221500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329221500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329543500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329543500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66363.469762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66363.469762 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76858.710801 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76858.710801 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73046.705125 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73046.705125 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73053.314121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73053.314121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36928 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.841098 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73108223 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38865 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1881.081256 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36911 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.852805 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73041980 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38848 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1880.199238 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.841098 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939864 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852805 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146333043 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146333043 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73108223 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73108223 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73108223 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73108223 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73108223 # number of overall hits -system.cpu.icache.overall_hits::total 73108223 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38866 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38866 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38866 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38866 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38866 # number of overall misses -system.cpu.icache.overall_misses::total 38866 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728130248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728130248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728130248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728130248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728130248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728130248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73147089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73147089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73147089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73147089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73147089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73147089 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18734.375753 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18734.375753 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18734.375753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18734.375753 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146200506 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146200506 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73041980 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73041980 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73041980 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73041980 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73041980 # number of overall hits +system.cpu.icache.overall_hits::total 73041980 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38849 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38849 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38849 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38849 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38849 # number of overall misses +system.cpu.icache.overall_misses::total 38849 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 726693000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 726693000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 726693000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 726693000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 726693000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 726693000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73080829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73080829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73080829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73080829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73080829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73080829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18705.578007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18705.578007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18705.578007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18705.578007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18705.578007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18705.578007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,123 +591,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668381252 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 668381252 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17197.068183 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17197.068183 # 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number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1308 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1308 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 481308750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214398750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266910000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 481308750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 187536500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 187536500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223262000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223262000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 87309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 87309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223262000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274846000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498108000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223262000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274846000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498108000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088110 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174885 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174931 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174885 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174931 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65710.056062 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65710.056062 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65224.072451 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65224.072451 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66750.382263 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66750.382263 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40489 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 22221 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 38849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 109950 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2839616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44387 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 81625 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44387 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 81625 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44387 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23203500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 81625 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 41822500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 59023248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58272998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7574708 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4732 # Transaction distribution -system.membus.trans_dist::ReadResp 4732 # Transaction distribution +system.membus.trans_dist::ReadResp 4731 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4731 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7586 # Request fanout histogram +system.membus.snoop_fanout::samples 7585 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7586 # Request fanout histogram -system.membus.reqLayer0.occupancy 8848500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7585 # Request fanout histogram +system.membus.reqLayer0.occupancy 8844500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40266750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40248250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 94f7097ff..8a385b77d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112557 # Number of seconds simulated -sim_ticks 112556618500 # Number of ticks simulated -final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112686 # Number of seconds simulated +sim_ticks 112686104500 # Number of ticks simulated +final_tick 112686104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125639 # Simulator instruction rate (inst/s) -host_op_rate 150843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51793233 # Simulator tick rate (ticks/s) -host_mem_usage 327772 # Number of bytes of host memory used -host_seconds 2173.19 # Real time elapsed on the host +host_inst_rate 125538 # Simulator instruction rate (inst/s) +host_op_rate 150722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51811162 # Simulator tick rate (ticks/s) +host_mem_usage 327864 # Number of bytes of host memory used +host_seconds 2174.94 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 117696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 162752 # Number of bytes read from this memory -system.physmem.bytes_read::total 467520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167936 # Number of bytes read from this memory +system.physmem.bytes_read::total 467904 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2543 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7305 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1662026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1045660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1445957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4153643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1662026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1662026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1662026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1045660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1445957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4153643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7305 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2624 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7311 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1660116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1001863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1490299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4152278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1660116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1660116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1660116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1001863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1490299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4152278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7311 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7305 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7311 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467520 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 467904 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467520 # Total read bytes from the system interface side +system.physmem.bytesReadSys 467904 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,16 +51,16 @@ system.physmem.perBankRdBursts::2 601 # Pe system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts -system.physmem.perBankRdBursts::6 146 # Per bank write bursts -system.physmem.perBankRdBursts::7 247 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 252 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts -system.physmem.perBankRdBursts::12 540 # Per bank write bursts +system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts system.physmem.perBankRdBursts::14 615 # Per bank write bursts -system.physmem.perBankRdBursts::15 555 # Per bank write bursts +system.physmem.perBankRdBursts::15 542 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112556460000 # Total gap between requests +system.physmem.totGap 112685946000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7305 # Read request sizes (log2) +system.physmem.readPktSize::6 7311 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.121147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.861490 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.787983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 501 35.91% 35.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 324 23.23% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 138 9.89% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 5.16% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 60 4.30% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 2.87% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 25 1.79% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.37% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 202 14.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1395 # Bytes accessed per row activation -system.physmem.totQLat 103629565 # Total ticks spent queuing -system.physmem.totMemAccLat 240598315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36525000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14186.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.646672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.022122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.529599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 486 35.55% 35.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 298 21.80% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 139 10.17% 67.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 76 5.56% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.61% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 51 3.73% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 1.98% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.90% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 201 14.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1367 # Bytes accessed per row activation +system.physmem.totQLat 102208518 # Total ticks spent queuing +system.physmem.totMemAccLat 239289768 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13980.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32936.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32730.10 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s @@ -218,51 +218,51 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5900 # Number of row buffer hits during reads +system.physmem.readRowHits 5935 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15408139.63 # Average gap between requests -system.physmem.pageHitRate 80.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4800600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2619375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28509000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 15413205.58 # Average gap between requests +system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 28657200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3210095790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64714428750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75311688315 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.136839 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107655127862 # Time in different power states -system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states +system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3231673425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64774920750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75402575040 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.157389 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107755851914 # Time in different power states +system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1137230638 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1164613086 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5692680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3106125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28033200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5496120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2998875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28064400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3321763065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64616466750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75326296620 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.266714 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107490739638 # Time in different power states -system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states +system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3295137510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64719250500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75410827725 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.230627 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107661884129 # Time in different power states +system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1301464112 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1258279621 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37745745 # Number of BP lookups -system.cpu.branchPred.condPredicted 20165036 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746193 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18664433 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299757 # Number of BTB hits +system.cpu.branchPred.lookups 37742989 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164516 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746156 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663196 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299233 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.688361 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7225644 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.691697 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223653 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,129 +381,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225113238 # number of cpu cycles simulated +system.cpu.numCycles 225372210 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12251417 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051298 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37745745 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24525401 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210778013 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510671 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2374 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89095174 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21831 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224788353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.802613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12439138 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334051202 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37742989 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522886 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210855691 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510707 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89092155 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21708 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225054059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.800470 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229417 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51103569 22.73% 22.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42898008 19.08% 41.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30051948 13.37% 55.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734828 44.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51374086 22.83% 22.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42891136 19.06% 41.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30054592 13.35% 55.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734245 44.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224788353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167674 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483926 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27670582 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63851253 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108576447 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23069494 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620577 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880022 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363530011 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6168132 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620577 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44985380 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17900890 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 342489 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113387887 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46551130 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355747905 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2899336 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6599141 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 195125 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7751977 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21225499 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2892433 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403402217 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533894130 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350207887 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194891394 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 225054059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167470 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.482220 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27837229 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63912010 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108618315 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23065911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620594 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880048 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363546099 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6169805 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45200014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17874059 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 342377 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113380979 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46636036 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355768136 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890465 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6610669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7803674 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223053 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2890533 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403406015 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534023592 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350247327 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894263 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31172166 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55319848 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88482470 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1658909 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1843123 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353235356 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346405014 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2300418 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25451778 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73600174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224788353 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.541027 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099686 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31175964 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55505783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416404 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498336 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661010 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1846418 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346438238 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2301579 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25468650 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73725461 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 225054059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099855 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40435382 17.99% 17.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78271933 34.82% 52.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 61035531 27.15% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34789384 15.48% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9595504 4.27% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 651863 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8756 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40665072 18.07% 18.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78300215 34.79% 52.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60997700 27.10% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34882254 15.50% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9557051 4.25% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 642945 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8822 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224788353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225054059 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9471637 7.62% 7.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7328 0.01% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 257062 0.21% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126985 0.10% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 92941 0.07% 8.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68002 0.05% 8.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 719490 0.58% 8.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 316341 0.25% 8.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 682827 0.55% 9.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53603507 43.13% 52.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58947270 47.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9490410 7.63% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7314 0.01% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126866 0.10% 7.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93218 0.07% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 721741 0.58% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683043 0.55% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53642366 43.14% 52.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58960700 47.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110656004 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148356 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655140 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148362 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798499 1.96% 34.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668326 2.50% 37.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3332485 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592467 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930113 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182308 2.07% 46.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148959 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798396 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668155 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332481 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930094 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182326 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91886991 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85885220 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923219 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883359 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346405014 # Type of FU issued -system.cpu.iq.rate 1.538803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124293390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358809 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756692141 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251708637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223263072 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287500048 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127016707 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424886 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303165485 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167532919 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5066153 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346438238 # Type of FU issued +system.cpu.iq.rate 1.537183 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124346666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358929 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757024395 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740362 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223260150 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287554385 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127018791 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424955 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303230405 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167554499 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5064919 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684353 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13689 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10190 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6106853 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684129 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13573 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122719 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 154467 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 567717 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155303 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607776 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620577 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2121612 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 331103 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353264247 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118849 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281117 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88482470 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8045 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 337585 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10190 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220609 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439082 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342414524 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90667106 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3990490 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92416404 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498336 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 338505 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220656 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439058 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659714 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342448377 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703712 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989861 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 867 # number of nop insts executed -system.cpu.iew.exec_refs 175256113 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752933 # Number of branches executed -system.cpu.iew.exec_stores 84589007 # Number of stores executed -system.cpu.iew.exec_rate 1.521077 # Inst execution rate -system.cpu.iew.wb_sent 340946411 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340687958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153730891 # num instructions producing a value -system.cpu.iew.wb_consumers 266895127 # num instructions consuming a value +system.cpu.iew.exec_nop 865 # number of nop insts executed +system.cpu.iew.exec_refs 175291126 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752707 # Number of branches executed +system.cpu.iew.exec_stores 84587414 # Number of stores executed +system.cpu.iew.exec_rate 1.519479 # Inst execution rate +system.cpu.iew.wb_sent 340943800 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340685105 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153662327 # num instructions producing a value +system.cpu.iew.wb_consumers 266738216 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513407 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575997 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511655 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23077429 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23082519 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221063225 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.482889 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.052142 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221328864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050764 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87359166 39.52% 39.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70369846 31.83% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20804571 9.41% 80.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13442893 6.08% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8809424 3.99% 90.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4514904 2.04% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2991184 1.35% 94.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2424669 1.10% 95.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10346568 4.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87530154 39.55% 39.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70479011 31.84% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20814829 9.40% 80.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13433176 6.07% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8801116 3.98% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4514131 2.04% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2986629 1.35% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2449420 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10320398 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221063225 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221328864 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,154 +654,154 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10346568 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561603777 # The number of ROB reads -system.cpu.rob.rob_writes 705508335 # The number of ROB writes -system.cpu.timesIdled 50687 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324885 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10320398 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561900676 # The number of ROB reads +system.cpu.rob.rob_writes 705518580 # The number of ROB writes +system.cpu.timesIdled 50864 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 318151 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824478 # CPI: Total CPI of All Threads -system.cpu.ipc 1.212888 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.212888 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331301011 # number of integer regfile reads -system.cpu.int_regfile_writes 136940115 # number of integer regfile writes -system.cpu.fp_regfile_reads 187107432 # number of floating regfile reads -system.cpu.fp_regfile_writes 132177980 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297030870 # number of cc regfile reads -system.cpu.cc_regfile_writes 80242369 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182848919 # number of misc regfile reads +system.cpu.cpi 0.825427 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825427 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211495 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211495 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331331443 # number of integer regfile reads +system.cpu.int_regfile_writes 136939322 # number of integer regfile writes +system.cpu.fp_regfile_reads 187108010 # number of floating regfile reads +system.cpu.fp_regfile_writes 132178699 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297132712 # number of cc regfile reads +system.cpu.cc_regfile_writes 80241070 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183128145 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533856 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.842901 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163689178 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.681825 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 84489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.842901 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999693 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999693 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533845 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844014 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163642665 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.652275 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82317000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844014 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336633512 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336633512 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82631334 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82631334 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80965560 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80965560 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70478 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70478 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336636785 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336636785 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82609327 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82609327 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941037 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941037 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70495 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70495 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163596894 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163596894 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163667372 # number of overall hits -system.cpu.dcache.overall_hits::total 163667372 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2773234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2773234 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1087139 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1087139 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163550364 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163550364 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163620859 # number of overall hits +system.cpu.dcache.overall_hits::total 163620859 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796866 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796866 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111662 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3860373 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3860373 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3860391 # number of overall misses -system.cpu.dcache.overall_misses::total 3860391 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22353219965 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22353219965 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8921439031 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8921439031 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31274658996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31274658996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31274658996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31274658996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85404568 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85404568 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses +system.cpu.dcache.overall_misses::total 3908546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22404027000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22404027000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31371530998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31371530998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31371530998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31371530998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85406193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85406193 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70496 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70496 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70513 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70513 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167457267 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167457267 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167527763 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167527763 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032472 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167458892 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167458892 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167529405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167529405 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8060.343976 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8060.343976 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8206.346227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8206.346227 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8101.460402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8101.460402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8101.422627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8101.422627 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.404145 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.404145 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8066.754102 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8066.754102 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8026.431178 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8026.431178 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8026.394214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8026.394214 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 920181 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1059827 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 117395 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 134751 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.838332 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.865077 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks -system.cpu.dcache.writebacks::total 966341 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459520 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1459520 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866494 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866494 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks +system.cpu.dcache.writebacks::total 966339 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483173 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483173 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891007 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2326014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2326014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2326014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2326014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2374180 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374180 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374180 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374180 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9970454284 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9970454284 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1720952041 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1720952041 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 709000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 709000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11691406325 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11691406325 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11692115325 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11692115325 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451082779 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12451082779 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -812,368 +812,381 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7589.516656 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7589.516656 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7799.642145 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7799.642145 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7619.733273 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7619.733273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7620.140726 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7620.140726 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.159399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.159399 # 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Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.397113 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 324802500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.830268 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999668 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178906541 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178906541 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88374047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88374047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88374047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88374047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88374047 # number of overall hits -system.cpu.icache.overall_hits::total 88374047 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721111 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721111 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721111 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721111 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721111 # number of overall misses -system.cpu.icache.overall_misses::total 721111 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5974650710 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5974650710 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5974650710 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5974650710 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5974650710 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5974650710 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89095158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89095158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89095158 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89095158 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89095158 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89095158 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8285.341244 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8285.341244 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8285.341244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8285.341244 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 59670 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2032 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178900425 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178900425 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88370349 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88370349 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88370349 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88370349 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88370349 # number of overall hits +system.cpu.icache.overall_hits::total 88370349 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721790 # number of overall misses +system.cpu.icache.overall_misses::total 721790 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973224944 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5973224944 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5973224944 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5973224944 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5973224944 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5973224944 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89092139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89092139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89092139 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89092139 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89092139 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89092139 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.571765 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8275.571765 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8275.571765 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8275.571765 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 62134 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2178 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.365157 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.528007 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716225 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 716225 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 716225 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 716225 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 716225 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 716225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5193352944 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5193352944 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5193352944 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5193352944 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5193352944 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5193352944 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7251.007636 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7251.007636 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5643 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 5643 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 5643 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 5643 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 5643 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5549831453 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5549831453 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7749.570204 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7749.570204 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 405309 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 405577 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 209 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404667 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404963 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 238 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5741 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.413940 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51684404 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51684404 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 712384 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1312658 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2025042 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 772 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5749 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030151 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414490 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 68225284 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 68225284 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 966339 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 966339 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219788 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219788 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 712384 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1532446 # 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number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 715319 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2249687 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000812 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001972 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 220653 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 220653 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 715241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1313704 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181139000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181139000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 68370000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 68370000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181139000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118983500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 300122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181139000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118983500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 489115802 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003648 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003648 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002117 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002083 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015565 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60140.537462 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64888.297872 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61381.170331 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5903.946949 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65502.176398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65502.176398 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62077.812474 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13543.310315 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015575 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6227.126919 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2029950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31761 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5466625 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32515 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205819968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32667 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531746 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.007009 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083423 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4499985 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 31761 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1075177011 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4531746 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216331500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074485469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301798469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301553965 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 6500 # Transaction distribution -system.membus.trans_dist::ReadResp 6500 # Transaction distribution +system.membus.trans_dist::ReadResp 6571 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 805 # Transaction distribution -system.membus.trans_dist::ReadExResp 805 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 467520 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 740 # Transaction distribution +system.membus.trans_dist::ReadExResp 740 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 6571 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14624 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 467904 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7306 # Request fanout histogram +system.membus.snoop_fanout::samples 7312 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7306 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7312 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7306 # Request fanout histogram -system.membus.reqLayer0.occupancy 9226230 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7312 # Request fanout histogram +system.membus.reqLayer0.occupancy 9348857 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38266679 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38261400 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index cfbe2044c..b10e642ea 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235405500 # Number of ticks simulated -final_tick 517235405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 517235407500 # Number of ticks simulated +final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 520716 # Simulator instruction rate (inst/s) -host_op_rate 625139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 987510163 # Simulator tick rate (ticks/s) -host_mem_usage 313820 # Number of bytes of host memory used -host_seconds 523.78 # Real time elapsed on the host +host_inst_rate 785915 # Simulator instruction rate (inst/s) +host_op_rate 943520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1490444540 # Simulator tick rate (ticks/s) +host_mem_usage 321320 # Number of bytes of host memory used +host_seconds 347.03 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470811 # number of cpu cycles simulated +system.cpu.numCycles 1034470815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470810.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445034 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445034 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -251,12 +251,12 @@ system.cpu.dcache.overall_misses::cpu.data 4479 # system.cpu.dcache.overall_misses::total 4479 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235818500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235818500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235818500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235818500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -283,12 +283,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.098302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52685.098302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52649.810225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52649.810225 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75951500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75951500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229066000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 229066000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229226500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 229226500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47380.848409 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47380.848409 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51187.932961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51187.932961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51189.481912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51189.481912 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007655 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007655 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312482000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312482000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312482000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312482000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312482000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312482000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.046081 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20027.046081 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.046081 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20027.046081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.046081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20027.046081 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289077500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 289077500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289077500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 289077500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289077500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 289077500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18527.046081 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18527.046081 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18527.046081 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18527.046081 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18527.046081 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18527.046081 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.765010 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623059 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714789 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy @@ -453,78 +453,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12995 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 238 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits system.cpu.l2cache.overall_hits::total 13249 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2608 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1368 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137027000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 72007000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137027000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 222081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137027000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 222081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150075000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 150075000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137027500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 137027500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 72007000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 72007000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137027500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 222082000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359109500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137027500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 222082000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359109500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851806 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.027607 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.695906 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.027607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.112689 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.027607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.112689 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.268908 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.268908 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52541.219325 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52541.219325 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52636.695906 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52636.695906 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52562.865925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52562.865925 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -533,84 +539,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2608 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1368 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105625000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55404000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105625000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105625000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171072000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 121515000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 121515000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 110947500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 110947500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58327000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58327000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110947500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 179842000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 290789500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110947500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 179842000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 290789500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42547.268908 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42547.268908 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42541.219325 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42541.219325 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42636.695906 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42636.695906 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) @@ -626,9 +638,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7261500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34588500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index efccfaef5..f751a40d2 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.561049 # Number of seconds simulated -sim_ticks 561048999000 # Number of ticks simulated -final_tick 561048999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.560940 # Number of seconds simulated +sim_ticks 560939897000 # Number of ticks simulated +final_tick 560939897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 327042 # Simulator instruction rate (inst/s) -host_op_rate 327042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197554566 # Simulator tick rate (ticks/s) -host_mem_usage 305844 # Number of bytes of host memory used -host_seconds 2839.97 # Real time elapsed on the host +host_inst_rate 309766 # Simulator instruction rate (inst/s) +host_op_rate 309766 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187082277 # Simulator tick rate (ticks/s) +host_mem_usage 305868 # Number of bytes of host memory used +host_seconds 2998.36 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory -system.physmem.bytes_read::total 18657344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 186880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18514240 # Number of bytes read from this memory +system.physmem.bytes_read::total 18701120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186880 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289285 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292205 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32921189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33254393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7606665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7606665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7606665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32921189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40861059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291521 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 333155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33005746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33338902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7608145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7608145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7608145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33005746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40947046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292205 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292205 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18657344 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18680832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18701120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17937 # Per bank write bursts -system.physmem.perBankRdBursts::1 18285 # Per bank write bursts -system.physmem.perBankRdBursts::2 18301 # Per bank write bursts -system.physmem.perBankRdBursts::3 18253 # Per bank write bursts -system.physmem.perBankRdBursts::4 18160 # Per bank write bursts -system.physmem.perBankRdBursts::5 18247 # Per bank write bursts -system.physmem.perBankRdBursts::6 18325 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18224 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18384 # Per bank write bursts -system.physmem.perBankRdBursts::12 18260 # Per bank write bursts -system.physmem.perBankRdBursts::13 18042 # Per bank write bursts -system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18099 # Per bank write bursts +system.physmem.perBankRdBursts::0 18030 # Per bank write bursts +system.physmem.perBankRdBursts::1 18359 # Per bank write bursts +system.physmem.perBankRdBursts::2 18394 # Per bank write bursts +system.physmem.perBankRdBursts::3 18343 # Per bank write bursts +system.physmem.perBankRdBursts::4 18248 # Per bank write bursts +system.physmem.perBankRdBursts::5 18243 # Per bank write bursts +system.physmem.perBankRdBursts::6 18313 # Per bank write bursts +system.physmem.perBankRdBursts::7 18291 # Per bank write bursts +system.physmem.perBankRdBursts::8 18223 # Per bank write bursts +system.physmem.perBankRdBursts::9 18225 # Per bank write bursts +system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18128 # Per bank write bursts +system.physmem.perBankRdBursts::14 18060 # Per bank write bursts +system.physmem.perBankRdBursts::15 18185 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4188 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 561048916000 # Total gap between requests +system.physmem.totGap 560939815000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291521 # Read request sizes (log2) +system.physmem.readPktSize::6 292205 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,117 +193,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 217.703657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.847395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 266.018983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39852 37.88% 37.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43676 41.51% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8737 8.30% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 846 0.80% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1608 1.53% 90.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1088 1.03% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 546 0.52% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 586 0.56% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8270 7.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105209 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4041 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.193764 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.202156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.629260 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4034 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4041 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.496907 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.475096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.865198 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3038 75.18% 75.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1001 24.77% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4041 # Writes before turning the bus around for reads -system.physmem.totQLat 2859634000 # Total ticks spent queuing -system.physmem.totMemAccLat 8320309000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9818.96 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 103977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 220.682651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.922946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 267.989820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 38271 36.81% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43979 42.30% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8888 8.55% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 756 0.73% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1408 1.35% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1167 1.12% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 628 0.60% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 577 0.55% 92.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8303 7.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103977 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.413929 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.545155 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 755.096124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 3 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.442765 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.845366 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3112 76.86% 76.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 934 23.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads +system.physmem.totQLat 2918754250 # Total ticks spent queuing +system.physmem.totMemAccLat 8391654250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9999.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28568.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.25 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28749.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 202235 # Number of row buffer hits during reads -system.physmem.writeRowHits 50448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.65 # Row buffer hit rate for writes -system.physmem.avgGap 1566283.22 # Average gap between requests -system.physmem.pageHitRate 70.60 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 396718560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 216463500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1137021600 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing +system.physmem.readRowHits 202534 # Number of row buffer hits during reads +system.physmem.writeRowHits 52030 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes +system.physmem.avgGap 1562994.07 # Average gap between requests +system.physmem.pageHitRate 70.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 391812120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 213786375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140274200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109036341675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240981860250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388629643425 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.687306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 400213963500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18734560000 # Time in different power states +system.physmem_0.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 109227211875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240749028000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388576230570 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.726692 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 399826633250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142097780250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142379745750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 398601000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 217490625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134307200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109322809425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240730572750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388664124600 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.748765 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399791677000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18734560000 # Time in different power states +system.physmem_1.actEnergy 394193520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 215085750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136148000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215524800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 109501586505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240508346250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388608564345 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.784339 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399420466000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 142520871000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 142786637000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749073 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144364 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157127 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103970968 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513050 # Number of BTB hits +system.cpu.branchPred.lookups 125749081 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144339 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157133 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103971313 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513402 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.323432 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.323504 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691072 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9449 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237538495 # DTB read hits +system.cpu.dtb.read_hits 237538494 # DTB read hits system.cpu.dtb.read_misses 198467 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736962 # DTB read accesses -system.cpu.dtb.write_hits 98305062 # DTB write hits -system.cpu.dtb.write_misses 7206 # DTB write misses +system.cpu.dtb.read_accesses 237736961 # DTB read accesses +system.cpu.dtb.write_hits 98305022 # DTB write hits +system.cpu.dtb.write_misses 7216 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312268 # DTB write accesses -system.cpu.dtb.data_hits 335843557 # DTB hits -system.cpu.dtb.data_misses 205673 # DTB misses +system.cpu.dtb.write_accesses 98312238 # DTB write accesses +system.cpu.dtb.data_hits 335843516 # DTB hits +system.cpu.dtb.data_misses 205683 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336049230 # DTB accesses -system.cpu.itb.fetch_hits 316986664 # ITB hits +system.cpu.dtb.data_accesses 336049199 # DTB accesses +system.cpu.itb.fetch_hits 316987000 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316986784 # ITB accesses +system.cpu.itb.fetch_accesses 316987120 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,67 +319,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1122097998 # number of cpu cycles simulated +system.cpu.numCycles 1121879794 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30863568 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30863449 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.208130 # CPI: cycles per instruction -system.cpu.ipc 0.827726 # IPC: instructions per cycle -system.cpu.tickCycles 1059712720 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62385278 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.207895 # CPI: cycles per instruction +system.cpu.ipc 0.827887 # IPC: instructions per cycle +system.cpu.tickCycles 1059714780 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62165014 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.688853 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322867255 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.723334 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322867251 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599378 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 907886250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.688853 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999192 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999192 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 413.599373 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 899878500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.723334 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999200 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999200 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648213290 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648213290 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224703202 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224703202 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164053 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322867255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322867255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322867255 # number of overall hits -system.cpu.dcache.overall_hits::total 322867255 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648213288 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648213288 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224703201 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224703201 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164050 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164050 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322867251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322867251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322867251 # number of overall hits +system.cpu.dcache.overall_hits::total 322867251 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137147 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849076 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849076 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849076 # number of overall misses -system.cpu.dcache.overall_misses::total 849076 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24858122500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24858122500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10112031250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10112031250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34970153750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34970153750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34970153750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34970153750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225415131 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225415131 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137150 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849079 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849079 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849079 # number of overall misses +system.cpu.dcache.overall_misses::total 849079 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24888612000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24888612000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9943107500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9943107500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34831719500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34831719500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34831719500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34831719500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225415130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225415130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323716331 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323716331 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323716331 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323716331 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 323716330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323716330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323716330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323716330 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -386,14 +388,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34916.575248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34916.575248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73731.333897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73731.333897 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41186.129098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41186.129098 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.401850 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.401850 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72498.049581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72498.049581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41022.943095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41022.943095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,16 +404,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks -system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88848 # number of writebacks +system.cpu.dcache.writebacks::total 88848 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68136 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68136 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68448 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68448 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68448 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68448 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68139 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68139 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68451 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68451 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68451 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68451 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -420,14 +422,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23712269000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23712269000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5006644750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5006644750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28718913750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28718913750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28718913750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28718913750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24170012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24170012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4987370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4987370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29157382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29157382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29157382500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29157382500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -436,24 +438,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33321.673035 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33321.673035 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72548.503137 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72548.503137 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33964.917224 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33964.917224 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72269.203460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72269.203460 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37351.187121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37351.187121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37351.187121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37351.187121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10608 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.311703 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316974313 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25665.936275 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10610 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.330189 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316974647 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12352 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25661.807562 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.311703 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823394 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.330189 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823403 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id @@ -461,44 +463,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633985678 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633985678 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316974313 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316974313 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316974313 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316974313 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316974313 # number of overall hits -system.cpu.icache.overall_hits::total 316974313 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses -system.cpu.icache.overall_misses::total 12351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 355440500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 355440500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 355440500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 355440500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 355440500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 355440500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316986664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316986664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316986664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316986664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316986664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316986664 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 633986352 # Number of tag accesses +system.cpu.icache.tags.data_accesses 633986352 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 316974647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 316974647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 316974647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 316974647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 316974647 # number of overall hits +system.cpu.icache.overall_hits::total 316974647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12353 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12353 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12353 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12353 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12353 # number of overall misses +system.cpu.icache.overall_misses::total 12353 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352286000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352286000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352286000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352286000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352286000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352286000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 316987000 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 316987000 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 316987000 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 316987000 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 316987000 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 316987000 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28778.277063 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28778.277063 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28778.277063 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28778.277063 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28518.254675 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28518.254675 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28518.254675 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28518.254675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28518.254675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28518.254675 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,123 +509,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 335642500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 335642500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 335642500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 335642500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335642500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 335642500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12353 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12353 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12353 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12353 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12353 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12353 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339934000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 339934000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339934000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 339934000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339934000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 339934000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27175.329933 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27175.329933 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27518.335627 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27518.335627 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258742 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32592.002895 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 523848 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291478 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.797213 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259426 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32593.023927 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218366 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292162 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.170173 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2882.733111 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.797304 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29624.472480 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087974 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002588 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.904067 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.520333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.221668 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29919.281926 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.079026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002570 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.913064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29475 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7436233 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7436233 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 9429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 499091 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 13002157 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13002157 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 88848 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 88848 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9429 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501457 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9429 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits -system.cpu.l2cache.overall_hits::total 501457 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2922 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 222370000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 222370000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17968315500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17968315500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 222370000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22827298500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23049668500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 222370000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22827298500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23049668500 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792979 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12351 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792981 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12353 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792979 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236580 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310617 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 792981 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236580 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.367629 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236580 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.367629 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76758.384668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80463.102881 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80414.964625 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73715.406257 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73715.406257 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76758.384668 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78904.889986 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78883.375011 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76758.384668 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78904.889986 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78883.375011 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.236461 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.236461 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312865 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312865 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236461 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368491 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236461 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368491 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.440243 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.440243 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76128.038343 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76128.038343 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80705.693047 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80705.693047 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76128.038343 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78909.374838 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78881.571563 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76128.038343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78909.374838 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78881.571563 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,103 +642,114 @@ system.cpu.l2cache.fast_writes 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19351356750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187662000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19163694750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19351356750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310617 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222640 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15741915500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15741915500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193170000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19934448500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20127618500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193170000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19934448500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20127618500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # 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mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.236461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368491 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368491 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62908.440243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62908.440243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66131.461828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66131.461828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70705.693047 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70705.693047 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 891037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711617 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337788 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2373103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55646464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56436992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259426 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1839549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1580123 85.90% 85.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 259426 14.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533723000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19161500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1839549 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 878909500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18528000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222147750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170942000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224876 # Transaction distribution -system.membus.trans_dist::ReadResp 224876 # Transaction distribution +system.membus.trans_dist::ReadResp 225560 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191116 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649725 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649725 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22925056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22925056 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225560 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842209 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22968832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22968832 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358204 # Request fanout histogram +system.membus.snoop_fanout::samples 550004 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358204 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 550004 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358204 # Request fanout histogram -system.membus.reqLayer0.occupancy 732288500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1552393250 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 550004 # Request fanout histogram +system.membus.reqLayer0.occupancy 918579000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1556120750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 887940ec1..7d418bd2e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279669 # Number of seconds simulated -sim_ticks 279668927000 # Number of ticks simulated -final_tick 279668927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279557 # Number of seconds simulated +sim_ticks 279556845500 # Number of ticks simulated +final_tick 279556845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172383 # Simulator instruction rate (inst/s) -host_op_rate 172383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57230702 # Simulator tick rate (ticks/s) -host_mem_usage 232716 # Number of bytes of host memory used -host_seconds 4886.69 # Real time elapsed on the host +host_inst_rate 180071 # Simulator instruction rate (inst/s) +host_op_rate 180071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59759118 # Simulator tick rate (ticks/s) +host_mem_usage 307148 # Number of bytes of host memory used +host_seconds 4678.06 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18476288 # Number of bytes read from this memory -system.physmem.bytes_read::total 18652544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520448 # Number of bytes read from this memory +system.physmem.bytes_read::total 18696768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176320 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288692 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289382 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292137 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 630231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66064858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 66695089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 630231 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 630231 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15259872 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15259872 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15259872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 630231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66064858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 81954961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291446 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 630713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66249310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 66880022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 630713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 630713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15265990 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15265990 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15265990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 630713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66249310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82146012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292137 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292137 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18633664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18652544 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18678144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265920 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18696768 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17911 # Per bank write bursts -system.physmem.perBankRdBursts::1 18258 # Per bank write bursts -system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18250 # Per bank write bursts -system.physmem.perBankRdBursts::4 18158 # Per bank write bursts -system.physmem.perBankRdBursts::5 18224 # Per bank write bursts -system.physmem.perBankRdBursts::6 18321 # Per bank write bursts -system.physmem.perBankRdBursts::7 18307 # Per bank write bursts -system.physmem.perBankRdBursts::8 18228 # Per bank write bursts +system.physmem.perBankRdBursts::0 18015 # Per bank write bursts +system.physmem.perBankRdBursts::1 18332 # Per bank write bursts +system.physmem.perBankRdBursts::2 18407 # Per bank write bursts +system.physmem.perBankRdBursts::3 18336 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18230 # Per bank write bursts +system.physmem.perBankRdBursts::6 18323 # Per bank write bursts +system.physmem.perBankRdBursts::7 18299 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts system.physmem.perBankRdBursts::9 18222 # Per bank write bursts -system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::10 18209 # Per bank write bursts system.physmem.perBankRdBursts::11 18393 # Per bank write bursts -system.physmem.perBankRdBursts::12 18247 # Per bank write bursts -system.physmem.perBankRdBursts::13 18043 # Per bank write bursts -system.physmem.perBankRdBursts::14 17966 # Per bank write bursts -system.physmem.perBankRdBursts::15 18104 # Per bank write bursts +system.physmem.perBankRdBursts::12 18246 # Per bank write bursts +system.physmem.perBankRdBursts::13 18127 # Per bank write bursts +system.physmem.perBankRdBursts::14 18048 # Per bank write bursts +system.physmem.perBankRdBursts::15 18184 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6 4262 # Pe system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts system.physmem.perBankWrBursts::9 4180 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts +system.physmem.perBankWrBursts::10 4149 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 279668837500 # Total gap between requests +system.physmem.totGap 279556756000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291446 # Read request sizes (log2) +system.physmem.readPktSize::6 292137 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -193,117 +193,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 228.091007 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.320458 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.791024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35777 35.64% 35.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42525 42.36% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10061 10.02% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 470 0.47% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 508 0.51% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 391 0.39% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 492 0.49% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1510 1.50% 91.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8654 8.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100388 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.235658 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.129419 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 756.508896 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.482690 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.461191 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3072 75.96% 75.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 964 23.84% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 8 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 3601508250 # Total ticks spent queuing -system.physmem.totMemAccLat 9060589500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12369.90 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 99332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.959771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.026626 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.596004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 34426 34.66% 34.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42079 42.36% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10100 10.17% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 831 0.84% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1119 1.13% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 640 0.64% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 198 0.20% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1366 1.38% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8573 8.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 99332 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4052 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.011846 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.507282 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 732.804018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4044 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4052 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.449901 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.429330 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.841533 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3145 77.62% 77.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 903 22.29% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4052 # Writes before turning the bus around for reads +system.physmem.totQLat 3589265250 # Total ticks spent queuing +system.physmem.totMemAccLat 9061377750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12298.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31119.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 66.70 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31048.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 66.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 206952 # Number of row buffer hits during reads -system.physmem.writeRowHits 50458 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 780916.48 # Average gap between requests -system.physmem.pageHitRate 71.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378650160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206604750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136467800 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing +system.physmem.readRowHits 207190 # Number of row buffer hits during reads +system.physmem.writeRowHits 51966 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.93 # Row buffer hit rate for writes +system.physmem.avgGap 779100.26 # Average gap between requests +system.physmem.pageHitRate 72.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 374756760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204480375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139564400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79892908290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97718574000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 197816101560 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.327829 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 162042939000 # Time in different power states -system.physmem_0.memoryStateTime::REF 9338680000 # Time in different power states +system.physmem_0.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80335161315 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97260556500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 197789787510 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.529215 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 161282435500 # Time in different power states +system.physmem_0.memoryStateTime::REF 9334780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108285182250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108932951500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 380207520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 207454500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80233432560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 97419868500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 197857002360 # Total energy per rank (pJ) -system.physmem_1.averagePower 707.474077 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 161543146250 # Time in different power states -system.physmem_1.memoryStateTime::REF 9338680000 # Time in different power states +system.physmem_1.actEnergy 375943680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 205128000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1135750200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215485920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80056140615 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 97505311500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 197752589595 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.396151 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 161684152500 # Time in different power states +system.physmem_1.memoryStateTime::REF 9334780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108784975000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108531075000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192995150 # Number of BP lookups -system.cpu.branchPred.condPredicted 125739221 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11883936 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 145375032 # Number of BTB lookups -system.cpu.branchPred.BTBHits 127081867 # Number of BTB hits +system.cpu.branchPred.lookups 192642813 # Number of BP lookups +system.cpu.branchPred.condPredicted 125666016 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11886398 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 146763457 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126951211 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.416570 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 29018342 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 86.500559 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 29013974 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 143 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244533779 # DTB read hits -system.cpu.dtb.read_misses 309591 # DTB read misses +system.cpu.dtb.read_hits 244534581 # DTB read hits +system.cpu.dtb.read_misses 309538 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244843370 # DTB read accesses -system.cpu.dtb.write_hits 135671849 # DTB write hits -system.cpu.dtb.write_misses 31346 # DTB write misses +system.cpu.dtb.read_accesses 244844119 # DTB read accesses +system.cpu.dtb.write_hits 135677576 # DTB write hits +system.cpu.dtb.write_misses 31395 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135703195 # DTB write accesses -system.cpu.dtb.data_hits 380205628 # DTB hits -system.cpu.dtb.data_misses 340937 # DTB misses +system.cpu.dtb.write_accesses 135708971 # DTB write accesses +system.cpu.dtb.data_hits 380212157 # DTB hits +system.cpu.dtb.data_misses 340933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380546565 # DTB accesses -system.cpu.itb.fetch_hits 197011138 # ITB hits -system.cpu.itb.fetch_misses 297 # ITB misses +system.cpu.dtb.data_accesses 380553090 # DTB accesses +system.cpu.itb.fetch_hits 197116758 # ITB hits +system.cpu.itb.fetch_misses 277 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 197011435 # ITB accesses +system.cpu.itb.fetch_accesses 197117035 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,238 +320,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 559337855 # number of cpu cycles simulated +system.cpu.numCycles 559113692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202154435 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1649182914 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192995150 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156100209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 344813807 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24235896 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6519 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 197011138 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7083229 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 559092875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.175515 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202267120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648589560 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192642813 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155965185 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 344477338 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24241354 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6562 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 197116758 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7079440 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 558871871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.174628 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 239653225 42.86% 42.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30449692 5.45% 48.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22058642 3.95% 52.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36467190 6.52% 58.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 68017058 12.17% 70.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21431579 3.83% 74.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19299153 3.45% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3537365 0.63% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118178971 21.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 239606568 42.87% 42.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30232310 5.41% 48.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22062681 3.95% 52.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36416175 6.52% 58.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 68096392 12.18% 70.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21641580 3.87% 74.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299985 3.45% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3539455 0.63% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 117976725 21.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 559092875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345042 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.948456 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168803167 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 91739479 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273671215 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12767829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12111185 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15522167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 6976 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1584668893 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12111185 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176688622 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61751221 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14050 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278532777 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29995020 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538585292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9438 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2658750 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 20386888 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7267964 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1027382191 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1769248125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1729530138 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39717986 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 558871871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344550 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.948577 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168941255 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 91534254 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273571884 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12710570 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12113908 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15306458 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 6991 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1583914254 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25227 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12113908 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176800339 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61738556 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14140 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278402636 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29802292 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538072104 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9577 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2573672 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20322038 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7208635 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1027250775 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1768837330 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1729119220 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39718109 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 388415033 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9495582 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372551032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175434243 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40723012 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11258595 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304972518 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1016009395 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8790765 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462590577 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427723515 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 559092875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.817246 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.904787 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 388283617 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1370 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9395851 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372336921 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175495034 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40680070 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11286315 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304559063 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1015639240 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8789930 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462177116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427685030 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 558871871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.817302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.903889 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 200119998 35.79% 35.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93029621 16.64% 52.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91384631 16.35% 68.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59843024 10.70% 79.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56522593 10.11% 89.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29852885 5.34% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17077557 3.05% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7239227 1.29% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4023339 0.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 199951896 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 92994240 16.64% 52.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91399550 16.35% 68.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59708328 10.68% 79.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56828177 10.17% 89.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29755879 5.32% 94.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17031836 3.05% 98.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7177923 1.28% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4024042 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 559092875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 558871871 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2463450 10.43% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15566876 65.90% 76.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5592414 23.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464205 10.45% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15633751 66.29% 76.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5485030 23.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579702610 57.06% 57.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7931 0.00% 57.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13180646 1.30% 58.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826544 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339801 0.33% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 277022873 27.27% 86.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138927710 13.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579358124 57.04% 57.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7924 0.00% 57.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13180764 1.30% 58.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339800 0.33% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276992447 27.27% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138932359 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1016009395 # Type of FU issued -system.cpu.iq.rate 1.816450 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23622740 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023251 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2552720615 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1726519951 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940123896 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70804555 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41088367 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34423394 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1003270759 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36360100 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50476055 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015639240 # Type of FU issued +system.cpu.iq.rate 1.816516 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23582986 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023220 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2551718253 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1725674688 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 939925074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70805014 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41106869 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34423614 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002860612 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36360338 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50469534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 135040435 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1174528 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45615 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77133043 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 134826324 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1160001 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45767 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77193834 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2509 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4123 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2684 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4171 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12111185 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60760024 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 216464 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479434002 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17901 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372551032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175434243 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 87 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21559 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 205996 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45615 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11877701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16644 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11894345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976302878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244843546 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39706517 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12113908 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60768232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 187260 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479124792 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 20793 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372336921 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175495034 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15841 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 182755 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45767 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11880363 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16467 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11896830 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976089984 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244844291 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39549256 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174461395 # number of nop insts executed -system.cpu.iew.exec_refs 380547191 # number of memory reference insts executed -system.cpu.iew.exec_branches 129259483 # Number of branches executed -system.cpu.iew.exec_stores 135703645 # Number of stores executed -system.cpu.iew.exec_rate 1.745462 # Inst execution rate -system.cpu.iew.wb_sent 975066188 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974547290 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556173359 # num instructions producing a value -system.cpu.iew.wb_consumers 831980820 # num instructions consuming a value +system.cpu.iew.exec_nop 174565646 # number of nop insts executed +system.cpu.iew.exec_refs 380553668 # number of memory reference insts executed +system.cpu.iew.exec_branches 129052167 # Number of branches executed +system.cpu.iew.exec_stores 135709377 # Number of stores executed +system.cpu.iew.exec_rate 1.745781 # Inst execution rate +system.cpu.iew.wb_sent 974867255 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974348688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556190036 # num instructions producing a value +system.cpu.iew.wb_consumers 832343662 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.742323 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668493 # average fanout of values written-back +system.cpu.iew.wb_rate 1.742666 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668222 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543601549 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543293982 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11877174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 486379014 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.909185 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.596644 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11879630 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 486147412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.910095 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.597279 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 208258289 42.82% 42.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102386957 21.05% 63.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51676822 10.62% 74.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25636051 5.27% 79.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21554637 4.43% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9250657 1.90% 86.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10396507 2.14% 88.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6664753 1.37% 89.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50554341 10.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 208054375 42.80% 42.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102342395 21.05% 63.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51700065 10.63% 74.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25702081 5.29% 79.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21547094 4.43% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9129205 1.88% 86.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10401484 2.14% 88.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6670149 1.37% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50600564 10.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 486379014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 486147412 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -594,345 +597,335 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50554341 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1905392712 # The number of ROB reads -system.cpu.rob.rob_writes 3017093514 # The number of ROB writes -system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 244980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 50600564 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1904807320 # The number of ROB reads +system.cpu.rob.rob_writes 3016488956 # The number of ROB writes +system.cpu.timesIdled 3196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 241821 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.663995 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.663995 # CPI: Total CPI of All Threads -system.cpu.ipc 1.506034 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.506034 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237178642 # number of integer regfile reads -system.cpu.int_regfile_writes 705781417 # number of integer regfile writes -system.cpu.fp_regfile_reads 36689419 # number of floating regfile reads -system.cpu.fp_regfile_writes 24410667 # number of floating regfile writes +system.cpu.cpi 0.663729 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.663729 # CPI: Total CPI of All Threads +system.cpu.ipc 1.506638 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.506638 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237184723 # number of integer regfile reads +system.cpu.int_regfile_writes 705784215 # number of integer regfile writes +system.cpu.fp_regfile_reads 36689750 # number of floating regfile reads +system.cpu.fp_regfile_writes 24410793 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777209 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.895157 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289903947 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781305 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 371.050930 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 374093250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.895157 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777216 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.910211 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289913128 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781312 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 371.059357 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 371553500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.910211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999246 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999246 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2498 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 253 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585486411 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585486411 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192496951 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192496951 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97406971 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97406971 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289903922 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289903922 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289903922 # number of overall hits -system.cpu.dcache.overall_hits::total 289903922 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554376 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554376 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 894229 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 894229 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2448605 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2448605 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2448605 # number of overall misses -system.cpu.dcache.overall_misses::total 2448605 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84529453750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84529453750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62304618080 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62304618080 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 100250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 100250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 146834071830 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 146834071830 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 146834071830 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 146834071830 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194051327 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194051327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 585500596 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585500596 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192503314 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192503314 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97409790 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97409790 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 24 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 24 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289913104 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289913104 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289913104 # number of overall hits +system.cpu.dcache.overall_hits::total 289913104 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1555104 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1555104 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 891410 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 891410 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2446514 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2446514 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2446514 # number of overall misses +system.cpu.dcache.overall_misses::total 2446514 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83796204000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83796204000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61715896841 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61715896841 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145512100841 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145512100841 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145512100841 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145512100841 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194058418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194058418 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 26 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 26 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292352527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292352527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292352527 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292352527 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009097 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038462 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038462 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008376 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008376 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008376 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008376 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54381.599915 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54381.599915 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69674.119359 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69674.119359 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 100250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 100250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59966.418361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59966.418361 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21964 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 69527 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292359618 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292359618 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292359618 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292359618 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008014 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008014 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009068 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008368 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008368 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008368 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008368 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53884.630224 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53884.630224 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69234.018960 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69234.018960 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59477.321953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59477.321953 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 67906 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 515 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.034985 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 135.003883 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.164265 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131.856311 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91524 # number of writebacks -system.cpu.dcache.writebacks::total 91524 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 841911 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 841911 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 825390 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 825390 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1667301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1667301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1667301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1667301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712465 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712465 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68839 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68839 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781304 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781304 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781304 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781304 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23794966500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23794966500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5675142998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5675142998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29470109498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29470109498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29470109498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29470109498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 88850 # number of writebacks +system.cpu.dcache.writebacks::total 88850 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842619 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842619 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 822583 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 822583 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1665202 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1665202 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1665202 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1665202 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781312 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781312 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781312 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781312 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24145312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24145312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5651970498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5651970498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29797282498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29797282498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29797282498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29797282498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038462 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.038462 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33398.084818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33398.084818 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82440.811139 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82440.811139 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33888.870643 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33888.870643 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82118.507243 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82118.507243 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4665 # number of replacements -system.cpu.icache.tags.tagsinuse 1651.262169 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 197002801 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6374 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30907.248353 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4695 # number of replacements +system.cpu.icache.tags.tagsinuse 1651.888032 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 197108400 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6404 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30778.950656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1651.262169 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.806280 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1651.888032 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.806586 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.806586 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1547 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 394028650 # Number of tag accesses -system.cpu.icache.tags.data_accesses 394028650 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 197002801 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 197002801 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 197002801 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 197002801 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 197002801 # number of overall hits -system.cpu.icache.overall_hits::total 197002801 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8337 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8337 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8337 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8337 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8337 # number of overall misses -system.cpu.icache.overall_misses::total 8337 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 359956749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 359956749 # 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number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354830499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354830499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354830499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354830499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354830499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354830499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 197116758 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 197116758 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 197116758 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 197116758 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 197116758 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 197116758 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43175.812522 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43175.812522 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43175.812522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43175.812522 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 938 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42453.996052 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42453.996052 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42453.996052 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42453.996052 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 620 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.533333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.363636 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1962 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1962 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1962 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1962 # 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number of cycles access was blocked @@ -943,103 +936,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222064 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224819 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 405 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 405 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66628 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66628 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288692 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288692 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291447 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 185539750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15158114250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15343654000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4753161750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4753161750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 185539750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19911276000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20096815750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 185539750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19911276000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20096815750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311684 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312752 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370007 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370007 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67346.551724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68260.115327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68248.920243 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71338.802756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71338.802756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2756 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2756 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222754 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222754 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2756 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289382 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2756 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289382 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292138 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4859074500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4859074500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192753000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192753000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15700662500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15700662500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192753000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20559737000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20752490000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192753000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20559737000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20752490000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.968050 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.968050 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430289 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312644 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312644 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370867 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370867 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72928.415981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72928.415981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69939.404935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69939.404935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70484.312291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70484.312291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69939.404935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71047.048538 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71036.599142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69939.404935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71047.048538 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71036.599142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 718841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68839 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68839 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666883 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56268992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879204 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 718889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 885737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339840 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2357344 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55690368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56100224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259359 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1828987 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879204 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1569628 85.82% 85.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 259359 14.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879204 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531126000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10103500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1828987 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 873664000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 9606000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1213595000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171968000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224818 # Transaction distribution -system.membus.trans_dist::ReadResp 224818 # Transaction distribution +system.membus.trans_dist::ReadResp 225509 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191067 # Transaction distribution system.membus.trans_dist::ReadExReq 66628 # Transaction distribution system.membus.trans_dist::ReadExResp 66628 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649575 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649575 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920256 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225509 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842024 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842024 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22964480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358129 # Request fanout histogram +system.membus.snoop_fanout::samples 549887 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358129 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549887 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358129 # Request fanout histogram -system.membus.reqLayer0.occupancy 682357500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1548216750 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 549887 # Request fanout histogram +system.membus.reqLayer0.occupancy 853984000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551628500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index eff48cf7e..07561ac8e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.286250 # Number of seconds simulated -sim_ticks 1286249817500 # Number of ticks simulated -final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.286279 # Number of seconds simulated +sim_ticks 1286278511500 # Number of ticks simulated +final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1412500 # Simulator instruction rate (inst/s) -host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1956550284 # Simulator tick rate (ticks/s) -host_mem_usage 303116 # Number of bytes of host memory used -host_seconds 657.41 # Real time elapsed on the host +host_inst_rate 1355944 # Simulator instruction rate (inst/s) +host_op_rate 1355944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1878251411 # Simulator tick rate (ticks/s) +host_mem_usage 303804 # Number of bytes of host memory used +host_seconds 684.83 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory -system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18509184 # Number of bytes read from this memory +system.physmem.bytes_read::total 18646976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289206 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291359 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14389717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14496842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3317876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3317876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3317876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14389717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17814717 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572499635 # number of cpu cycles simulated +system.cpu.numCycles 2572557023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572499635 # Number of busy cycles +system.cpu.num_busy_cycles 2572557023 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -129,12 +129,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4094.261358 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 1046537500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261358 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18597166000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18597166000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696410000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696410000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22293576000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22293576000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22293576000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22293576000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) @@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26137.456185 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26137.456185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.292115 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.292115 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28562.173298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28562.173298 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks -system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.writebacks::writebacks 89031 # number of writebacks +system.cpu.dcache.writebacks::total 89031 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses @@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528 system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17885652000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17885652000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3627396000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3627396000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21513048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21513048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21513048000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21513048000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -228,22 +228,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25137.456185 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25137.456185 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52560.292115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52560.292115 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.486224 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486224 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id @@ -266,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170684500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170684500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170684500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170684500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170684500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170684500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -284,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27672.584306 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27672.584306 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27672.584306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27672.584306 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,38 +304,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164516500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 164516500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164516500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 164516500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164516500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 164516500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26672.584306 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26672.584306 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257900 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258580 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32657.927159 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207050 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291314 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.143467 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2486.879631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.811890 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30121.235638 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.075894 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001520 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.919227 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996641 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id @@ -343,78 +343,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7386496 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7386496 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 4015 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 489636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 493651 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91660 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91660 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 12902296 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12902296 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 89031 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 89031 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4015 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4015 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488956 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488956 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 91660 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 91660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 289206 # number of overall misses +system.cpu.l2cache.overall_misses::total 291359 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499032000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3499032000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 113105000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 113105000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11684343000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11684343000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 113105000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15183375000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15296480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 113105000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15183375000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15296480000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 89031 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 89031 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.312159 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.349060 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312795 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312795 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369655 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.369493 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370526 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370526 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.180050 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.180050 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52533.673943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52533.673943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.215674 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.215674 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.454765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.454765 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -425,103 +431,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221878 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224031 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 238 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 238 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2153 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2153 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222558 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222558 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288526 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290679 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289206 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291359 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289206 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291359 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2832552000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2832552000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91575000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91575000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9458763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9458763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91575000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12291315000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12382890000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91575000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12291315000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12382890000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.349060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312795 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312795 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.180050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.180050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42533.673943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42533.673943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.215674 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.215674 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 878356 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55651776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258580 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141585 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348624 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 878356 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1567746 85.84% 85.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 258580 14.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 878356 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224031 # Transaction distribution -system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224711 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 190417 # Transaction distribution system.membus.trans_dist::ReadExReq 66648 # Transaction distribution system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224711 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839818 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839818 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22914688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22914688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::samples 548514 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 548514 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 357362 # Request fanout histogram -system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 548514 # Request fanout histogram +system.membus.reqLayer0.occupancy 815261292 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1456808792 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 5b9278fb0..cc0a8b561 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541773 # Number of seconds simulated -sim_ticks 541773299500 # Number of ticks simulated -final_tick 541773299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541068 # Number of seconds simulated +sim_ticks 541067717500 # Number of ticks simulated +final_tick 541067717500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180126 # Simulator instruction rate (inst/s) -host_op_rate 221759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152324877 # Simulator tick rate (ticks/s) -host_mem_usage 323140 # Number of bytes of host memory used -host_seconds 3556.70 # Real time elapsed on the host +host_inst_rate 180313 # Simulator instruction rate (inst/s) +host_op_rate 221989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152283805 # Simulator tick rate (ticks/s) +host_mem_usage 322972 # Number of bytes of host memory used +host_seconds 3553.02 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18429120 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164800 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470272 # Number of bytes read from this memory +system.physmem.bytes_read::total 18635008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164736 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2575 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287955 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2574 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288598 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291172 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 304186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34016294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34320481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 304186 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 304186 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808196 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808196 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 304186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34016294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42128676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290530 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 304465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34136710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34441175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 304465 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 304465 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7818378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7818378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7818378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 304465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34136710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42259553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291172 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290530 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291172 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593920 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18613824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18635008 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18136 # Per bank write bursts -system.physmem.perBankRdBursts::2 18223 # Per bank write bursts -system.physmem.perBankRdBursts::3 18182 # Per bank write bursts -system.physmem.perBankRdBursts::4 18272 # Per bank write bursts -system.physmem.perBankRdBursts::5 18313 # Per bank write bursts -system.physmem.perBankRdBursts::6 18098 # Per bank write bursts -system.physmem.perBankRdBursts::7 17913 # Per bank write bursts -system.physmem.perBankRdBursts::8 17942 # Per bank write bursts -system.physmem.perBankRdBursts::9 17963 # Per bank write bursts -system.physmem.perBankRdBursts::10 18020 # Per bank write bursts -system.physmem.perBankRdBursts::11 18117 # Per bank write bursts -system.physmem.perBankRdBursts::12 18146 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18079 # Per bank write bursts -system.physmem.perBankRdBursts::15 18260 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4100 # Per bank write bursts -system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts -system.physmem.perBankWrBursts::5 4225 # Per bank write bursts -system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankRdBursts::0 18282 # Per bank write bursts +system.physmem.perBankRdBursts::1 18127 # Per bank write bursts +system.physmem.perBankRdBursts::2 18214 # Per bank write bursts +system.physmem.perBankRdBursts::3 18173 # Per bank write bursts +system.physmem.perBankRdBursts::4 18274 # Per bank write bursts +system.physmem.perBankRdBursts::5 18402 # Per bank write bursts +system.physmem.perBankRdBursts::6 18180 # Per bank write bursts +system.physmem.perBankRdBursts::7 17989 # Per bank write bursts +system.physmem.perBankRdBursts::8 18022 # Per bank write bursts +system.physmem.perBankRdBursts::9 18061 # Per bank write bursts +system.physmem.perBankRdBursts::10 18102 # Per bank write bursts +system.physmem.perBankRdBursts::11 18198 # Per bank write bursts +system.physmem.perBankRdBursts::12 18215 # Per bank write bursts +system.physmem.perBankRdBursts::13 18265 # Per bank write bursts +system.physmem.perBankRdBursts::14 18078 # Per bank write bursts +system.physmem.perBankRdBursts::15 18259 # Per bank write bursts +system.physmem.perBankWrBursts::0 4171 # Per bank write bursts +system.physmem.perBankWrBursts::1 4098 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4223 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::7 4092 # Per bank write bursts system.physmem.perBankWrBursts::8 4093 # Per bank write bursts -system.physmem.perBankWrBursts::9 4092 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4095 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4096 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541773205000 # Total gap between requests +system.physmem.totGap 541067624000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290530 # Read request sizes (log2) +system.physmem.readPktSize::6 291172 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,96 +193,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 112123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 203.355529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.415015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 254.574164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47170 42.07% 42.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43612 38.90% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9039 8.06% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1917 1.71% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 483 0.43% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 738 0.66% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 730 0.65% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 502 0.45% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7932 7.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 112123 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.524570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.058155 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.570273 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 110882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.996862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.129754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.860056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45611 41.13% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43911 39.60% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9208 8.30% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1504 1.36% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 772 0.70% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 428 0.39% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 846 0.76% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 594 0.54% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8008 7.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 110882 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.509335 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.234035 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.719748 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.480918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.459590 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.855706 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3046 75.98% 75.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 961 23.97% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads -system.physmem.totQLat 2883248250 # Total ticks spent queuing -system.physmem.totMemAccLat 8324929500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9934.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.446602 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.426400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.833021 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3120 77.67% 77.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 897 22.33% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads +system.physmem.totQLat 3065169000 # Total ticks spent queuing +system.physmem.totMemAccLat 8518437750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10538.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28684.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29288.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.18 # Average write queue length when enqueuing -system.physmem.readRowHits 194064 # Number of row buffer hits during reads -system.physmem.writeRowHits 50094 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 1519154.99 # Average gap between requests -system.physmem.pageHitRate 68.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 423874080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 231280500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1134198000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215622000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107588305125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 230684814750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375663699255 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.403859 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383052702750 # Time in different power states -system.physmem_0.memoryStateTime::REF 18090800000 # Time in different power states +system.physmem.avgWrQLen 28.63 # Average write queue length when enqueuing +system.physmem.readRowHits 194425 # Number of row buffer hits during reads +system.physmem.writeRowHits 51597 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 1514450.20 # Average gap between requests +system.physmem.pageHitRate 68.93 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 420041160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229189125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1135976400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 108869403780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 229140586500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375350562645 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.723181 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 380482098250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18067400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140624192250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142518050750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 423692640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231181500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1129104600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212524560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 107075040930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 231135046500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 375592195530 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.271876 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 383804077000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18090800000 # Time in different power states +system.physmem_1.actEnergy 418226760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228199125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132497600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212576400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 107776907010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230098917000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 375207158295 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.458141 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 382081982750 # Time in different power states +system.physmem_1.memoryStateTime::REF 18067400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 139874284500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 140917403500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 156119313 # Number of BP lookups -system.cpu.branchPred.condPredicted 106151666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12881666 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90098747 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82494804 # Number of BTB hits +system.cpu.branchPred.lookups 157565509 # Number of BP lookups +system.cpu.branchPred.condPredicted 107229273 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12892751 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 98103751 # Number of BTB lookups +system.cpu.branchPred.BTBHits 81778311 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.560434 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19276925 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1327 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.359005 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19318729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1315 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -401,69 +399,69 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083546599 # number of cpu cycles simulated +system.cpu.numCycles 1082135435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23911488 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23942424 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691310 # CPI: cycles per instruction -system.cpu.ipc 0.591258 # IPC: instructions per cycle -system.cpu.tickCycles 1025165387 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58381212 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778275 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.437677 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378454072 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782371 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.727122 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 802618250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.437677 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999130 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999130 # Average percentage of cache occupancy +system.cpu.cpi 1.689108 # CPI: cycles per instruction +system.cpu.ipc 0.592029 # IPC: instructions per cycle +system.cpu.tickCycles 1024380125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57755310 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778330 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.458630 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378454621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782426 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.693820 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 795587500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.458630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999135 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999135 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1345 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1346 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1586 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759393811 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759393811 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249625343 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249625343 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 759395078 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759395078 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249625893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249625893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378439109 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378439109 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378442594 # number of overall hits -system.cpu.dcache.overall_hits::total 378442594 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713796 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713796 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 378439658 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378439658 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378443143 # number of overall hits +system.cpu.dcache.overall_hits::total 378443143 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713852 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713852 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 851507 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851507 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851648 # number of overall misses -system.cpu.dcache.overall_misses::total 851648 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24839025218 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24839025218 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10202615750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10202615750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35041640968 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35041640968 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35041640968 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35041640968 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250339139 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250339139 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 851564 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851564 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851705 # number of overall misses +system.cpu.dcache.overall_misses::total 851705 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24973506500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24973506500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10064105500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10064105500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35037612000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35037612000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35037612000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35037612000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250339745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250339745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) @@ -472,12 +470,12 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379290616 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379290616 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379294242 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379294242 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 379291222 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379291222 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379294848 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379294848 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses @@ -486,14 +484,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34798.493152 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34798.493152 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74087.151716 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74087.151716 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41152.499002 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41152.499002 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41145.685739 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41145.685739 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34984.151477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34984.151477 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73080.817213 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73080.817213 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41145.013176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41145.013176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41138.201607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41138.201607 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,36 +500,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks -system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 886 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 886 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69275 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69275 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69275 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69275 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712910 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712910 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 88940 # number of writebacks +system.cpu.dcache.writebacks::total 88940 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 887 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 887 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69277 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69277 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69277 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69277 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712965 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712965 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782232 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782232 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782371 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782371 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23683196777 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23683196777 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5051765250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5051765250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28734962027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28734962027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28736681027 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28736681027 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782287 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782287 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782426 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782426 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24245308500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24245308500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5047418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5047418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29292727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29292727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29294515000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29294515000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -542,69 +540,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33220.458090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33220.458090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72873.910880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72873.910880 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36734.577500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36734.577500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36730.248216 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36730.248216 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34006.309566 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34006.309566 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72811.207120 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72811.207120 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37444.987581 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37444.987581 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37440.620583 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37440.620583 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23596 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.059457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 290105857 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11445.372510 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23593 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.048816 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 288484492 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11382.752999 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.059457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835967 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835967 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.048816 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1603 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 580287757 # Number of tag accesses -system.cpu.icache.tags.data_accesses 580287757 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 290105857 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 290105857 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 290105857 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 290105857 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 290105857 # number of overall hits -system.cpu.icache.overall_hits::total 290105857 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses -system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 499853745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 499853745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 499853745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 499853745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 499853745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 499853745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290131205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290131205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290131205 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290131205 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290131205 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290131205 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19719.652241 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19719.652241 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19719.652241 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19719.652241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19719.652241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19719.652241 # average overall miss latency +system.cpu.icache.tags.tag_accesses 577045018 # Number of tag accesses +system.cpu.icache.tags.data_accesses 577045018 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 288484492 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288484492 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288484492 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288484492 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288484492 # number of overall hits +system.cpu.icache.overall_hits::total 288484492 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25345 # number of overall misses +system.cpu.icache.overall_misses::total 25345 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499936000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499936000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499936000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499936000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499936000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499936000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288509837 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288509837 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288509837 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288509837 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288509837 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288509837 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19725.231801 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19725.231801 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19725.231801 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19725.231801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19725.231801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19725.231801 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,123 +611,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460727755 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 460727755 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460727755 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 460727755 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460727755 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 460727755 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000088 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18725.271257 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18725.271257 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18725.271257 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18725.271257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18725.271257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18725.271257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257750 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32572.840203 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 539129 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.855904 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258392 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32574.171271 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1245331 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291136 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.277489 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2880.993603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.456847 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29602.389753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087921 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002730 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.903393 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994044 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.797972 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.410409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29893.962890 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.079034 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.912291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994085 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2810 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2812 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29416 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7552928 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7552928 # 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miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76066.156528 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80285.553492 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80237.038473 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74874.275620 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74874.275620 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76066.156528 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79043.681550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79017.232924 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76066.156528 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79043.681550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79017.232924 # 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number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 28 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2576 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221864 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 369 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 369 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2576 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287955 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290531 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2576 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287955 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290531 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15037461500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15201199500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4120172250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4120172250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163738000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19157633750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19321371750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163738000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19157633750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19321371750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311148 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303956 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2575 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2575 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222507 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222507 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288598 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288598 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291173 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4248598000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4248598000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171535500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171535500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15799227000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15799227000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171535500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20047825000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20219360500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171535500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20047825000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20219360500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359693 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359693 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63562.888199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67777.834619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67729.457762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62340.897399 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62340.897399 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101598 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312026 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312026 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64284.062883 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64284.062883 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66615.728155 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66615.728155 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71005.527916 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71005.527916 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 901935 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656162 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706857 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55922624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57544832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899139 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 25345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 713104 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2414122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55767424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57389440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258392 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1868086 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 899139 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1609694 86.17% 86.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 258392 13.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899139 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 540989500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38573245 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1868086 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 893787000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 38017996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224491973 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173652972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224439 # Transaction distribution -system.membus.trans_dist::ReadResp 224439 # Transaction distribution +system.membus.trans_dist::ReadResp 225081 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190637 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647158 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824192 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225081 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839079 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839079 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22865280 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356628 # Request fanout histogram +system.membus.snoop_fanout::samples 547907 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356628 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 547907 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356628 # Request fanout histogram -system.membus.reqLayer0.occupancy 731800000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1550863750 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 547907 # Request fanout histogram +system.membus.reqLayer0.occupancy 916769500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1554235250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index bdaafd38c..95f0885fc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409388 # Number of seconds simulated -sim_ticks 409388416000 # Number of ticks simulated -final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410927 # Number of seconds simulated +sim_ticks 410926760000 # Number of ticks simulated +final_tick 410926760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93306 # Simulator instruction rate (inst/s) -host_op_rate 114872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59624294 # Simulator tick rate (ticks/s) -host_mem_usage 320320 # Number of bytes of host memory used -host_seconds 6866.13 # Real time elapsed on the host +host_inst_rate 92513 # Simulator instruction rate (inst/s) +host_op_rate 113896 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59339858 # Simulator tick rate (ticks/s) +host_mem_usage 320156 # Number of bytes of host memory used +host_seconds 6924.97 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315456 # Number of read requests accepted -system.physmem.writeReqs 66342 # Number of write requests accepted -system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19899 # Per bank write bursts -system.physmem.perBankRdBursts::1 19575 # Per bank write bursts -system.physmem.perBankRdBursts::2 19715 # Per bank write bursts -system.physmem.perBankRdBursts::3 19833 # Per bank write bursts -system.physmem.perBankRdBursts::4 19635 # Per bank write bursts -system.physmem.perBankRdBursts::5 20130 # Per bank write bursts -system.physmem.perBankRdBursts::6 19631 # Per bank write bursts -system.physmem.perBankRdBursts::7 19419 # Per bank write bursts -system.physmem.perBankRdBursts::8 19547 # Per bank write bursts -system.physmem.perBankRdBursts::9 19463 # Per bank write bursts -system.physmem.perBankRdBursts::10 19540 # Per bank write bursts -system.physmem.perBankRdBursts::11 19765 # Per bank write bursts -system.physmem.perBankRdBursts::12 19604 # Per bank write bursts -system.physmem.perBankRdBursts::13 19959 # Per bank write bursts -system.physmem.perBankRdBursts::14 19457 # Per bank write bursts -system.physmem.perBankRdBursts::15 19978 # Per bank write bursts -system.physmem.perBankWrBursts::0 4260 # Per bank write bursts -system.physmem.perBankWrBursts::1 4107 # Per bank write bursts -system.physmem.perBankWrBursts::2 4142 # Per bank write bursts -system.physmem.perBankWrBursts::3 4156 # Per bank write bursts -system.physmem.perBankWrBursts::4 4244 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 227008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7012480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12950080 # Number of bytes read from this memory +system.physmem.bytes_read::total 20189568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245632 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3547 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202345 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315462 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66338 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66338 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 552429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17065036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31514326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49131792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10331846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10331846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10331846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17065036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31514326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59463638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315462 # Number of read requests accepted +system.physmem.writeReqs 66338 # Number of write requests accepted +system.physmem.readBursts 315462 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66338 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20169664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4239360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20189568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 69 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19798 # Per bank write bursts +system.physmem.perBankRdBursts::1 19540 # Per bank write bursts +system.physmem.perBankRdBursts::2 19718 # Per bank write bursts +system.physmem.perBankRdBursts::3 19803 # Per bank write bursts +system.physmem.perBankRdBursts::4 19742 # Per bank write bursts +system.physmem.perBankRdBursts::5 20227 # Per bank write bursts +system.physmem.perBankRdBursts::6 19591 # Per bank write bursts +system.physmem.perBankRdBursts::7 19445 # Per bank write bursts +system.physmem.perBankRdBursts::8 19492 # Per bank write bursts +system.physmem.perBankRdBursts::9 19431 # Per bank write bursts +system.physmem.perBankRdBursts::10 19416 # Per bank write bursts +system.physmem.perBankRdBursts::11 19789 # Per bank write bursts +system.physmem.perBankRdBursts::12 19620 # Per bank write bursts +system.physmem.perBankRdBursts::13 20020 # Per bank write bursts +system.physmem.perBankRdBursts::14 19553 # Per bank write bursts +system.physmem.perBankRdBursts::15 19966 # Per bank write bursts +system.physmem.perBankWrBursts::0 4272 # Per bank write bursts +system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4154 # Per bank write bursts +system.physmem.perBankWrBursts::4 4243 # Per bank write bursts system.physmem.perBankWrBursts::5 4228 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4095 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts @@ -83,38 +83,38 @@ system.physmem.perBankWrBursts::11 4097 # Pe system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4150 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409388361500 # Total gap between requests +system.physmem.totGap 410926705500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315456 # Read request sizes (log2) +system.physmem.readPktSize::6 315462 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66342 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1340 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66338 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 125674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 115954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 985 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,165 +148,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 449.952316 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3996 98.96% 98.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 21 0.52% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 8 0.20% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 136743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.487469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.645908 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.261259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54158 39.61% 39.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57478 42.03% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14696 10.75% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1431 1.05% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1373 1.00% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1481 1.08% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1196 0.87% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1150 0.84% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3780 2.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136743 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 66.735038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.718214 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 464.978559 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3992 99.13% 99.13% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 4 0.10% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 3 0.07% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 4 0.10% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 2 0.05% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-5631 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4038 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.401932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.368431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.138933 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3429 84.92% 84.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.15% 85.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 436 10.80% 95.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 81 2.01% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 33 0.82% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 20 0.50% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 9 0.22% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads -system.physmem.totQLat 9474850817 # Total ticks spent queuing -system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::8192-8703 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 2 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4027 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.448969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.407245 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.299266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3382 83.98% 83.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 84.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 453 11.25% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 103 2.56% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.50% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.47% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.25% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.27% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.20% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.12% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4027 # Writes before turning the bus around for reads +system.physmem.totQLat 8985315314 # Total ticks spent queuing +system.physmem.totMemAccLat 14894396564 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1575755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28511.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47261.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.13 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.47 # Data bus utilization in percentage +system.physmem.busUtil 0.46 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 218195 # Number of row buffer hits during reads -system.physmem.writeRowHits 26465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes -system.physmem.avgGap 1072264.29 # Average gap between requests -system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ) +system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing +system.physmem.readRowHits 218304 # Number of row buffer hits during reads +system.physmem.writeRowHits 26331 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.73 # Row buffer hit rate for writes +system.physmem.avgGap 1076287.86 # Average gap between requests +system.physmem.pageHitRate 64.14 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 518260680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282781125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1231058400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216470880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96374211480 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.719632 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states -system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states +system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96516777600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161887922250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 287492576775 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.632177 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 268678979341 # Time in different power states +system.physmem_0.memoryStateTime::REF 13721500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128519138159 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.635519 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states -system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states +system.physmem_1.actEnergy 515334960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 281184750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1226448600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212712480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96027774030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 162316872750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 287419581570 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.454538 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 269400106911 # Time in different power states +system.physmem_1.memoryStateTime::REF 13721500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127799659089 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233960267 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits +system.cpu.branchPred.lookups 233961600 # Number of BP lookups +system.cpu.branchPred.condPredicted 161823435 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514478 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121576875 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108260850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.047239 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25036809 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300056 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,129 +427,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 818776833 # number of cpu cycles simulated +system.cpu.numCycles 821853521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85352108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200709266 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233961600 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133297659 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 720636600 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063377 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2846 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370706156 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652600 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 821526595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.826688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.166658 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 139803220 17.02% 17.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223204281 27.17% 44.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98088574 11.94% 56.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360430520 43.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 821526595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284676 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.460977 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121268240 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 161448420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484660246 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38631680 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518009 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25181996 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13829 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248138563 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966565 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518009 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178275276 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80711720 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 210548 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319817 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82491225 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190650018 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25545971 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24926226 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267555 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41530027 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1673344 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225393242 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812447453 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358179782 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 350615012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7270 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108779302 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366116842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236096763 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1776884 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5334939 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168558899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017090766 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18380245 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379846300 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032153355 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 821526595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.238050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084805 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 263868507 32.12% 32.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227113166 27.65% 59.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217783209 26.51% 86.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96635677 11.76% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16126029 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 821526595 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63875827 18.90% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 157407577 46.57% 65.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116033793 34.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456370958 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195826 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -569,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478993 1.13% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478994 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322082825 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215586812 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued -system.cpu.iq.rate 1.242264 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017090766 # Type of FU issued +system.cpu.iq.rate 1.237557 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337972229 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3150183586 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504870139 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934273978 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877015 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565815 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1321252671 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810324 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960626 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113875904 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18399 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065816 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 20694 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518009 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35327000 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41213 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168576814 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18393 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.iewDispLoadInsts 366116842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236096763 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 44806 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18399 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437241 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784654 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 974751722 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303298002 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42339044 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5554 # number of nop insts executed -system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613469 # Number of branches executed -system.cpu.iew.exec_stores 194467616 # Number of stores executed -system.cpu.iew.exec_rate 1.190497 # Inst execution rate -system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536680583 # num instructions producing a value -system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value +system.cpu.iew.exec_nop 5556 # number of nop insts executed +system.cpu.iew.exec_refs 497764632 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613642 # Number of branches executed +system.cpu.iew.exec_stores 194466630 # Number of stores executed +system.cpu.iew.exec_rate 1.186041 # Inst execution rate +system.cpu.iew.wb_sent 963724701 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960426422 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536047355 # num instructions producing a value +system.cpu.iew.wb_consumers 893284415 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back +system.cpu.iew.wb_rate 1.168610 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357420349 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500799 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770704967 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.023388 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.776993 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 432077450 56.06% 56.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174390434 22.63% 78.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72936884 9.46% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32898197 4.27% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538905 1.11% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14258273 1.85% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269904 0.94% 96.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5974492 0.78% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360428 2.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 767631497 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770704967 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,383 +700,389 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360345 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1891399680 # The number of ROB reads -system.cpu.rob.rob_writes 2343098733 # The number of ROB writes -system.cpu.timesIdled 647345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 325081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360428 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1894486207 # The number of ROB reads +system.cpu.rob.rob_writes 2343126387 # The number of ROB writes +system.cpu.timesIdled 647317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326926 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads -system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995806519 # number of integer regfile reads -system.cpu.int_regfile_writes 567906159 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794435468 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898950 # number of cc regfile writes -system.cpu.misc_regfile_reads 715817595 # number of misc regfile reads +system.cpu.cpi 1.282845 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282845 # CPI: Total CPI of All Threads +system.cpu.ipc 0.779518 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.779518 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995802121 # number of integer regfile reads +system.cpu.int_regfile_writes 567908278 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794438886 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898194 # number of cc regfile writes +system.cpu.misc_regfile_reads 715817246 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes system.cpu.dcache.tags.replacements 2756184 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.932971 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414226712 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.933712 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414215984 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.262021 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.932971 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 150.258129 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 256316000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.933712 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999871 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999871 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839343984 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839343984 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286295259 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286295259 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127916705 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127916705 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3174 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3174 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839346446 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839346446 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293586 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293586 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907704 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907704 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414211964 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414211964 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414215138 # number of overall hits -system.cpu.dcache.overall_hits::total 414215138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031608 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031608 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1034772 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1034772 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414201290 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414201290 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414204447 # number of overall hits +system.cpu.dcache.overall_hits::total 414204447 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3034530 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3034530 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043773 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043773 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4066380 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4066380 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4067027 # number of overall misses -system.cpu.dcache.overall_misses::total 4067027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35305181420 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35305181420 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981703626 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9981703626 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 189500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45286885046 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45286885046 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45286885046 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45286885046 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289326867 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289326867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4078303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4078303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4078949 # number of overall misses +system.cpu.dcache.overall_misses::total 4078949 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35233063500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35233063500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9908998850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9908998850 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45142062350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45142062350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45142062350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45142062350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328116 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3821 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3821 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418278344 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418278344 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418282165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418282165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169327 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169327 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418279593 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279593 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283396 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283396 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008094 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008094 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.283071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.283071 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11136.904334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11135.132628 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009750 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009750 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009752 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009752 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11610.715168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11610.715168 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9493.442396 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9493.442396 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11068.834844 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11068.834844 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11067.081827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11067.081827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 343566 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 326278 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5188 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 66.223207 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 67.011296 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735673 # number of writebacks -system.cpu.dcache.writebacks::total 735673 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 996399 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313907 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 313907 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735190 # number of writebacks +system.cpu.dcache.writebacks::total 735190 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999322 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999322 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322910 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 322910 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1310306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1310306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1310306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1310306 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720865 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720865 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1322232 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1322232 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1322232 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1322232 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035208 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720863 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720863 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23118028700 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23118028700 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596519781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596519781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5770003 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5770003 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714548481 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28714548481 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720318484 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28720318484 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756071 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756712 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756712 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24098858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24098858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5945182850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5945182850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6199500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6199500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30044041350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30044041350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30050240850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30050240850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167757 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167757 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.617017 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.617017 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9001.564743 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9001.564743 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.980627 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.980627 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8247.313082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8247.313082 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9671.606864 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9671.606864 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10901.040412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10901.040412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10900.754540 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10900.754540 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169974 # number of replacements -system.cpu.icache.tags.tagsinuse 511.005918 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 365528009 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5170484 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.695124 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 247768250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.005918 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998058 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169094 # number of replacements +system.cpu.icache.tags.tagsinuse 511.159465 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 365531814 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169604 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.707894 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 246618500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.159465 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998358 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 746574831 # Number of tag accesses -system.cpu.icache.tags.data_accesses 746574831 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 365528032 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 365528032 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 365528032 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 365528032 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 365528032 # number of overall hits -system.cpu.icache.overall_hits::total 365528032 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174132 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174132 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174132 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174132 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174132 # number of overall misses -system.cpu.icache.overall_misses::total 5174132 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647443196 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41647443196 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41647443196 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41647443196 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41647443196 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41647443196 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370702164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370702164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370702164 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370702164 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370702164 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370702164 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 746581864 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746581864 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365531869 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365531869 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365531869 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 365531869 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 365531869 # number of overall hits +system.cpu.icache.overall_hits::total 365531869 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174253 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174253 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174253 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174253 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174253 # number of overall misses +system.cpu.icache.overall_misses::total 5174253 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41642635922 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41642635922 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41642635922 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41642635922 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41642635922 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41642635922 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370706122 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370706122 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370706122 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370706122 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370706122 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370706122 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013958 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.165193 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8049.165193 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8049.165193 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8049.165193 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 75254 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3130 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.047887 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8048.047887 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.047887 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8048.047887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.047887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8048.047887 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 80330 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3828 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.042812 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.984848 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3628 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3628 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3628 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3628 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3628 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3628 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170504 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170504 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170504 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170504 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170504 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170504 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431387686 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36431387686 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431387686 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36431387686 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431387686 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36431387686 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013948 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013948 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013948 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.003192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.003192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4632 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4632 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4632 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4632 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4632 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4632 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5169621 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169621 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5169621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5169621 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39011263436 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39011263436 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39011263436 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39011263436 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39011263436 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39011263436 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013945 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013945 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013945 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7546.252121 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7546.252121 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7546.252121 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7546.252121 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7546.252121 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7546.252121 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1347095 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1354943 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 6866 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 1349196 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355261 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 5306 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4789921 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 299165 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16361.556320 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7824806 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 315529 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.799007 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13406100000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 743.986923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582614 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.045409 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.535375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410063 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998630 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229882786 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723775758 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25032488193 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053222 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 66338 # number of writebacks +system.cpu.l2cache.writebacks::total 66338 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1216 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1216 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1112 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1112 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2328 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2341 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2328 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2341 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8918 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 8918 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202421 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202421 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1394 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1394 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3547 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3547 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 108176 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 108176 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3547 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113117 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3547 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 109570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202421 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 315538 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17045778133 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17045778133 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 268500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 123342500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 123342500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 239801000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 239801000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7820358000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7820358000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 239801000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7943700500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8183501500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 239801000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7943700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17045778133 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25229279633 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001934 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001934 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053136 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053136 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039809 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84209.534253 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16781.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16781.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88480.989957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88480.989957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67606.709896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67606.709896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72292.911552 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72292.911552 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72345.460894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79956.390777 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340989 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330911040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 248905 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7205469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 801528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6778838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 266094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035849 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15507443 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23133859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330854720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223480704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554335424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 565266 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 16416862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.034431 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.182334 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15851611 96.56% 96.56% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 565251 3.44% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 16416862 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8660995500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7754456946 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135063976 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 314058 # Transaction distribution -system.membus.trans_dist::ReadResp 314058 # Transaction distribution -system.membus.trans_dist::Writeback 66342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19 # Transaction distribution -system.membus.trans_dist::UpgradeResp 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 1398 # Transaction distribution -system.membus.trans_dist::ReadExResp 1398 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 314068 # Transaction distribution +system.membus.trans_dist::Writeback 66338 # Transaction distribution +system.membus.trans_dist::CleanEvict 232219 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1394 # Transaction distribution +system.membus.trans_dist::ReadExResp 1394 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 314068 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 929513 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 929513 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24435200 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381817 # Request fanout histogram +system.membus.snoop_fanout::samples 614035 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 614035 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381817 # Request fanout histogram -system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 614035 # Request fanout histogram +system.membus.reqLayer0.occupancy 967133123 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1648308021 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 4a7e6f230..627fd964a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.043695 # Number of seconds simulated -sim_ticks 1043695078500 # Number of ticks simulated -final_tick 1043695078500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043722 # Number of seconds simulated +sim_ticks 1043722398500 # Number of ticks simulated +final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 624059 # Simulator instruction rate (inst/s) -host_op_rate 766694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1018706197 # Simulator tick rate (ticks/s) -host_mem_usage 313408 # Number of bytes of host memory used -host_seconds 1024.53 # Real time elapsed on the host +host_inst_rate 921530 # Simulator instruction rate (inst/s) +host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1504334297 # Simulator tick rate (ticks/s) +host_mem_usage 320916 # Number of bytes of host memory used +host_seconds 693.81 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18428352 # Number of bytes read from this memory -system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18469760 # Number of bytes read from this memory +system.physmem.bytes_read::total 18582976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287943 # Number of read requests responded to by this memory -system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288590 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290359 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 108476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17656835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17656835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087390157 # number of cpu cycles simulated +system.cpu.numCycles 2087444797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087390156.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640584 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996415000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640584 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582740000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18582740000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22259892000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22259892000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22259892000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22259892000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.414780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.414780 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.189436 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28465.189436 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.130692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28460.130692 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks -system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.writebacks::writebacks 89072 # number of writebacks +system.cpu.dcache.writebacks::total 89072 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513680000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513680000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086847500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21086847500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088530000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21088530000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.395241 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.395241 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.174686 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.174686 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.533658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.533658 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464501 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464501 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207074000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207074000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207074000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207074000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207074000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207074000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20285.462382 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20285.462382 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20285.462382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20285.462382 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,38 +419,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191762000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 191762000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191762000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 191762000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191762000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 191762000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995689 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id @@ -458,78 +458,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71648500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661691500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71648500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661691500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311229 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288590 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290359 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.173295 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312137 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312137 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366453 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.261164 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366453 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55757696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257579 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 223619 # Transaction distribution -system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 224266 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190085 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224266 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836901 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22813248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 355811 # Request fanout histogram +system.membus.snoop_fanout::samples 546599 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 546599 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 546599 # Request fanout histogram +system.membus.reqLayer0.occupancy 811365948 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1452169448 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index bd4df05db..dfd14c576 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059732 # Number of seconds simulated -sim_ticks 59731559000 # Number of ticks simulated -final_tick 59731559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059580 # Number of seconds simulated +sim_ticks 59579614000 # Number of ticks simulated +final_tick 59579614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330143 # Simulator instruction rate (inst/s) -host_op_rate 330143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222980587 # Simulator tick rate (ticks/s) -host_mem_usage 304704 # Number of bytes of host memory used -host_seconds 267.88 # Real time elapsed on the host +host_inst_rate 321432 # Simulator instruction rate (inst/s) +host_op_rate 321432 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216544599 # Simulator tick rate (ticks/s) +host_mem_usage 304972 # Number of bytes of host memory used +host_seconds 275.14 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 516416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147392 # Number of bytes read from this memory -system.physmem.bytes_read::total 10663808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 516416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 516416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7298880 # Number of bytes written to this memory -system.physmem.bytes_written::total 7298880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158553 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166622 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114045 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114045 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8645614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169883261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178528874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8645614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8645614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122194701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122194701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122194701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8645614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169883261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 300723576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166622 # Number of read requests accepted -system.physmem.writeReqs 114045 # Number of write requests accepted -system.physmem.readBursts 166622 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114045 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10663168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10663808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7298880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 500672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10147648 # Number of bytes read from this memory +system.physmem.bytes_read::total 10648320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 500672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 500672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7320576 # Number of bytes written to this memory +system.physmem.bytes_written::total 7320576 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158557 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166380 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114384 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114384 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8403411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170320808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178724219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8403411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8403411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122870484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122870484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122870484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8403411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170320808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301594703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166380 # Number of read requests accepted +system.physmem.writeReqs 114384 # Number of write requests accepted +system.physmem.readBursts 166380 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114384 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10648064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7319040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10648320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7320576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10463 # Per bank write bursts -system.physmem.perBankRdBursts::1 10512 # Per bank write bursts -system.physmem.perBankRdBursts::2 10314 # Per bank write bursts -system.physmem.perBankRdBursts::3 10093 # Per bank write bursts -system.physmem.perBankRdBursts::4 10430 # Per bank write bursts -system.physmem.perBankRdBursts::5 10428 # Per bank write bursts -system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10305 # Per bank write bursts -system.physmem.perBankRdBursts::8 10593 # Per bank write bursts -system.physmem.perBankRdBursts::9 10642 # Per bank write bursts -system.physmem.perBankRdBursts::10 10591 # Per bank write bursts +system.physmem.perBankRdBursts::0 10451 # Per bank write bursts +system.physmem.perBankRdBursts::1 10506 # Per bank write bursts +system.physmem.perBankRdBursts::2 10284 # Per bank write bursts +system.physmem.perBankRdBursts::3 10088 # Per bank write bursts +system.physmem.perBankRdBursts::4 10415 # Per bank write bursts +system.physmem.perBankRdBursts::5 10418 # Per bank write bursts +system.physmem.perBankRdBursts::6 9828 # Per bank write bursts +system.physmem.perBankRdBursts::7 10277 # Per bank write bursts +system.physmem.perBankRdBursts::8 10580 # Per bank write bursts +system.physmem.perBankRdBursts::9 10645 # Per bank write bursts +system.physmem.perBankRdBursts::10 10557 # Per bank write bursts system.physmem.perBankRdBursts::11 10259 # Per bank write bursts -system.physmem.perBankRdBursts::12 10303 # Per bank write bursts -system.physmem.perBankRdBursts::13 10653 # Per bank write bursts -system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10649 # Per bank write bursts -system.physmem.perBankWrBursts::0 7087 # Per bank write bursts -system.physmem.perBankWrBursts::1 7261 # Per bank write bursts -system.physmem.perBankWrBursts::2 7256 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts -system.physmem.perBankWrBursts::4 7125 # Per bank write bursts -system.physmem.perBankWrBursts::5 7180 # Per bank write bursts -system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7091 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7094 # Per bank write bursts +system.physmem.perBankRdBursts::12 10298 # Per bank write bursts +system.physmem.perBankRdBursts::13 10623 # Per bank write bursts +system.physmem.perBankRdBursts::14 10516 # Per bank write bursts +system.physmem.perBankRdBursts::15 10631 # Per bank write bursts +system.physmem.perBankWrBursts::0 7162 # Per bank write bursts +system.physmem.perBankWrBursts::1 7274 # Per bank write bursts +system.physmem.perBankWrBursts::2 7295 # Per bank write bursts +system.physmem.perBankWrBursts::3 6999 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 7182 # Per bank write bursts +system.physmem.perBankWrBursts::6 6834 # Per bank write bursts +system.physmem.perBankWrBursts::7 7095 # Per bank write bursts +system.physmem.perBankWrBursts::8 7222 # Per bank write bursts +system.physmem.perBankWrBursts::9 6994 # Per bank write bursts +system.physmem.perBankWrBursts::10 7111 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6965 # Per bank write bursts -system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7283 # Per bank write bursts -system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.perBankWrBursts::12 6990 # Per bank write bursts +system.physmem.perBankWrBursts::13 7296 # Per bank write bursts +system.physmem.perBankWrBursts::14 7306 # Per bank write bursts +system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59731532000 # Total gap between requests +system.physmem.totGap 59579590000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166622 # Read request sizes (log2) +system.physmem.readPktSize::6 166380 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114045 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1551 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114384 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1592 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -193,121 +193,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54759 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.975602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.612520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.469121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19499 35.61% 35.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11959 21.84% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5687 10.39% 67.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3574 6.53% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2717 4.96% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2083 3.80% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1679 3.07% 86.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1528 2.79% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6033 11.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54759 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.742625 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.245058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7015 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.249109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.233383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.749815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6248 89.04% 89.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.26% 89.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 569 8.11% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 155 2.21% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 21 0.30% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 54737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.220838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.100573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.685535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19472 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11861 21.67% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5645 10.31% 67.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3680 6.72% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2860 5.22% 79.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2018 3.69% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1694 3.09% 86.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1489 2.72% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6018 10.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54737 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.631676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.376134 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7037 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7040 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.244318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.229045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.737232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6278 89.18% 89.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 16 0.23% 89.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 578 8.21% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 145 2.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 15 0.21% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.03% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7017 # Writes before turning the bus around for reads -system.physmem.totQLat 1993187750 # Total ticks spent queuing -system.physmem.totMemAccLat 5117162750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11963.05 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7040 # Writes before turning the bus around for reads +system.physmem.totQLat 2004219750 # Total ticks spent queuing +system.physmem.totMemAccLat 5123769750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12046.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30713.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.19 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30796.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.84 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.35 # Data bus utilization in percentage -system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.36 # Data bus utilization in percentage +system.physmem.busUtilRead 1.40 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.13 # Average write queue length when enqueuing -system.physmem.readRowHits 144646 # Number of row buffer hits during reads -system.physmem.writeRowHits 81220 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing +system.physmem.readRowHits 144447 # Number of row buffer hits during reads +system.physmem.writeRowHits 81540 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.22 # Row buffer hit rate for writes -system.physmem.avgGap 212819.93 # Average gap between requests -system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199621800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108920625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 642564000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367681680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12761553015 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24642806250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42624311130 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.633365 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40844346250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1994460000 # Time in different power states +system.physmem.writeRowHitRate 71.29 # Row buffer hit rate for writes +system.physmem.avgGap 212205.23 # Average gap between requests +system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199372320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108784500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641464200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368938800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12501731340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24777284250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42488567970 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.220229 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41071172000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1989260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16889792000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16512675000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214235280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116894250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 656728800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370960560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13264546950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24201582750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42726112350 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.337777 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40104532750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1994460000 # Time in different power states +system.physmem_1.actEnergy 214189920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116869500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 655792800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371790000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13114227690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24240006750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42603869220 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.155695 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40171909250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1989260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17629849250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17411703250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14669488 # Number of BP lookups -system.cpu.branchPred.condPredicted 9491497 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 392361 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10408467 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6389552 # Number of BTB hits +system.cpu.branchPred.lookups 14668515 # Number of BP lookups +system.cpu.branchPred.condPredicted 9490335 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 391198 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9984003 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6387554 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.388022 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708748 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85394 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.977885 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708558 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85259 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20569996 # DTB read hits -system.cpu.dtb.read_misses 97344 # DTB read misses +system.cpu.dtb.read_hits 20570256 # DTB read hits +system.cpu.dtb.read_misses 97321 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20667340 # DTB read accesses -system.cpu.dtb.write_hits 14665866 # DTB write hits -system.cpu.dtb.write_misses 9405 # DTB write misses +system.cpu.dtb.read_accesses 20667577 # DTB read accesses +system.cpu.dtb.write_hits 14665734 # DTB write hits +system.cpu.dtb.write_misses 9406 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675271 # DTB write accesses -system.cpu.dtb.data_hits 35235862 # DTB hits -system.cpu.dtb.data_misses 106749 # DTB misses +system.cpu.dtb.write_accesses 14675140 # DTB write accesses +system.cpu.dtb.data_hits 35235990 # DTB hits +system.cpu.dtb.data_misses 106727 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35342611 # DTB accesses -system.cpu.itb.fetch_hits 25629903 # ITB hits -system.cpu.itb.fetch_misses 5247 # ITB misses +system.cpu.dtb.data_accesses 35342717 # DTB accesses +system.cpu.itb.fetch_hits 25623202 # ITB hits +system.cpu.itb.fetch_misses 5252 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25635150 # ITB accesses +system.cpu.itb.fetch_accesses 25628454 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,81 +322,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119463118 # number of cpu cycles simulated +system.cpu.numCycles 119159228 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1109771 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1111760 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.350811 # CPI: cycles per instruction -system.cpu.ipc 0.740296 # IPC: instructions per cycle -system.cpu.tickCycles 91541167 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27921951 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200768 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.577182 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616116 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204864 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.971200 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.577182 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993793 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993793 # Average percentage of cache occupancy +system.cpu.cpi 1.347375 # CPI: cycles per instruction +system.cpu.ipc 0.742184 # IPC: instructions per cycle +system.cpu.tickCycles 91522395 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27636833 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200775 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.716592 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616548 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204871 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.967536 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 688117500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.716592 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993827 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993827 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 679 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176158 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176158 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282855 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282855 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616116 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616116 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616116 # number of overall hits -system.cpu.dcache.overall_hits::total 34616116 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89415 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89415 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses -system.cpu.dcache.overall_misses::total 369531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4791422750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4791422750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21873540250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21873540250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26664963000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26664963000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26664963000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26664963000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372270 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372270 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70177059 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70177059 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20283298 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20283298 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333250 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333250 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616548 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616548 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616548 # number of overall hits +system.cpu.dcache.overall_hits::total 34616548 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89419 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89419 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280127 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280127 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369546 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369546 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369546 # number of overall misses +system.cpu.dcache.overall_misses::total 369546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4766015000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4766015000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21725113500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21725113500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26491128500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26491128500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26491128500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26491128500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372717 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372717 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985647 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985647 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985647 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985647 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34986094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34986094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34986094 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34986094 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53586.341777 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53586.341777 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78087.436098 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78087.436098 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72158.933892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72158.933892 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53299.802055 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53299.802055 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77554.514559 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77554.514559 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71685.604769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71685.604769 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,32 +405,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168537 # number of writebacks -system.cpu.dcache.writebacks::total 168537 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136551 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136551 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164667 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61299 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61299 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143565 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143565 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204864 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204864 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204864 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204864 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2648121500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2648121500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10930365250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10930365250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13578486750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13578486750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13578486750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13578486750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168451 # number of writebacks +system.cpu.dcache.writebacks::total 168451 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136563 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136563 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164675 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164675 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164675 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164675 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61307 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61307 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143564 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143564 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204871 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204871 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204871 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204871 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2678080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2678080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10985374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10985374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13663454000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13663454000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13663454000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13663454000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -438,68 +439,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43200.076673 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43200.076673 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76135.306307 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76135.306307 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66280.492180 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66280.492180 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66280.492180 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66280.492180 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43683.103071 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43683.103071 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76519.001978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76519.001978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66692.962889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66692.962889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66692.962889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66692.962889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 152979 # number of replacements -system.cpu.icache.tags.tagsinuse 1932.259039 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25474875 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155027 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 164.325408 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42450985250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1932.259039 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943486 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943486 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 153439 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.585595 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25467714 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155487 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.793205 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42332946500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.585595 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943645 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943645 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1043 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51414833 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51414833 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25474875 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25474875 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25474875 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25474875 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25474875 # number of overall hits -system.cpu.icache.overall_hits::total 25474875 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155028 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155028 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155028 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155028 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155028 # number of overall misses -system.cpu.icache.overall_misses::total 155028 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2574589242 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2574589242 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2574589242 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2574589242 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2574589242 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2574589242 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25629903 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25629903 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25629903 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16607.253154 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16607.253154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16607.253154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16607.253154 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51401891 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51401891 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25467714 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25467714 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25467714 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25467714 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25467714 # number of overall hits +system.cpu.icache.overall_hits::total 25467714 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155488 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155488 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155488 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155488 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155488 # number of overall misses +system.cpu.icache.overall_misses::total 155488 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2558679500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2558679500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2558679500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2558679500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2558679500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2558679500 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2338939258 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2338939258 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15087.205266 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15087.205266 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15087.205266 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15087.205266 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15087.205266 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15087.205266 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155488 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 155488 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 155488 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 155488 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155488 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155488 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2403192500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2403192500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2403192500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2403192500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2403192500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2403192500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006068 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006068 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006068 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164772 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.334141 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132455 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30425.611503 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 404125 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164531 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.456224 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26160.561062 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2366.479179 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1894.410957 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.798357 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11640 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19278 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 937 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11867 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19026 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 126 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4535770 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4535770 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 146958 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33627 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 180585 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168537 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168537 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12684 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 146958 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 193269 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 146958 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46311 # number of overall hits -system.cpu.l2cache.overall_hits::total 193269 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8070 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27671 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35741 # number of ReadReq misses +system.cpu.l2cache.tags.tag_accesses 6024680 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 6024680 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 168451 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168451 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12683 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12683 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 147664 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 147664 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33631 # 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number of cycles access was blocked @@ -633,105 +641,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114045 # number of writebacks -system.cpu.l2cache.writebacks::total 114045 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8070 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27671 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35741 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 114384 # number of writebacks +system.cpu.l2cache.writebacks::total 114384 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2093 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 2093 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9327992500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 541189000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 541189000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1955782000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1955782000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541189000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11283774500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11824963500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541189000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11283774500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11824963500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050319 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451424 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451424 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.461709 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.461709 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71270.247246 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71270.247246 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69170.373211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69170.373211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70669.629630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70669.629630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 216326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 216325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168537 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143566 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310055 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 888320 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9921728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33819392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 528429 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 216793 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 282835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 203834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 155488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61306 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610517 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1074931 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9951168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33843776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132455 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 847028 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.156376 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.363212 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 528429 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 714573 84.36% 84.36% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 132455 15.64% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 528429 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 432751500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 234095242 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 847028 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 525737500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 233232496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343202250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35740 # Transaction distribution -system.membus.trans_dist::ReadResp 35740 # Transaction distribution -system.membus.trans_dist::Writeback 114045 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 307309993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadResp 35498 # Transaction distribution +system.membus.trans_dist::Writeback 114384 # Transaction distribution +system.membus.trans_dist::CleanEvict 16134 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447289 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447289 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17962688 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 35498 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 463278 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17968896 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280667 # Request fanout histogram +system.membus.snoop_fanout::samples 296898 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280667 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 296898 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280667 # Request fanout histogram -system.membus.reqLayer0.occupancy 816993000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 296898 # Request fanout histogram +system.membus.reqLayer0.occupancy 824886500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 879772000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 878487500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 9afa0da2d..2061356b3 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022578 # Number of seconds simulated -sim_ticks 22578120000 # Number of ticks simulated -final_tick 22578120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022637 # Number of seconds simulated +sim_ticks 22637068500 # Number of ticks simulated +final_tick 22637068500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210348 # Simulator instruction rate (inst/s) -host_op_rate 210348 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59670380 # Simulator tick rate (ticks/s) -host_mem_usage 234940 # Number of bytes of host memory used -host_seconds 378.38 # Real time elapsed on the host +host_inst_rate 222882 # Simulator instruction rate (inst/s) +host_op_rate 222882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63391012 # Simulator tick rate (ticks/s) +host_mem_usage 306268 # Number of bytes of host memory used +host_seconds 357.10 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10151104 # Number of bytes read from this memory -system.physmem.bytes_read::total 10638720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7619 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158611 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166230 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21596838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449599169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 471196007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21596838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21596838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 323181558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 323181558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 323181558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21596838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449599169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 794377566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166230 # Number of read requests accepted -system.physmem.writeReqs 114013 # Number of write requests accepted -system.physmem.readBursts 166230 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114013 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10638720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 472384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153088 # Number of bytes read from this memory +system.physmem.bytes_read::total 10625472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 472384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 472384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7318784 # Number of bytes written to this memory +system.physmem.bytes_written::total 7318784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158642 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114356 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114356 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20867720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 448516026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 469383746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20867720 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20867720 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323309708 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323309708 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323309708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20867720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 448516026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 792693453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166023 # Number of read requests accepted +system.physmem.writeReqs 114356 # Number of write requests accepted +system.physmem.readBursts 166023 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114356 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10625216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7317504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10625472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7318784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10435 # Per bank write bursts -system.physmem.perBankRdBursts::1 10460 # Per bank write bursts -system.physmem.perBankRdBursts::2 10318 # Per bank write bursts +system.physmem.perBankRdBursts::0 10427 # Per bank write bursts +system.physmem.perBankRdBursts::1 10469 # Per bank write bursts +system.physmem.perBankRdBursts::2 10285 # Per bank write bursts system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10413 # Per bank write bursts -system.physmem.perBankRdBursts::5 10396 # Per bank write bursts -system.physmem.perBankRdBursts::6 9837 # Per bank write bursts -system.physmem.perBankRdBursts::7 10308 # Per bank write bursts -system.physmem.perBankRdBursts::8 10587 # Per bank write bursts -system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10547 # Per bank write bursts -system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10270 # Per bank write bursts -system.physmem.perBankRdBursts::13 10618 # Per bank write bursts -system.physmem.perBankRdBursts::14 10481 # Per bank write bursts -system.physmem.perBankRdBursts::15 10621 # Per bank write bursts -system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7259 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6997 # Per bank write bursts -system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6772 # Per bank write bursts -system.physmem.perBankWrBursts::7 7083 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6939 # Per bank write bursts -system.physmem.perBankWrBursts::10 7083 # Per bank write bursts -system.physmem.perBankWrBursts::11 6988 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts -system.physmem.perBankWrBursts::13 7288 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts -system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.perBankRdBursts::4 10410 # Per bank write bursts +system.physmem.perBankRdBursts::5 10383 # Per bank write bursts +system.physmem.perBankRdBursts::6 9823 # Per bank write bursts +system.physmem.perBankRdBursts::7 10285 # Per bank write bursts +system.physmem.perBankRdBursts::8 10562 # Per bank write bursts +system.physmem.perBankRdBursts::9 10635 # Per bank write bursts +system.physmem.perBankRdBursts::10 10512 # Per bank write bursts +system.physmem.perBankRdBursts::11 10227 # Per bank write bursts +system.physmem.perBankRdBursts::12 10266 # Per bank write bursts +system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::14 10475 # Per bank write bursts +system.physmem.perBankRdBursts::15 10612 # Per bank write bursts +system.physmem.perBankWrBursts::0 7161 # Per bank write bursts +system.physmem.perBankWrBursts::1 7270 # Per bank write bursts +system.physmem.perBankWrBursts::2 7294 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 7175 # Per bank write bursts +system.physmem.perBankWrBursts::6 6835 # Per bank write bursts +system.physmem.perBankWrBursts::7 7095 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::9 6995 # Per bank write bursts +system.physmem.perBankWrBursts::10 7100 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts +system.physmem.perBankWrBursts::12 6993 # Per bank write bursts +system.physmem.perBankWrBursts::13 7294 # Per bank write bursts +system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22578086500 # Total gap between requests +system.physmem.totGap 22637037500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166230 # Read request sizes (log2) +system.physmem.readPktSize::6 166023 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114013 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 52462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114356 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 52265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1941 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,121 +193,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.127440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.641716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.309325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18423 35.25% 35.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10477 20.05% 55.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5934 11.35% 66.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2978 5.70% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2855 5.46% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1509 2.89% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2072 3.96% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 924 1.77% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7088 13.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52260 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6982 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.804927 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.249057 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6981 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.050573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.162039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.313279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18282 34.96% 34.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10576 20.22% 55.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5922 11.32% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2988 5.71% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3062 5.85% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1483 2.84% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1989 3.80% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1021 1.95% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6978 13.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52301 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.736917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.159441 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6991 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6982 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6982 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.325265 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.299310 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.979398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6150 88.08% 88.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.36% 88.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 468 6.70% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 181 2.59% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 78 1.12% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.66% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 19 0.27% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.14% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 4 0.06% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6982 # Writes before turning the bus around for reads -system.physmem.totQLat 5742111500 # Total ticks spent queuing -system.physmem.totMemAccLat 8858755250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34545.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.347727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.319415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.025091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6123 87.55% 87.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.37% 87.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 468 6.69% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 194 2.77% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 92 1.32% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 55 0.79% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 18 0.26% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads +system.physmem.totQLat 5783499750 # Total ticks spent queuing +system.physmem.totMemAccLat 8896356000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 830095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34836.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53295.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 471.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 323.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 471.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 323.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53586.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 469.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 469.38 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.21 # Data bus utilization in percentage -system.physmem.busUtilRead 3.68 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 146222 # Number of row buffer hits during reads -system.physmem.writeRowHits 81709 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.67 # Row buffer hit rate for writes -system.physmem.avgGap 80566.10 # Average gap between requests +system.physmem.busUtil 6.19 # Data bus utilization in percentage +system.physmem.busUtilRead 3.67 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.53 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 145949 # Number of row buffer hits during reads +system.physmem.writeRowHits 82096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes +system.physmem.avgGap 80737.28 # Average gap between requests system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190685880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 104044875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641035200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367584480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6555814245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7792863750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 17126343870 # Total energy per rank (pJ) -system.physmem_0.averagePower 758.721685 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12883309000 # Time in different power states -system.physmem_0.memoryStateTime::REF 753740000 # Time in different power states +system.physmem_0.actEnergy 190852200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 104135625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640543800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368925840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6748287570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7661408250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 17192537205 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.557739 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12661521500 # Time in different power states +system.physmem_0.memoryStateTime::REF 755820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8935594000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9217738000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204104880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111366750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370701360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6889050495 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7500532500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 17204990625 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.206905 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12395641000 # Time in different power states -system.physmem_1.memoryStateTime::REF 753740000 # Time in different power states +system.physmem_1.actEnergy 204354360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111502875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654108000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6845140260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7576424250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17241677745 # Total energy per rank (pJ) +system.physmem_1.averagePower 761.730174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12521267250 # Time in different power states +system.physmem_1.memoryStateTime::REF 755820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9423231500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9357815250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16619938 # Number of BP lookups -system.cpu.branchPred.condPredicted 10751763 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 361573 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10694449 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7373128 # Number of BTB hits +system.cpu.branchPred.lookups 16666171 # Number of BP lookups +system.cpu.branchPred.condPredicted 10777513 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 373740 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11097684 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7405754 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.943505 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990233 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3119 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 66.732428 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1996658 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2898 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22587975 # DTB read hits -system.cpu.dtb.read_misses 226213 # DTB read misses -system.cpu.dtb.read_acv 17 # DTB read access violations -system.cpu.dtb.read_accesses 22814188 # DTB read accesses -system.cpu.dtb.write_hits 15866557 # DTB write hits -system.cpu.dtb.write_misses 44947 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15911504 # DTB write accesses -system.cpu.dtb.data_hits 38454532 # DTB hits -system.cpu.dtb.data_misses 271160 # DTB misses -system.cpu.dtb.data_acv 18 # DTB access violations -system.cpu.dtb.data_accesses 38725692 # DTB accesses -system.cpu.itb.fetch_hits 13913083 # ITB hits -system.cpu.itb.fetch_misses 32600 # ITB misses +system.cpu.dtb.read_hits 22620977 # DTB read hits +system.cpu.dtb.read_misses 226849 # DTB read misses +system.cpu.dtb.read_acv 27 # DTB read access violations +system.cpu.dtb.read_accesses 22847826 # DTB read accesses +system.cpu.dtb.write_hits 15870488 # DTB write hits +system.cpu.dtb.write_misses 45057 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15915545 # DTB write accesses +system.cpu.dtb.data_hits 38491465 # DTB hits +system.cpu.dtb.data_misses 271906 # DTB misses +system.cpu.dtb.data_acv 31 # DTB access violations +system.cpu.dtb.data_accesses 38763371 # DTB accesses +system.cpu.itb.fetch_hits 13971550 # ITB hits +system.cpu.itb.fetch_misses 35700 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13945683 # ITB accesses +system.cpu.itb.fetch_accesses 14007250 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,101 +323,101 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 45156244 # number of cpu cycles simulated +system.cpu.numCycles 45274140 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15767330 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106100961 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16619938 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9363361 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27775290 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 962592 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 339291 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13913083 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207051 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 44368516 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.391357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.125574 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15840684 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106412182 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16666171 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9402412 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27820247 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 987192 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 787 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5202 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 343767 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13971550 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209132 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 44504386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.391049 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.126296 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24640012 55.53% 55.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1537852 3.47% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1401576 3.16% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1522530 3.43% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4244947 9.57% 75.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1845094 4.16% 79.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 677475 1.53% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069981 2.41% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7429049 16.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24724412 55.56% 55.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1545163 3.47% 59.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1406842 3.16% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1520478 3.42% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4242713 9.53% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1851895 4.16% 79.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685374 1.54% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070742 2.41% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7456767 16.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44368516 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.368054 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.349641 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15099347 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9823247 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18465046 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 597969 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 382907 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3741515 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100209 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104016227 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 382907 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15487504 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6707215 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96849 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18654699 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3039342 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102867556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4643 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 101006 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 348263 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2491758 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61906530 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124122948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123794647 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 328300 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44504386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368117 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.350397 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15190182 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9797968 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18517517 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 603822 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 394897 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3753615 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100898 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104278713 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 316536 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 394897 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15562376 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4515044 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96153 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18732590 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5203326 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103086111 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6702 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 93508 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 341438 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4700364 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 62061981 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124384146 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124055114 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 329031 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9359649 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5745 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5793 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2522683 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23265731 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16453437 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1244012 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 539260 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91299347 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5639 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89055311 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 77552 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11713229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4714239 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1056 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44368516 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007174 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.246117 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9515100 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5718 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2349661 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23316234 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16465365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246740 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 545757 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91441079 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5553 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89167924 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 83024 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11854875 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4801848 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 970 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44504386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.243462 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17795444 40.11% 40.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5774110 13.01% 53.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5077311 11.44% 64.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4396727 9.91% 74.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4357066 9.82% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2650893 5.97% 90.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1948119 4.39% 94.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1385813 3.12% 97.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 983033 2.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17850579 40.11% 40.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5788896 13.01% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5155949 11.59% 64.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4393297 9.87% 74.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4359248 9.80% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2645472 5.94% 90.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1941559 4.36% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1381555 3.10% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 987831 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44368516 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44504386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243204 9.64% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 244058 9.64% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available @@ -443,118 +445,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1172094 46.45% 56.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1108166 43.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1174802 46.40% 56.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1112961 43.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49651741 55.75% 55.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44157 0.05% 55.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121956 0.14% 55.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121436 0.14% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39055 0.04% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23004684 25.83% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16072139 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49705550 55.74% 55.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44198 0.05% 55.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121960 0.14% 55.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121539 0.14% 56.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39076 0.04% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23058691 25.86% 81.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16076765 18.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89055311 # Type of FU issued -system.cpu.iq.rate 1.972159 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028336 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224465346 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102605449 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87163804 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 614809 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 433844 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 300747 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91271228 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307548 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1661543 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89167924 # Type of FU issued +system.cpu.iq.rate 1.969511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2531821 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028394 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224839378 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102887543 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87218101 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615701 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 435266 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 300894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91391726 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 308019 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1669932 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2989093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6317 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21548 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1840060 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3039596 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21688 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1851988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3023 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 186080 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 205518 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 382907 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1413856 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4974138 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100829471 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 151929 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23265731 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16453437 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5565 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4957861 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21548 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151078 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 158072 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 309150 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88275465 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22814985 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 779846 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 394897 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1352665 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2733681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100982224 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 167502 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23316234 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16465365 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5553 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2732159 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21688 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 162395 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 158558 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 320953 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88354535 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22848688 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 813389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9524485 # number of nop insts executed -system.cpu.iew.exec_refs 38726852 # number of memory reference insts executed -system.cpu.iew.exec_branches 15171568 # Number of branches executed -system.cpu.iew.exec_stores 15911867 # Number of stores executed -system.cpu.iew.exec_rate 1.954889 # Inst execution rate -system.cpu.iew.wb_sent 87882002 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87464551 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33900833 # num instructions producing a value -system.cpu.iew.wb_consumers 44342613 # num instructions consuming a value +system.cpu.iew.exec_nop 9535592 # number of nop insts executed +system.cpu.iew.exec_refs 38764588 # number of memory reference insts executed +system.cpu.iew.exec_branches 15181336 # Number of branches executed +system.cpu.iew.exec_stores 15915900 # Number of stores executed +system.cpu.iew.exec_rate 1.951545 # Inst execution rate +system.cpu.iew.wb_sent 87941007 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87518995 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33890392 # num instructions producing a value +system.cpu.iew.wb_consumers 44346264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.936931 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764520 # average fanout of values written-back +system.cpu.iew.wb_rate 1.933090 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764222 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9282281 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9432406 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 263184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43000551 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.054408 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.876009 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 275041 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43112835 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.049057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.870632 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21467431 49.92% 49.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6329802 14.72% 64.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2918642 6.79% 71.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1760390 4.09% 75.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1670777 3.89% 79.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1138707 2.65% 82.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1203989 2.80% 84.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 794665 1.85% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5716148 13.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21537439 49.96% 49.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6339258 14.70% 64.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2938097 6.81% 71.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1767481 4.10% 75.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1703049 3.95% 79.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1136594 2.64% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1201073 2.79% 84.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 797579 1.85% 86.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5692265 13.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43000551 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43112835 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,343 +602,349 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 133590014 # The number of ROB reads -system.cpu.rob.rob_writes 196617452 # The number of ROB writes -system.cpu.timesIdled 47547 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 787728 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5692265 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 133876306 # The number of ROB reads +system.cpu.rob.rob_writes 196941310 # The number of ROB writes +system.cpu.timesIdled 47582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 769754 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.567348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.567348 # CPI: Total CPI of All Threads -system.cpu.ipc 1.762586 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.762586 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116851082 # number of integer regfile reads -system.cpu.int_regfile_writes 57926468 # number of integer regfile writes -system.cpu.fp_regfile_reads 255690 # number of floating regfile reads -system.cpu.fp_regfile_writes 241313 # number of floating regfile writes -system.cpu.misc_regfile_reads 38160 # number of misc regfile reads +system.cpu.cpi 0.568830 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.568830 # CPI: Total CPI of All Threads +system.cpu.ipc 1.757996 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.757996 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116950893 # number of integer regfile reads +system.cpu.int_regfile_writes 57974920 # number of integer regfile writes +system.cpu.fp_regfile_reads 255771 # number of floating regfile reads +system.cpu.fp_regfile_writes 241359 # number of floating regfile writes +system.cpu.misc_regfile_reads 38164 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.706489 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34086491 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.904910 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 231989000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.706489 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201397 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.850359 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34098493 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205493 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.935059 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 231077500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.850359 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993860 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993860 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2590 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2777 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1229 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71020044 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71020044 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20525035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20525035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561393 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561393 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34086428 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34086428 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34086428 # number of overall hits -system.cpu.dcache.overall_hits::total 34086428 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268817 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268817 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1051984 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1051984 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 71045365 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71045365 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20537317 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20537317 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561115 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561115 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34098432 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34098432 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34098432 # number of overall hits +system.cpu.dcache.overall_hits::total 34098432 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269180 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269180 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052262 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052262 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1320801 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1320801 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1320801 # number of overall misses -system.cpu.dcache.overall_misses::total 1320801 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17503667749 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17503667749 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89467046923 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89467046923 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 99750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106970714672 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106970714672 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106970714672 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106970714672 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20793852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20793852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1321442 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321442 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321442 # number of overall misses +system.cpu.dcache.overall_misses::total 1321442 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17386725500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17386725500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89260696666 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89260696666 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106647422166 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106647422166 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106647422166 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106647422166 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20806497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20806497 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 64 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 64 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35407229 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35407229 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35407229 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35407229 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012928 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012928 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071988 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071988 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015625 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015625 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037303 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037303 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65113.693513 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65113.693513 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85046.014885 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85046.014885 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80989.274442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80989.274442 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6831456 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35419874 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35419874 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35419874 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35419874 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012937 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072007 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072007 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016129 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016129 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037308 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037308 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037308 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037308 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64591.446244 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64591.446244 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84827.444749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84827.444749 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80705.337174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80705.337174 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6894813 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88055 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 88842 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.581693 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.607584 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168921 # number of writebacks -system.cpu.dcache.writebacks::total 168921 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206754 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206754 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908590 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908590 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115344 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115344 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115344 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115344 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62063 # 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number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115950 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62095 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62095 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205457 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205457 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205457 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205457 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3191920501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3191920501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14187677704 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14187677704 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 97750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17379598205 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17379598205 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17379598205 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17379598205 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002985 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002985 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 205492 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205492 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205492 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205492 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3215385000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3215385000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14267732202 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14267732202 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483117202 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17483117202 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17483117202 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17483117202 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.015625 # 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miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007763 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007763 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007763 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007763 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007763 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18890.733893 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18890.733893 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18890.733893 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18890.733893 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18890.733893 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18890.733893 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1636224764 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1636224764 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1636224764 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1636224764 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006828 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006828 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006828 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006828 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006828 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006828 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17223.962483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17223.962483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17223.962483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17223.962483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17223.962483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17223.962483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13251 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 13251 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 13251 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 13251 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 13251 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12290499750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12290499750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 527900750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14712869750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15240770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 527900750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14712869750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15240770500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448415 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.225710 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912033 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912033 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.553264 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.553264 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69278.313648 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87041.681639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 83223.434415 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93977.716564 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93977.716564 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 7382 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 7382 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27861 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27861 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7382 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158642 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166024 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7382 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158642 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166024 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12608258500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12608258500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 528810000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 528810000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2479533500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2479533500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 528810000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15087792000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15616602000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 528810000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15087792000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15616602000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912020 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912020 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077535 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.552121 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.552121 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96407.417744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96407.417744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71635.058250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71635.058250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88996.572269 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88996.572269 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71635.058250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95105.911423 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94062.316292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71635.058250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95105.911423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94062.316292 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 157060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157059 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168921 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189993 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 769830 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6079744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23960256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30040000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 469376 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 157304 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 283196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 143468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 95209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62096 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 283577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612383 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 895960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6093312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23957312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30050624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132107 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 727366 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.181624 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.385534 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 469376 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 595259 81.84% 81.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 132107 18.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 469376 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403609000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 143899236 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 727366 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 466469500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 142819485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 325469999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308243991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35449 # Transaction distribution -system.membus.trans_dist::ReadResp 35449 # Transaction distribution -system.membus.trans_dist::Writeback 114013 # Transaction distribution +system.membus.trans_dist::ReadResp 35242 # Transaction distribution +system.membus.trans_dist::Writeback 114356 # Transaction distribution +system.membus.trans_dist::CleanEvict 15775 # Transaction distribution system.membus.trans_dist::ReadExReq 130781 # Transaction distribution system.membus.trans_dist::ReadExResp 130781 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446473 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446473 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17935552 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 35242 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462177 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17944256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17944256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280243 # Request fanout histogram +system.membus.snoop_fanout::samples 296154 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280243 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 296154 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280243 # Request fanout histogram -system.membus.reqLayer0.occupancy 786749500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 865056500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 296154 # Request fanout histogram +system.membus.reqLayer0.occupancy 778878000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 857917500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c3c27d986..a8d113a77 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057148 # Number of seconds simulated -sim_ticks 57147901500 # Number of ticks simulated -final_tick 57147901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057054 # Number of seconds simulated +sim_ticks 57053790500 # Number of ticks simulated +final_tick 57053790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198372 # Simulator instruction rate (inst/s) -host_op_rate 253689 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 159860838 # Simulator tick rate (ticks/s) -host_mem_usage 323444 # Number of bytes of host memory used -host_seconds 357.49 # Real time elapsed on the host +host_inst_rate 195523 # Simulator instruction rate (inst/s) +host_op_rate 250045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157305109 # Simulator tick rate (ticks/s) +host_mem_usage 323528 # Number of bytes of host memory used +host_seconds 362.70 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923136 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123799 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5672299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138642641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144314940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5672299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5672299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94015701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94015701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94015701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5672299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138642641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 238330641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128864 # Number of read requests accepted -system.physmem.writeReqs 83950 # Number of write requests accepted -system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 319296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924224 # Number of bytes read from this memory +system.physmem.bytes_read::total 8243520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 319296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 319296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5514240 # Number of bytes written to this memory +system.physmem.bytes_written::total 5514240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86160 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86160 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5596403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138890404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144486807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5596403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5596403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96649845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96649845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96649845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5596403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138890404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241136652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128805 # Number of read requests accepted +system.physmem.writeReqs 86160 # Number of write requests accepted +system.physmem.readBursts 128805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86160 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8243200 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side +system.physmem.bytesWritten 5512512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8243520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5514240 # Total written bytes from the system interface side system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::0 8145 # Per bank write bursts system.physmem.perBankRdBursts::1 8375 # Per bank write bursts -system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8317 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8089 # Per bank write bursts -system.physmem.perBankRdBursts::7 7970 # Per bank write bursts -system.physmem.perBankRdBursts::8 8070 # Per bank write bursts -system.physmem.perBankRdBursts::9 7639 # Per bank write bursts -system.physmem.perBankRdBursts::10 7818 # Per bank write bursts -system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::4 8318 # Per bank write bursts +system.physmem.perBankRdBursts::5 8434 # Per bank write bursts +system.physmem.perBankRdBursts::6 8084 # Per bank write bursts +system.physmem.perBankRdBursts::7 7957 # Per bank write bursts +system.physmem.perBankRdBursts::8 8058 # Per bank write bursts +system.physmem.perBankRdBursts::9 7633 # Per bank write bursts +system.physmem.perBankRdBursts::10 7816 # Per bank write bursts +system.physmem.perBankRdBursts::11 7829 # Per bank write bursts system.physmem.perBankRdBursts::12 7882 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts -system.physmem.perBankRdBursts::14 7978 # Per bank write bursts -system.physmem.perBankRdBursts::15 8005 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts -system.physmem.perBankWrBursts::1 5374 # Per bank write bursts -system.physmem.perBankWrBursts::2 5285 # Per bank write bursts -system.physmem.perBankWrBursts::3 5155 # Per bank write bursts -system.physmem.perBankWrBursts::4 5266 # Per bank write bursts -system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5197 # Per bank write bursts -system.physmem.perBankWrBursts::7 5049 # Per bank write bursts -system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5143 # Per bank write bursts -system.physmem.perBankWrBursts::12 5343 # Per bank write bursts -system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5224 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 7996 # Per bank write bursts +system.physmem.perBankWrBursts::0 5393 # Per bank write bursts +system.physmem.perBankWrBursts::1 5541 # Per bank write bursts +system.physmem.perBankWrBursts::2 5463 # Per bank write bursts +system.physmem.perBankWrBursts::3 5328 # Per bank write bursts +system.physmem.perBankWrBursts::4 5352 # Per bank write bursts +system.physmem.perBankWrBursts::5 5550 # Per bank write bursts +system.physmem.perBankWrBursts::6 5247 # Per bank write bursts +system.physmem.perBankWrBursts::7 5180 # Per bank write bursts +system.physmem.perBankWrBursts::8 5155 # Per bank write bursts +system.physmem.perBankWrBursts::9 5102 # Per bank write bursts +system.physmem.perBankWrBursts::10 5289 # Per bank write bursts +system.physmem.perBankWrBursts::11 5270 # Per bank write bursts +system.physmem.perBankWrBursts::12 5531 # Per bank write bursts +system.physmem.perBankWrBursts::13 5597 # Per bank write bursts +system.physmem.perBankWrBursts::14 5703 # Per bank write bursts +system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57147867000 # Total gap between requests +system.physmem.totGap 57053759500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128864 # Read request sizes (log2) +system.physmem.readPktSize::6 128805 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83950 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86160 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12216 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,98 +193,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.471023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.710692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.512328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12078 31.44% 31.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8121 21.14% 52.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4196 10.92% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2833 7.38% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2487 6.47% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1687 4.39% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1308 3.41% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1147 2.99% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4553 11.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38410 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.969750 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.703721 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5155 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.314336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.053807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.949103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12175 31.45% 31.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8182 21.14% 52.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4142 10.70% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2786 7.20% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2727 7.05% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1625 4.20% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1301 3.36% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1172 3.03% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4597 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38707 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.311061 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 351.967739 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5296 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.272833 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.766988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4532 87.88% 87.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 8 0.16% 88.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 487 9.44% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 109 2.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 13 0.25% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 1657207000 # Total ticks spent queuing -system.physmem.totMemAccLat 4073313250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12860.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.259581 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.243681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.749380 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4690 88.54% 88.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.08% 88.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 472 8.91% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads +system.physmem.totQLat 1693807750 # Total ticks spent queuing +system.physmem.totMemAccLat 4108807750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13150.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31610.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 94.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31900.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.86 # Data bus utilization in percentage +system.physmem.busUtil 1.88 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing -system.physmem.readRowHits 112198 # Number of row buffer hits during reads -system.physmem.writeRowHits 62160 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes -system.physmem.avgGap 268534.34 # Average gap between requests -system.physmem.pageHitRate 81.93 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 150580080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82161750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512592600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11751586830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 23977725000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40479283620 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.378781 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39762160500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1908140000 # Time in different power states +system.physmem.avgWrQLen 23.52 # Average write queue length when enqueuing +system.physmem.readRowHits 112096 # Number of row buffer hits during reads +system.physmem.writeRowHits 64121 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.42 # Row buffer hit rate for writes +system.physmem.avgGap 265409.53 # Average gap between requests +system.physmem.pageHitRate 81.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 151956000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82912500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512405400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3726219120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11612859660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24043349250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40408652970 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.301006 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39871864500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1905020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15473270000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15273243000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139769280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76263000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492016200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11244014370 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24422958750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40378823040 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.620851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40500942500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1908140000 # Time in different power states +system.physmem_1.actEnergy 140638680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76737375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491797800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279151920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3726219120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11026970910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24557286750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40298802555 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.375499 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40728832250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1905020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14734649500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14416275250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14823153 # Number of BP lookups -system.cpu.branchPred.condPredicted 9921447 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 393425 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9508830 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6745421 # Number of BTB hits +system.cpu.branchPred.lookups 14816555 # Number of BP lookups +system.cpu.branchPred.condPredicted 9915062 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 392110 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9527196 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6742365 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.938496 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1716328 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.769668 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1716488 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,97 +403,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 114295803 # number of cpu cycles simulated +system.cpu.numCycles 114107581 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1165738 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1163698 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.611727 # CPI: cycles per instruction -system.cpu.ipc 0.620453 # IPC: instructions per cycle -system.cpu.tickCycles 95732462 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18563341 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156421 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.059654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42628242 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160517 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.568395 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 829804250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.059654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992934 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992934 # Average percentage of cache occupancy +system.cpu.cpi 1.609072 # CPI: cycles per instruction +system.cpu.ipc 0.621476 # IPC: instructions per cycle +system.cpu.tickCycles 95702284 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18405297 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156420 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.153595 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42625103 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.550493 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 823362500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.153595 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2909 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86023319 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86023319 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22869697 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22869697 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642191 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642191 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84516 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84516 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86018450 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86018450 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22867482 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22867482 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642183 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642183 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83600 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83600 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42511888 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42511888 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42596404 # number of overall hits -system.cpu.dcache.overall_hits::total 42596404 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51738 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51738 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207710 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 43711 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 43711 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259448 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259448 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303159 # number of overall misses -system.cpu.dcache.overall_misses::total 303159 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1479377187 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1479377187 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16921529000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16921529000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18400906187 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18400906187 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18400906187 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18400906187 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22921435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22921435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42509665 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42509665 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42593265 # number of overall hits +system.cpu.dcache.overall_hits::total 42593265 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51591 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51591 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207718 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207718 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44555 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44555 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259309 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259309 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303864 # number of overall misses +system.cpu.dcache.overall_misses::total 303864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1486882500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1486882500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16821632500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16821632500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18308515000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18308515000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18308515000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18308515000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22919073 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22919073 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128227 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128227 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128155 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128155 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42771336 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42771336 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42899563 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42899563 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002257 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002257 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42768974 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42768974 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42897129 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42897129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002251 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002251 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340888 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.340888 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007067 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007067 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28593.629189 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28593.629189 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81467.088729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81467.088729 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70923.291708 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70923.291708 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60697.212311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60697.212311 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.347665 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.347665 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006063 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006063 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28820.579171 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28820.579171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80983.027470 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80983.027470 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70605.011781 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70605.011781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60252.333281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60252.333281 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,110 +502,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128425 # number of writebacks -system.cpu.dcache.writebacks::total 128425 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22255 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22255 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100680 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100680 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122935 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122935 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122935 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122935 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29483 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29483 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24004 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 24004 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136513 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136513 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160517 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160517 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 559151063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 559151063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8446390250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8446390250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1684744250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1684744250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9005541313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9005541313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10690285563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10690285563 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128380 # number of writebacks +system.cpu.dcache.writebacks::total 128380 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22097 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22097 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100690 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100690 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122787 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122787 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122787 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122787 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29494 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29494 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23994 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23994 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136522 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136522 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160516 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160516 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 572555000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 572555000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8494060500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8494060500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1717129000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1717129000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9066615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10783744500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10783744500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187199 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187199 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187226 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187226 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18965.202422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18965.202422 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78916.100626 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78916.100626 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70185.979420 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70185.979420 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65968.378931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65968.378931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66599.086471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66599.086471 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.592392 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.592392 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79362.975109 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79362.975109 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71564.932900 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71564.932900 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66411.387908 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66411.387908 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67181.742007 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67181.742007 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42924 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.595671 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24987535 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.698417 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42980 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.974873 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24976744 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45022 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 554.767536 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.595671 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904588 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904588 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.974873 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904773 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904773 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 914 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1007 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50109970 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50109970 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24987535 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24987535 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24987535 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24987535 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24987535 # number of overall hits -system.cpu.icache.overall_hits::total 24987535 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44967 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44967 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44967 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44967 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44967 # number of overall misses -system.cpu.icache.overall_misses::total 44967 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 940451988 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 940451988 # 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average overall miss latency +system.cpu.icache.tags.tag_accesses 50088556 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50088556 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24976744 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24976744 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24976744 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24976744 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24976744 # number of overall hits +system.cpu.icache.overall_hits::total 24976744 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 45023 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 45023 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 45023 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 45023 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 45023 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20644.603869 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20644.603869 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20644.603869 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,123 +614,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44967 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44967 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19644.626080 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19644.626080 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19644.626080 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19644.626080 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95727 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29852.290925 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99928 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126845 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.787796 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95667 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955647 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110832 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402614 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402614 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771362 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.626674 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771362 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.626674 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70988.981336 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70988.981336 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69355.110220 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69355.110220 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76818.504760 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76818.504760 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69355.110220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72002.895425 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71900.319085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69355.110220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72002.895425 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71900.319085 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98453 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89933 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 539392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2877824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21370112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333909 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 98510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 214540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 72719 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45023 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53488 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 602669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2881408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18489344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21370752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 95667 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 500606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.191102 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.393170 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 333909 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 404939 80.89% 80.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 95667 19.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333909 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295379500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68407488 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 500606 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 330849500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 67538489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268248937 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26586 # Transaction distribution -system.membus.trans_dist::ReadResp 26586 # Transaction distribution -system.membus.trans_dist::Writeback 83950 # Transaction distribution -system.membus.trans_dist::ReadExReq 102278 # Transaction distribution -system.membus.trans_dist::ReadExResp 102278 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341678 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 240805936 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadResp 26524 # Transaction distribution +system.membus.trans_dist::Writeback 86160 # Transaction distribution +system.membus.trans_dist::CleanEvict 7518 # Transaction distribution +system.membus.trans_dist::ReadExReq 102281 # Transaction distribution +system.membus.trans_dist::ReadExResp 102281 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26524 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 351288 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13757760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13757760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212814 # Request fanout histogram +system.membus.snoop_fanout::samples 222483 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212814 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222483 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212814 # Request fanout histogram -system.membus.reqLayer0.occupancy 578378500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222483 # Request fanout histogram +system.membus.reqLayer0.occupancy 591579500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 680081000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 679724750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 3b7597919..54ac67971 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033331 # Number of seconds simulated -sim_ticks 33330913000 # Number of ticks simulated -final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033295 # Number of seconds simulated +sim_ticks 33294994000 # Number of ticks simulated +final_tick 33294994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123947 # Simulator instruction rate (inst/s) -host_op_rate 158514 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58262578 # Simulator tick rate (ticks/s) -host_mem_usage 323704 # Number of bytes of host memory used -host_seconds 572.08 # Real time elapsed on the host +host_inst_rate 125667 # Simulator instruction rate (inst/s) +host_op_rate 160714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59007684 # Simulator tick rate (ticks/s) +host_mem_usage 325068 # Number of bytes of host memory used +host_seconds 564.25 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 583488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2505024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6203200 # Number of bytes read from this memory -system.physmem.bytes_read::total 9291712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 583488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 583488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6256128 # Number of bytes written to this memory -system.physmem.bytes_written::total 6256128 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96925 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145183 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97752 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17505911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75156177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 186109513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 278771602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17505911 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17505911 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187697469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187697469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187697469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17505911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75156177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 186109513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 466469070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145183 # Number of read requests accepted -system.physmem.writeReqs 97752 # Number of write requests accepted -system.physmem.readBursts 145183 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97752 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9284992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 6254720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9291712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6256128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 579648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2508288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6196352 # Number of bytes read from this memory +system.physmem.bytes_read::total 9284288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 579648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 579648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6263808 # Number of bytes written to this memory +system.physmem.bytes_written::total 6263808 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9057 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39192 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96818 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145067 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97872 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97872 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17409464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75335289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 186104614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 278849367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17409464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17409464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 188130624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 188130624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 188130624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17409464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75335289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 186104614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466979991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145067 # Number of read requests accepted +system.physmem.writeReqs 97872 # Number of write requests accepted +system.physmem.readBursts 145067 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97872 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9276928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 6262080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9284288 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6263808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9145 # Per bank write bursts -system.physmem.perBankRdBursts::1 9372 # Per bank write bursts -system.physmem.perBankRdBursts::2 9233 # Per bank write bursts -system.physmem.perBankRdBursts::3 9500 # Per bank write bursts -system.physmem.perBankRdBursts::4 9743 # Per bank write bursts -system.physmem.perBankRdBursts::5 9700 # Per bank write bursts -system.physmem.perBankRdBursts::6 9083 # Per bank write bursts -system.physmem.perBankRdBursts::7 8995 # Per bank write bursts -system.physmem.perBankRdBursts::8 9233 # Per bank write bursts -system.physmem.perBankRdBursts::9 8567 # Per bank write bursts -system.physmem.perBankRdBursts::10 8856 # Per bank write bursts -system.physmem.perBankRdBursts::11 8704 # Per bank write bursts -system.physmem.perBankRdBursts::12 8629 # Per bank write bursts -system.physmem.perBankRdBursts::13 8694 # Per bank write bursts -system.physmem.perBankRdBursts::14 8697 # Per bank write bursts -system.physmem.perBankRdBursts::15 8927 # Per bank write bursts -system.physmem.perBankWrBursts::0 5993 # Per bank write bursts -system.physmem.perBankWrBursts::1 6233 # Per bank write bursts -system.physmem.perBankWrBursts::2 6131 # Per bank write bursts -system.physmem.perBankWrBursts::3 6188 # Per bank write bursts -system.physmem.perBankWrBursts::4 6147 # Per bank write bursts -system.physmem.perBankWrBursts::5 6290 # Per bank write bursts -system.physmem.perBankWrBursts::6 6056 # Per bank write bursts -system.physmem.perBankWrBursts::7 6014 # Per bank write bursts -system.physmem.perBankWrBursts::8 6000 # Per bank write bursts -system.physmem.perBankWrBursts::9 6152 # Per bank write bursts -system.physmem.perBankWrBursts::10 6228 # Per bank write bursts -system.physmem.perBankWrBursts::11 5920 # Per bank write bursts -system.physmem.perBankWrBursts::12 6078 # Per bank write bursts -system.physmem.perBankWrBursts::13 6086 # Per bank write bursts -system.physmem.perBankWrBursts::14 6193 # Per bank write bursts -system.physmem.perBankWrBursts::15 6021 # Per bank write bursts +system.physmem.perBankRdBursts::0 9133 # Per bank write bursts +system.physmem.perBankRdBursts::1 9402 # Per bank write bursts +system.physmem.perBankRdBursts::2 9189 # Per bank write bursts +system.physmem.perBankRdBursts::3 9501 # Per bank write bursts +system.physmem.perBankRdBursts::4 9688 # Per bank write bursts +system.physmem.perBankRdBursts::5 9749 # Per bank write bursts +system.physmem.perBankRdBursts::6 9050 # Per bank write bursts +system.physmem.perBankRdBursts::7 9017 # Per bank write bursts +system.physmem.perBankRdBursts::8 9142 # Per bank write bursts +system.physmem.perBankRdBursts::9 8554 # Per bank write bursts +system.physmem.perBankRdBursts::10 8859 # Per bank write bursts +system.physmem.perBankRdBursts::11 8689 # Per bank write bursts +system.physmem.perBankRdBursts::12 8621 # Per bank write bursts +system.physmem.perBankRdBursts::13 8707 # Per bank write bursts +system.physmem.perBankRdBursts::14 8654 # Per bank write bursts +system.physmem.perBankRdBursts::15 8997 # Per bank write bursts +system.physmem.perBankWrBursts::0 5994 # Per bank write bursts +system.physmem.perBankWrBursts::1 6239 # Per bank write bursts +system.physmem.perBankWrBursts::2 6113 # Per bank write bursts +system.physmem.perBankWrBursts::3 6223 # Per bank write bursts +system.physmem.perBankWrBursts::4 6099 # Per bank write bursts +system.physmem.perBankWrBursts::5 6360 # Per bank write bursts +system.physmem.perBankWrBursts::6 6100 # Per bank write bursts +system.physmem.perBankWrBursts::7 5988 # Per bank write bursts +system.physmem.perBankWrBursts::8 5999 # Per bank write bursts +system.physmem.perBankWrBursts::9 6164 # Per bank write bursts +system.physmem.perBankWrBursts::10 6223 # Per bank write bursts +system.physmem.perBankWrBursts::11 5911 # Per bank write bursts +system.physmem.perBankWrBursts::12 6098 # Per bank write bursts +system.physmem.perBankWrBursts::13 6094 # Per bank write bursts +system.physmem.perBankWrBursts::14 6156 # Per bank write bursts +system.physmem.perBankWrBursts::15 6084 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33330641500 # Total gap between requests +system.physmem.totGap 33294791000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145183 # Read request sizes (log2) +system.physmem.readPktSize::6 145067 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97752 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 41867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6097 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97872 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 42425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 52688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6069 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 5279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4301 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 3567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,101 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.273178 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.551570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.030923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52157 58.84% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22538 25.42% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4461 5.03% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1758 1.98% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1068 1.20% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 785 0.89% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 713 0.80% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 748 0.84% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4421 4.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88649 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.566130 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.054973 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.117675 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5904 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.366717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.599846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 238.987527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52022 58.71% 58.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22627 25.54% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4475 5.05% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1626 1.84% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1127 1.27% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 853 0.96% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 741 0.84% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 771 0.87% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4363 4.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88605 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.519032 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.016952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 186.911555 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.550381 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.508750 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.243905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4712 79.80% 79.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.49% 80.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 757 12.82% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 163 2.76% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 111 1.88% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 62 1.05% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 43 0.73% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.34% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.10% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads -system.physmem.totQLat 7425181339 # Total ticks spent queuing -system.physmem.totMemAccLat 10145393839 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 725390000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51180.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.553037 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.510340 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.264183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4718 79.82% 79.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.51% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 754 12.76% 93.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 178 3.01% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 93 1.57% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 63 1.07% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 39 0.66% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.30% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.22% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads +system.physmem.totQLat 7210112096 # Total ticks spent queuing +system.physmem.totMemAccLat 9927962096 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 724760000 # Total ticks spent in databus transfers +system.physmem.avgQLat 49741.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 69930.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 278.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 278.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.70 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 68491.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 188.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 278.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 188.13 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.64 # Data bus utilization in percentage +system.physmem.busUtil 3.65 # Data bus utilization in percentage system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing -system.physmem.readRowHits 117819 # Number of row buffer hits during reads -system.physmem.writeRowHits 36329 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.16 # Row buffer hit rate for writes -system.physmem.avgGap 137199.83 # Average gap between requests -system.physmem.pageHitRate 63.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342679680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186978000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 582769200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 317714400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11943657450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9518358000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25068793530 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.242445 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15735797307 # Time in different power states -system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 117862 # Number of row buffer hits during reads +system.physmem.writeRowHits 36326 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.12 # Row buffer hit rate for writes +system.physmem.avgGap 137050.00 # Average gap between requests +system.physmem.pageHitRate 63.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 582823800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318271680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2174602560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11786161320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9637821000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25027725510 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.712810 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15936534744 # Time in different power states +system.physmem_0.memoryStateTime::REF 1111760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16476833443 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16245984006 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 327053160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178451625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 548121600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315264960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11265215805 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10113486000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24924229950 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.904367 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16730540892 # Time in different power states -system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem_1.actEnergy 328217400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179086875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 547723800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315763920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2174602560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11208088125 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10144902750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24898385430 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.828055 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16783464024 # Time in different power states +system.physmem_1.memoryStateTime::REF 1111760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15482244108 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15399360476 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17205793 # Number of BP lookups -system.cpu.branchPred.condPredicted 11516695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648305 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9352037 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7676056 # Number of BTB hits +system.cpu.branchPred.lookups 17206050 # Number of BP lookups +system.cpu.branchPred.condPredicted 11517760 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648066 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9347785 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7673761 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.078974 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1873350 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101557 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.091758 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1873139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -410,95 +411,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66661827 # number of cpu cycles simulated +system.cpu.numCycles 66589989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4979954 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88191186 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17205793 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9549406 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60159688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322593 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6446 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13285 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22768352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68999 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65820694 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.695691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5006781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88183966 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17206050 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9546900 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60089478 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322083 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 23 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13752 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22762089 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69210 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65777829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696584 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296287 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20039717 30.45% 30.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8265549 12.56% 43.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9200264 13.98% 56.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28315164 43.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20002417 30.41% 30.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8264821 12.56% 42.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9199012 13.98% 56.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28311579 43.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65820694 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258106 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322964 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8562659 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19557917 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31575920 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5632021 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492177 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179708 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171007 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101418024 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3051775 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492177 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13320782 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5331170 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 788978 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32236803 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13650784 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99206458 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 984473 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3857341 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 63915 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4307533 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5353775 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103928524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457724306 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115417327 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65777829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258388 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.324283 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8581179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19502182 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31574906 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5627602 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 491960 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179377 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170933 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101404474 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3045182 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 491960 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13335070 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5313056 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 801397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32234531 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13601815 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99199856 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 982546 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3844821 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62523 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4317608 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5297882 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103921297 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457696388 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115410759 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10299298 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18655 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12693692 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24322711 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21993814 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1396246 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2340033 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98168548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 10292071 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12693629 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24321623 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21992796 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1398027 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2340833 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98163899 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 34521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94889336 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694958 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7520484 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20257229 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 94893533 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694347 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7515835 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20236855 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 735 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65820694 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.441634 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150001 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 65777829 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.442637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.149664 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17560123 26.68% 26.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17422684 26.47% 53.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17103546 25.99% 79.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11678791 17.74% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2054563 3.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 987 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17511633 26.62% 26.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17428256 26.50% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17102675 26.00% 79.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11682123 17.76% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2052152 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 990 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65820694 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65777829 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6715459 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6715699 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available @@ -526,118 +527,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11205581 37.37% 59.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12062957 40.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11201748 37.36% 59.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12068794 40.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49498174 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89865 0.09% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24060336 25.36% 77.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21240923 22.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49496640 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89875 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24065423 25.36% 77.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241557 22.38% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94889336 # Type of FU issued -system.cpu.iq.rate 1.423443 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29984036 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315990 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286278153 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105734805 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93465836 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94893533 # Type of FU issued +system.cpu.iq.rate 1.425042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29986279 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315999 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286245314 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105725496 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93465397 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124873254 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124879694 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1363649 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1364211 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1456449 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2030 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11752 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1438076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1455361 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11748 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1437058 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 138616 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 176709 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140354 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 182528 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492177 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 621288 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 454814 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98212928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 491960 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 620291 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 463716 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98208276 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24322711 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21993814 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 24321623 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21992796 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 18601 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1642 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 450257 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11752 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303335 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221647 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524982 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93971179 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23753264 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 918157 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 1628 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 459155 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11748 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302696 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221540 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524236 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93976140 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23758122 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 917393 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9859 # number of nop insts executed -system.cpu.iew.exec_refs 44736876 # number of memory reference insts executed -system.cpu.iew.exec_branches 14252919 # Number of branches executed -system.cpu.iew.exec_stores 20983612 # Number of stores executed -system.cpu.iew.exec_rate 1.409670 # Inst execution rate -system.cpu.iew.wb_sent 93587571 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93465893 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44982416 # num instructions producing a value -system.cpu.iew.wb_consumers 76564206 # num instructions consuming a value +system.cpu.iew.exec_nop 9856 # number of nop insts executed +system.cpu.iew.exec_refs 44743070 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251776 # Number of branches executed +system.cpu.iew.exec_stores 20984948 # Number of stores executed +system.cpu.iew.exec_rate 1.411265 # Inst execution rate +system.cpu.iew.wb_sent 93586994 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93465454 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44981756 # num instructions producing a value +system.cpu.iew.wb_consumers 76565949 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.402090 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587512 # average fanout of values written-back +system.cpu.iew.wb_rate 1.403596 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587490 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6539953 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6535729 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479186 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64761460 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.400341 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.165093 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 478985 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64719651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.401246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164864 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31172018 48.13% 48.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16800427 25.94% 74.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4337432 6.70% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4161423 6.43% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935218 2.99% 90.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1264756 1.95% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 739046 1.14% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579471 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3771669 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31116285 48.08% 48.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16809912 25.97% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4342534 6.71% 80.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4161990 6.43% 87.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1938865 3.00% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1263903 1.95% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 739138 1.14% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 578808 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3768216 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64761460 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64719651 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -683,379 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3771669 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158192582 # The number of ROB reads -system.cpu.rob.rob_writes 195517129 # The number of ROB writes -system.cpu.timesIdled 23763 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 841133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3768216 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158150002 # The number of ROB reads +system.cpu.rob.rob_writes 195507605 # The number of ROB writes +system.cpu.timesIdled 23773 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 812160 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940122 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940122 # CPI: Total CPI of All Threads -system.cpu.ipc 1.063692 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.063692 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102266688 # number of integer regfile reads -system.cpu.int_regfile_writes 56794481 # number of integer regfile writes +system.cpu.cpi 0.939109 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.939109 # CPI: Total CPI of All Threads +system.cpu.ipc 1.064839 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.064839 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102273698 # number of integer regfile reads +system.cpu.int_regfile_writes 56793498 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346084159 # number of cc regfile reads -system.cpu.cc_regfile_writes 38805382 # number of cc regfile writes -system.cpu.misc_regfile_reads 44209334 # number of misc regfile reads +system.cpu.cc_regfile_reads 346096996 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804962 # number of cc regfile writes +system.cpu.misc_regfile_reads 44209976 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485106 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.740457 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40427935 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485618 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.250487 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 152807000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.740457 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997540 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997540 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485041 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.740827 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40418511 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485553 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.242223 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152851500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.740827 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997541 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997541 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84615616 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84615616 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21501539 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21501539 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18833357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18833357 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 61715 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 61715 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84611501 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84611501 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21495962 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21495962 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831064 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831064 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15352 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15352 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40334896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40334896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40396611 # number of overall hits -system.cpu.dcache.overall_hits::total 40396611 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 552871 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 552871 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1016544 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1016544 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 67128 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 67128 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1569415 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1569415 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636543 # number of overall misses -system.cpu.dcache.overall_misses::total 1636543 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9102953011 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9102953011 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14661434456 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14661434456 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23764387467 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23764387467 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23764387467 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23764387467 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054410 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054410 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40327026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40327026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40387214 # number of overall hits +system.cpu.dcache.overall_hits::total 40387214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 556411 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 556411 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018837 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018837 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68667 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68667 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 574 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 574 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1575248 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575248 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1643915 # number of overall misses +system.cpu.dcache.overall_misses::total 1643915 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8968261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8968261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14556255401 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14556255401 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4964500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4964500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23524516401 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23524516401 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23524516401 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23524516401 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22052373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22052373 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128843 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128843 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033154 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033154 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025069 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025069 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051212 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521006 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.521006 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037452 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037452 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038935 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038935 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16464.876998 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16464.876998 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14422.823268 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14422.823268 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9348.263254 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9348.263254 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15142.194682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15142.194682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14521.089557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14521.089557 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3013610 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 128472 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.457329 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41902274 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41902274 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42031129 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42031129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025231 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025231 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051327 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051327 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532901 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532901 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16118.051225 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16118.051225 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14287.128757 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14287.128757 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8648.954704 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8648.954704 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14933.849401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14933.849401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14310.056421 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14310.056421 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 45 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3094334 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 130016 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.625000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.799640 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 264409 # number of writebacks -system.cpu.dcache.writebacks::total 264409 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253375 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 253375 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868011 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868011 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1121386 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1121386 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1121386 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1121386 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299496 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299496 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37600 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37600 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448029 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448029 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485629 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485629 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3035888114 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3035888114 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279411901 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279411901 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2033283784 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2033283784 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5315300015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5315300015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7348583799 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7348583799 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013580 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 256956 # number of writebacks +system.cpu.dcache.writebacks::total 256956 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256971 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 256971 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870307 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870307 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 574 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 574 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1127278 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1127278 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1127278 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1127278 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299440 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299440 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148530 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148530 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37596 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37596 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447970 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447970 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3182608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3182608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2345597960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2345597960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2017960000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2017960000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5528206460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5528206460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7546166460 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7546166460 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013579 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291828 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291828 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010692 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010692 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010691 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011553 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.011553 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10136.656630 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10136.656630 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15346.164832 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15346.164832 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54076.696383 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54076.696383 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11863.740997 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11863.740997 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15132.094251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15132.094251 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10628.534932 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10628.534932 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15792.082138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15792.082138 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53674.859028 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53674.859028 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12340.572940 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12340.572940 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15540.969631 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15540.969631 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322771 # number of replacements -system.cpu.icache.tags.tagsinuse 510.304013 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22435446 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323283 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.398781 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1099609250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.304013 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.replacements 322718 # number of replacements +system.cpu.icache.tags.tagsinuse 510.301604 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22427944 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323227 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.387594 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1102167500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.301604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996683 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996683 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 354 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 347 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45859770 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45859770 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22435446 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22435446 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22435446 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22435446 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22435446 # number of overall hits -system.cpu.icache.overall_hits::total 22435446 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 332792 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 332792 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 332792 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 332792 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 332792 # number of overall misses -system.cpu.icache.overall_misses::total 332792 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3372368098 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3372368098 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3372368098 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3372368098 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3372368098 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3372368098 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22768238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22768238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22768238 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22768238 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22768238 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22768238 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014617 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014617 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014617 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014617 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014617 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014617 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10133.561197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10133.561197 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10133.561197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10133.561197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10133.561197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10133.561197 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 259166 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14826 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45847164 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45847164 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22427950 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22427950 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22427950 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22427950 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22427950 # number of overall hits +system.cpu.icache.overall_hits::total 22427950 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334012 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334012 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334012 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334012 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334012 # number of overall misses +system.cpu.icache.overall_misses::total 334012 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3359547390 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3359547390 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3359547390 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3359547390 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3359547390 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3359547390 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22761962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22761962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22761962 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22761962 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22761962 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22761962 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014674 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014674 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014674 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014674 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014674 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014674 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10058.163749 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10058.163749 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10058.163749 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10058.163749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10058.163749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10058.163749 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 273191 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 314 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16668 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.480507 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.390149 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2623 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11971 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 617 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 894 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001465 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.992493 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17467290 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17467290 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76545.123938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69779.012833 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78121.134641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90510.811957 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.198705 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96833.015054 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77197.331885 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77197.331885 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71792.315336 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71792.315336 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80574.686984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80574.686984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71792.315336 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79860.902735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78346.318058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71792.315336 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79860.902735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91282.795754 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 660341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 660341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 264409 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 151292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148571 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646576 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1882243 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20690048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48001728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 151304 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.123542 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 660226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 354828 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 502259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 152780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336986 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2345500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20686336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47520576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68206912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 281979 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1898528 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.148517 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.355611 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1073332 87.65% 87.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 151292 12.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1616565 85.15% 85.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 281963 14.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486570693 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1898528 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1065238500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 485020678 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 734618165 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728403365 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 137030 # Transaction distribution -system.membus.trans_dist::ReadResp 137030 # Transaction distribution -system.membus.trans_dist::Writeback 97752 # Transaction distribution +system.membus.trans_dist::ReadResp 136784 # Transaction distribution +system.membus.trans_dist::Writeback 97872 # Transaction distribution +system.membus.trans_dist::CleanEvict 30200 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8153 # Transaction distribution -system.membus.trans_dist::ReadExResp 8153 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 388130 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15547840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15547840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8283 # Transaction distribution +system.membus.trans_dist::ReadExResp 8283 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 136784 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 418218 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15548096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15548096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 242941 # Request fanout histogram +system.membus.snoop_fanout::samples 273145 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 242941 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 273145 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 242941 # Request fanout histogram -system.membus.reqLayer0.occupancy 691321050 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 757153835 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 273145 # Request fanout histogram +system.membus.reqLayer0.occupancy 717072511 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 756625908 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 959bae132..baff53399 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.211096 # Number of seconds simulated -sim_ticks 1211096219500 # Number of ticks simulated -final_tick 1211096219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.209315 # Number of seconds simulated +sim_ticks 1209314565500 # Number of ticks simulated +final_tick 1209314565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 325701 # Simulator instruction rate (inst/s) -host_op_rate 325701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 215976885 # Simulator tick rate (ticks/s) -host_mem_usage 296636 # Number of bytes of host memory used -host_seconds 5607.53 # Real time elapsed on the host +host_inst_rate 310001 # Simulator instruction rate (inst/s) +host_op_rate 310001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205263152 # Simulator tick rate (ticks/s) +host_mem_usage 296916 # Number of bytes of host memory used +host_seconds 5891.53 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125445568 # Number of bytes read from this memory -system.physmem.bytes_read::total 125506880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124968128 # Number of bytes read from this memory +system.physmem.bytes_read::total 125029440 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65168832 # Number of bytes written to this memory -system.physmem.bytes_written::total 65168832 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65415808 # Number of bytes written to this memory +system.physmem.bytes_written::total 65415808 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960087 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961045 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018263 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018263 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103580183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103630808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 53809789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 53809789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 53809789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103580183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157440597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961045 # Number of read requests accepted -system.physmem.writeReqs 1018263 # Number of write requests accepted -system.physmem.readBursts 1961045 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018263 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125425280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81600 # Total number of bytes read from write queue -system.physmem.bytesWritten 65167232 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125506880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65168832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1275 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 1952627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1953585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022122 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022122 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103337983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103388683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54093294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54093294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54093294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103337983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157481977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1953585 # Number of read requests accepted +system.physmem.writeReqs 1022122 # Number of write requests accepted +system.physmem.readBursts 1953585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1022122 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 124947328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue +system.physmem.bytesWritten 65414528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125029440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65415808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118758 # Per bank write bursts -system.physmem.perBankRdBursts::1 114090 # Per bank write bursts -system.physmem.perBankRdBursts::2 116233 # Per bank write bursts -system.physmem.perBankRdBursts::3 117775 # Per bank write bursts -system.physmem.perBankRdBursts::4 117826 # Per bank write bursts -system.physmem.perBankRdBursts::5 117520 # Per bank write bursts -system.physmem.perBankRdBursts::6 119879 # Per bank write bursts -system.physmem.perBankRdBursts::7 124540 # Per bank write bursts -system.physmem.perBankRdBursts::8 126979 # Per bank write bursts -system.physmem.perBankRdBursts::9 130098 # Per bank write bursts -system.physmem.perBankRdBursts::10 128644 # Per bank write bursts -system.physmem.perBankRdBursts::11 130342 # Per bank write bursts -system.physmem.perBankRdBursts::12 126070 # Per bank write bursts -system.physmem.perBankRdBursts::13 125249 # Per bank write bursts -system.physmem.perBankRdBursts::14 122589 # Per bank write bursts -system.physmem.perBankRdBursts::15 123178 # Per bank write bursts -system.physmem.perBankWrBursts::0 61223 # Per bank write bursts -system.physmem.perBankWrBursts::1 61482 # Per bank write bursts -system.physmem.perBankWrBursts::2 60569 # Per bank write bursts -system.physmem.perBankWrBursts::3 61241 # Per bank write bursts -system.physmem.perBankWrBursts::4 61665 # Per bank write bursts -system.physmem.perBankWrBursts::5 63100 # Per bank write bursts -system.physmem.perBankWrBursts::6 64149 # Per bank write bursts -system.physmem.perBankWrBursts::7 65619 # Per bank write bursts -system.physmem.perBankWrBursts::8 65334 # Per bank write bursts -system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65299 # Per bank write bursts -system.physmem.perBankWrBursts::11 65645 # Per bank write bursts -system.physmem.perBankWrBursts::12 64166 # Per bank write bursts -system.physmem.perBankWrBursts::13 64211 # Per bank write bursts -system.physmem.perBankWrBursts::14 64570 # Per bank write bursts -system.physmem.perBankWrBursts::15 64186 # Per bank write bursts +system.physmem.perBankRdBursts::0 118324 # Per bank write bursts +system.physmem.perBankRdBursts::1 113533 # Per bank write bursts +system.physmem.perBankRdBursts::2 115739 # Per bank write bursts +system.physmem.perBankRdBursts::3 117256 # Per bank write bursts +system.physmem.perBankRdBursts::4 117310 # Per bank write bursts +system.physmem.perBankRdBursts::5 117130 # Per bank write bursts +system.physmem.perBankRdBursts::6 119399 # Per bank write bursts +system.physmem.perBankRdBursts::7 124116 # Per bank write bursts +system.physmem.perBankRdBursts::8 126631 # Per bank write bursts +system.physmem.perBankRdBursts::9 129581 # Per bank write bursts +system.physmem.perBankRdBursts::10 128158 # Per bank write bursts +system.physmem.perBankRdBursts::11 129926 # Per bank write bursts +system.physmem.perBankRdBursts::12 125582 # Per bank write bursts +system.physmem.perBankRdBursts::13 124841 # Per bank write bursts +system.physmem.perBankRdBursts::14 122135 # Per bank write bursts +system.physmem.perBankRdBursts::15 122641 # Per bank write bursts +system.physmem.perBankWrBursts::0 61422 # Per bank write bursts +system.physmem.perBankWrBursts::1 61664 # Per bank write bursts +system.physmem.perBankWrBursts::2 60721 # Per bank write bursts +system.physmem.perBankWrBursts::3 61393 # Per bank write bursts +system.physmem.perBankWrBursts::4 61822 # Per bank write bursts +system.physmem.perBankWrBursts::5 63305 # Per bank write bursts +system.physmem.perBankWrBursts::6 64352 # Per bank write bursts +system.physmem.perBankWrBursts::7 65861 # Per bank write bursts +system.physmem.perBankWrBursts::8 65572 # Per bank write bursts +system.physmem.perBankWrBursts::9 66032 # Per bank write bursts +system.physmem.perBankWrBursts::10 65638 # Per bank write bursts +system.physmem.perBankWrBursts::11 65947 # Per bank write bursts +system.physmem.perBankWrBursts::12 64508 # Per bank write bursts +system.physmem.perBankWrBursts::13 64525 # Per bank write bursts +system.physmem.perBankWrBursts::14 64898 # Per bank write bursts +system.physmem.perBankWrBursts::15 64442 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1211096102000 # Total gap between requests +system.physmem.totGap 1209314463000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961045 # Read request sizes (log2) +system.physmem.readPktSize::6 1953585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018263 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1837965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121788 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1022122 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1829869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122416 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -193,129 +193,136 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1839625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.602019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.031630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.543213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1461173 79.43% 79.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261967 14.24% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48998 2.66% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20657 1.12% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13124 0.71% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7476 0.41% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5272 0.29% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4494 0.24% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16464 0.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1839625 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59444 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.966456 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 164.214090 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59406 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59444 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.129365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.093444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.113658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27743 46.67% 46.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1259 2.12% 48.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26068 43.85% 92.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3874 6.52% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 419 0.70% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 52 0.09% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 24 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59444 # Writes before turning the bus around for reads -system.physmem.totQLat 36839321750 # Total ticks spent queuing -system.physmem.totMemAccLat 73585009250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798850000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18797.78 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1831684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.926852 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.136404 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.467751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1453241 79.34% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261868 14.30% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48841 2.67% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20589 1.12% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13172 0.72% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7181 0.39% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5391 0.29% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4514 0.25% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16887 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1831684 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.743530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 149.210927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59467 99.74% 99.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 109 0.18% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 6 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 6 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-13823 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 59621 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.143322 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.107211 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.116873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27512 46.14% 46.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1216 2.04% 48.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26386 44.26% 92.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3971 6.66% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 453 0.76% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 62 0.10% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 9 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59621 # Writes before turning the bus around for reads +system.physmem.totQLat 36542895500 # Total ticks spent queuing +system.physmem.totMemAccLat 73148558000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9761510000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18717.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37547.78 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 53.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 53.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37467.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing -system.physmem.readRowHits 725244 # Number of row buffer hits during reads -system.physmem.writeRowHits 413130 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.57 # Row buffer hit rate for writes -system.physmem.avgGap 406502.48 # Average gap between requests -system.physmem.pageHitRate 38.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6747186600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3681500625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7383597000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3233831040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416789244855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361048893750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 877986693390 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.956282 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 597858043000 # Time in different power states -system.physmem_0.memoryStateTime::REF 40440920000 # Time in different power states +system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing +system.physmem.readRowHits 723569 # Number of row buffer hits during reads +system.physmem.writeRowHits 419148 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes +system.physmem.avgGap 406395.68 # Average gap between requests +system.physmem.pageHitRate 38.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6717619440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3665367750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7353894600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3243499200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78986487840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416110602285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 360579035250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 876656506365 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.920562 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 597088834750 # Time in different power states +system.physmem_0.memoryStateTime::REF 40381640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 572793401000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 571843431500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7160348160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3906936000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7901891400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3364351200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 428401624860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 350862595500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 880700186640 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.196822 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 580834507250 # Time in different power states -system.physmem_1.memoryStateTime::REF 40440920000 # Time in different power states +system.physmem_1.actEnergy 7129911600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3890328750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7873975200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3379721760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78986487840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 426511213875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351455691750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 879227330775 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.046416 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 581836550250 # Time in different power states +system.physmem_1.memoryStateTime::REF 40381640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 589813744000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587095716000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246195404 # Number of BP lookups -system.cpu.branchPred.condPredicted 186411563 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15682149 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167682775 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165241760 # Number of BTB hits +system.cpu.branchPred.lookups 246216332 # Number of BP lookups +system.cpu.branchPred.condPredicted 186427958 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15694657 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167633562 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165258832 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.544266 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18427120 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104306 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.583380 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18428300 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104795 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452923392 # DTB read hits -system.cpu.dtb.read_misses 4979932 # DTB read misses +system.cpu.dtb.read_hits 452931478 # DTB read hits +system.cpu.dtb.read_misses 4979966 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457903324 # DTB read accesses -system.cpu.dtb.write_hits 161377581 # DTB write hits -system.cpu.dtb.write_misses 1710142 # DTB write misses +system.cpu.dtb.read_accesses 457911444 # DTB read accesses +system.cpu.dtb.write_hits 161379324 # DTB write hits +system.cpu.dtb.write_misses 1710368 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163087723 # DTB write accesses -system.cpu.dtb.data_hits 614300973 # DTB hits -system.cpu.dtb.data_misses 6690074 # DTB misses +system.cpu.dtb.write_accesses 163089692 # DTB write accesses +system.cpu.dtb.data_hits 614310802 # DTB hits +system.cpu.dtb.data_misses 6690334 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620991047 # DTB accesses -system.cpu.itb.fetch_hits 598257344 # ITB hits +system.cpu.dtb.data_accesses 621001136 # DTB accesses +system.cpu.itb.fetch_hits 598312460 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598257363 # ITB accesses +system.cpu.itb.fetch_accesses 598312479 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,82 +336,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2422192439 # number of cpu cycles simulated +system.cpu.numCycles 2418629131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52052944 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52090489 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.326227 # CPI: cycles per instruction -system.cpu.ipc 0.754019 # IPC: instructions per cycle -system.cpu.tickCycles 2076133627 # Number of cycles that the object actually ticked -system.cpu.idleCycles 346058812 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121955 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.744039 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601604629 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.921682 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16824784000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.744039 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996275 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996275 # Average percentage of cache occupancy +system.cpu.cpi 1.324276 # CPI: cycles per instruction +system.cpu.ipc 0.755130 # IPC: instructions per cycle +system.cpu.tickCycles 2076311536 # Number of cycles that the object actually ticked +system.cpu.idleCycles 342317595 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121994 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.733344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601608000 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126090 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.921769 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16821289500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.733344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1544 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2417 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1558 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231402079 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231402079 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443119981 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443119981 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158484648 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158484648 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601604629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601604629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601604629 # number of overall hits -system.cpu.dcache.overall_hits::total 601604629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289531 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289531 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2243854 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2243854 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9533385 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9533385 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9533385 # number of overall misses -system.cpu.dcache.overall_misses::total 9533385 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 186817706000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 186817706000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108924057250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108924057250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 295741763250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 295741763250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 295741763250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 295741763250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450409512 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450409512 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231414126 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231414126 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443125970 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443125970 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158482030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158482030 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601608000 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601608000 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601608000 # number of overall hits +system.cpu.dcache.overall_hits::total 601608000 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289546 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289546 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246472 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246472 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9536018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9536018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9536018 # number of overall misses +system.cpu.dcache.overall_misses::total 9536018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185444020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185444020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108463697500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108463697500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 293907717500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 293907717500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 293907717500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 293907717500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450415516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450415516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611138014 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611138014 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611138014 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611138014 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 611144018 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611144018 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611144018 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611144018 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016184 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016184 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013961 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013961 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015599 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015599 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015599 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015599 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25628.220252 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25628.220252 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48543.290807 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48543.290807 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31021.695153 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31021.695153 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31021.695153 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31021.695153 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015604 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015604 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015604 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015604 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25439.721486 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25439.721486 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48281.793630 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48281.793630 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30820.801460 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30820.801460 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30820.801460 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30820.801460 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,32 +420,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700563 # number of writebacks -system.cpu.dcache.writebacks::total 3700563 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50798 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50798 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 356536 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 356536 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 407334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 407334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 407334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 407334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238733 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238733 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887318 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887318 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126051 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126051 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126051 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126051 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174355280750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 174355280750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82395435500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82395435500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256750716250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 256750716250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256750716250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 256750716250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3686660 # number of writebacks +system.cpu.dcache.writebacks::total 3686660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50795 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50795 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359133 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 359133 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 409928 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 409928 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 409928 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 409928 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238751 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238751 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887339 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887339 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126090 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126090 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126090 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126090 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176979090000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 176979090000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83292376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83292376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260271466000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260271466000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260271466000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260271466000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016071 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016071 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -447,67 +454,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014933 system.cpu.dcache.demand_mshr_miss_rate::total 0.014933 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014933 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014933 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24086.436224 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24086.436224 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43657.420477 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43657.420477 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28133.824395 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28133.824395 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28133.824395 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28133.824395 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.843454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.843454 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44132.175513 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44132.175513 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.493671 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.493671 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.493671 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.493671 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 751.308351 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 598256386 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 751.748828 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 598311502 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624484.745303 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 624542.277662 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 751.308351 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366850 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 751.748828 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.367065 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.367065 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 875 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1196515646 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1196515646 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598256386 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598256386 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 598256386 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 598256386 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 598256386 # number of overall hits -system.cpu.icache.overall_hits::total 598256386 # number of overall hits +system.cpu.icache.tags.tag_accesses 1196625878 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1196625878 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 598311502 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 598311502 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 598311502 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 958 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 958 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238751 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7238751 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 958 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9126051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127009 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9126090 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127048 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413555 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161921 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161921 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214779 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.213961 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214043 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214779 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214862 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77223.382046 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87654.336644 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 87645.879633 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88282.333512 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88282.333512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77223.382046 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87904.062932 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87898.845259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77223.382046 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87904.062932 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87898.845259 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213961 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214043 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88108.328059 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88108.328059 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77687.369520 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77687.369520 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87358.078899 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87358.078899 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77687.369520 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87657.973848 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87653.084458 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77687.369520 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87657.973848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87653.084458 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,105 +649,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018263 # number of writebacks -system.cpu.l2cache.writebacks::total 1018263 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1180648 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181606 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 779439 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779439 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1022122 # number of writebacks +system.cpu.l2cache.writebacks::total 1022122 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 245 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 245 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780518 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 780518 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 958 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 958 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172109 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172109 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1960087 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961045 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1952627 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1953585 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1960087 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961045 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61981000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88565561250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 88627542250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58963288250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58963288250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61981000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147528849500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 147590830500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61981000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147528849500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 147590830500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163101 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163212 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412988 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1952627 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1953585 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60964956000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60964956000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64844500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64844500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90672100500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90672100500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64844500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151637056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 151701901000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64844500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151637056500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 151701901000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413555 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413555 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161921 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161921 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214862 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213961 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214043 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214862 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64698.329854 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75014.366052 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75006.002212 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75648.367929 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75648.367929 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64698.329854 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64698.329854 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213961 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214043 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78108.328059 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78108.328059 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67687.369520 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67687.369520 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77358.078899 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77358.078899 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67687.369520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77657.973848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.084458 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67687.369520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77657.973848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.084458 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887318 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952665 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954581 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 7239709 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4708782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6334073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238751 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27376093 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820903296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820964608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827572 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820016000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820077312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1920858 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20169903 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.095234 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.293538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827572 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18249045 90.48% 90.48% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1920858 9.52% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827572 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114349000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1637500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20169903 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12811182500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14015266250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181606 # Transaction distribution -system.membus.trans_dist::ReadResp 1181606 # Transaction distribution -system.membus.trans_dist::Writeback 1018263 # Transaction distribution -system.membus.trans_dist::ReadExReq 779439 # Transaction distribution -system.membus.trans_dist::ReadExResp 779439 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940353 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940353 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190675712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 13689135000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1173067 # Transaction distribution +system.membus.trans_dist::Writeback 1022122 # Transaction distribution +system.membus.trans_dist::CleanEvict 897712 # Transaction distribution +system.membus.trans_dist::ReadExReq 780518 # Transaction distribution +system.membus.trans_dist::ReadExResp 780518 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1173067 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5827004 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190445248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190445248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979308 # Request fanout histogram +system.membus.snoop_fanout::samples 3873419 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3873419 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979308 # Request fanout histogram -system.membus.reqLayer0.occupancy 7754390500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 10727987500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3873419 # Request fanout histogram +system.membus.reqLayer0.occupancy 8427454000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 10685206000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 58eeef87c..fd8f8a2dd 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.672882 # Number of seconds simulated -sim_ticks 672881519500 # Number of ticks simulated -final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.671755 # Number of seconds simulated +sim_ticks 671754803000 # Number of ticks simulated +final_tick 671754803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165835 # Simulator instruction rate (inst/s) -host_op_rate 165835 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64276745 # Simulator tick rate (ticks/s) -host_mem_usage 226308 # Number of bytes of host memory used -host_seconds 10468.51 # Real time elapsed on the host +host_inst_rate 168955 # Simulator instruction rate (inst/s) +host_op_rate 168955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65376371 # Simulator tick rate (ticks/s) +host_mem_usage 298196 # Number of bytes of host memory used +host_seconds 10275.19 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 62400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125964544 # Number of bytes read from this memory -system.physmem.bytes_read::total 126026944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125486976 # Number of bytes read from this memory +system.physmem.bytes_read::total 125549376 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 62400 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 62400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65296192 # Number of bytes written to this memory -system.physmem.bytes_written::total 65296192 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65552256 # Number of bytes written to this memory +system.physmem.bytes_written::total 65552256 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 975 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968196 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969171 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020253 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020253 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 187201670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 187294405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97039657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97039657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97039657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 187201670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 284334062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969171 # Number of read requests accepted -system.physmem.writeReqs 1020253 # Number of write requests accepted -system.physmem.readBursts 1969171 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020253 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125945600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue -system.physmem.bytesWritten 65294336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126026944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65296192 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 1960734 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961709 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1024254 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1024254 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 186804732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186897623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97583606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97583606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97583606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 186804732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 284481229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961709 # Number of read requests accepted +system.physmem.writeReqs 1024254 # Number of write requests accepted +system.physmem.readBursts 1961709 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1024254 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125464000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 85376 # Total number of bytes read from write queue +system.physmem.bytesWritten 65551040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125549376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65552256 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1334 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119102 # Per bank write bursts -system.physmem.perBankRdBursts::1 114505 # Per bank write bursts -system.physmem.perBankRdBursts::2 116613 # Per bank write bursts -system.physmem.perBankRdBursts::3 118153 # Per bank write bursts -system.physmem.perBankRdBursts::4 118234 # Per bank write bursts -system.physmem.perBankRdBursts::5 117885 # Per bank write bursts -system.physmem.perBankRdBursts::6 120369 # Per bank write bursts -system.physmem.perBankRdBursts::7 125035 # Per bank write bursts -system.physmem.perBankRdBursts::8 127648 # Per bank write bursts -system.physmem.perBankRdBursts::9 130593 # Per bank write bursts -system.physmem.perBankRdBursts::10 129299 # Per bank write bursts -system.physmem.perBankRdBursts::11 130947 # Per bank write bursts -system.physmem.perBankRdBursts::12 126747 # Per bank write bursts -system.physmem.perBankRdBursts::13 125863 # Per bank write bursts -system.physmem.perBankRdBursts::14 123089 # Per bank write bursts -system.physmem.perBankRdBursts::15 123818 # Per bank write bursts -system.physmem.perBankWrBursts::0 61291 # Per bank write bursts -system.physmem.perBankWrBursts::1 61585 # Per bank write bursts -system.physmem.perBankWrBursts::2 60661 # Per bank write bursts -system.physmem.perBankWrBursts::3 61360 # Per bank write bursts -system.physmem.perBankWrBursts::4 61790 # Per bank write bursts -system.physmem.perBankWrBursts::5 63221 # Per bank write bursts -system.physmem.perBankWrBursts::6 64275 # Per bank write bursts -system.physmem.perBankWrBursts::7 65726 # Per bank write bursts -system.physmem.perBankWrBursts::8 65508 # Per bank write bursts -system.physmem.perBankWrBursts::9 65914 # Per bank write bursts -system.physmem.perBankWrBursts::10 65448 # Per bank write bursts -system.physmem.perBankWrBursts::11 65777 # Per bank write bursts -system.physmem.perBankWrBursts::12 64328 # Per bank write bursts -system.physmem.perBankWrBursts::13 64347 # Per bank write bursts -system.physmem.perBankWrBursts::14 64660 # Per bank write bursts -system.physmem.perBankWrBursts::15 64333 # Per bank write bursts +system.physmem.perBankRdBursts::0 118672 # Per bank write bursts +system.physmem.perBankRdBursts::1 113926 # Per bank write bursts +system.physmem.perBankRdBursts::2 116092 # Per bank write bursts +system.physmem.perBankRdBursts::3 117630 # Per bank write bursts +system.physmem.perBankRdBursts::4 117777 # Per bank write bursts +system.physmem.perBankRdBursts::5 117495 # Per bank write bursts +system.physmem.perBankRdBursts::6 119900 # Per bank write bursts +system.physmem.perBankRdBursts::7 124641 # Per bank write bursts +system.physmem.perBankRdBursts::8 127326 # Per bank write bursts +system.physmem.perBankRdBursts::9 130085 # Per bank write bursts +system.physmem.perBankRdBursts::10 128786 # Per bank write bursts +system.physmem.perBankRdBursts::11 130484 # Per bank write bursts +system.physmem.perBankRdBursts::12 126296 # Per bank write bursts +system.physmem.perBankRdBursts::13 125416 # Per bank write bursts +system.physmem.perBankRdBursts::14 122597 # Per bank write bursts +system.physmem.perBankRdBursts::15 123252 # Per bank write bursts +system.physmem.perBankWrBursts::0 61496 # Per bank write bursts +system.physmem.perBankWrBursts::1 61762 # Per bank write bursts +system.physmem.perBankWrBursts::2 60827 # Per bank write bursts +system.physmem.perBankWrBursts::3 61508 # Per bank write bursts +system.physmem.perBankWrBursts::4 61962 # Per bank write bursts +system.physmem.perBankWrBursts::5 63415 # Per bank write bursts +system.physmem.perBankWrBursts::6 64494 # Per bank write bursts +system.physmem.perBankWrBursts::7 65970 # Per bank write bursts +system.physmem.perBankWrBursts::8 65774 # Per bank write bursts +system.physmem.perBankWrBursts::9 66157 # Per bank write bursts +system.physmem.perBankWrBursts::10 65800 # Per bank write bursts +system.physmem.perBankWrBursts::11 66076 # Per bank write bursts +system.physmem.perBankWrBursts::12 64701 # Per bank write bursts +system.physmem.perBankWrBursts::13 64671 # Per bank write bursts +system.physmem.perBankWrBursts::14 65003 # Per bank write bursts +system.physmem.perBankWrBursts::15 64619 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 672881423000 # Total gap between requests +system.physmem.totGap 671754707500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969171 # Read request sizes (log2) +system.physmem.readPktSize::6 1961709 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020253 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1621016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 243733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1024254 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1618535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 64414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -193,143 +193,150 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1777587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.583217 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.835342 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.553801 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1382839 77.79% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271264 15.26% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53815 3.03% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21128 1.19% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12924 0.73% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6598 0.37% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5024 0.28% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3881 0.22% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20114 1.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1777587 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59878 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.821905 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.087941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59840 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59878 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.038378 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.996376 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.234472 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31771 53.06% 53.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1453 2.43% 55.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 20992 35.06% 90.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4585 7.66% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 809 1.35% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 191 0.32% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 1769993 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.917046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.949504 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.477186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1374954 77.68% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271630 15.35% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53313 3.01% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21496 1.21% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12783 0.72% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6453 0.36% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4820 0.27% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3869 0.22% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20675 1.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1769993 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60112 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.611592 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 146.109791 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59940 99.71% 99.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 128 0.21% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 7 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 6 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 4 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60112 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.038778 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.996488 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.239516 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31933 53.12% 53.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1463 2.43% 55.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20988 34.91% 90.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4635 7.71% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 815 1.36% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 185 0.31% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 40 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::34 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59878 # Writes before turning the bus around for reads -system.physmem.totQLat 40967898000 # Total ticks spent queuing -system.physmem.totMemAccLat 77866023000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9839500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20818.08 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60112 # Writes before turning the bus around for reads +system.physmem.totQLat 40612494250 # Total ticks spent queuing +system.physmem.totMemAccLat 77369525500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9801875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20716.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39568.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 187.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 97.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 187.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 97.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39466.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 186.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 186.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.22 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing -system.physmem.readRowHits 794560 # Number of row buffer hits during reads -system.physmem.writeRowHits 415972 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes -system.physmem.avgGap 225087.32 # Average gap between requests -system.physmem.pageHitRate 40.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6515684280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3555184875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7409165400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3239410320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 305964835695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 135337912500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 505971439710 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.948773 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 223158478000 # Time in different power states -system.physmem_0.memoryStateTime::REF 22468940000 # Time in different power states +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 792670 # Number of row buffer hits during reads +system.physmem.writeRowHits 421939 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.19 # Row buffer hit rate for writes +system.physmem.avgGap 224970.87 # Average gap between requests +system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6484688280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3538272375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7379814000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3249285840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43875505440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305078205825 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 135438254250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 505044026010 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.831975 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 223329404750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22431240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 427253308500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 425992710250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6922850760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3777349125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7940244000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3371641200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 312976099035 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129187681500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 508125112260 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.149450 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 212887456750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22468940000 # Time in different power states +system.physmem_1.actEnergy 6896405880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3762919875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7910526000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3387653280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43875505440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 312108901605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129270987000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 507212899080 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.060642 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 213031369750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22431240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 437523815750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 436288612000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 410709882 # Number of BP lookups -system.cpu.branchPred.condPredicted 318998342 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16277823 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282986544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279468528 # Number of BTB hits +system.cpu.branchPred.lookups 410738673 # Number of BP lookups +system.cpu.branchPred.condPredicted 319032195 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16276977 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282876736 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279471264 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.756826 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26379180 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.796129 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26377862 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646309229 # DTB read hits -system.cpu.dtb.read_misses 12154225 # DTB read misses +system.cpu.dtb.read_hits 646528255 # DTB read hits +system.cpu.dtb.read_misses 12150594 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658463454 # DTB read accesses -system.cpu.dtb.write_hits 218201258 # DTB write hits -system.cpu.dtb.write_misses 7510092 # DTB write misses +system.cpu.dtb.read_accesses 658678849 # DTB read accesses +system.cpu.dtb.write_hits 218209856 # DTB write hits +system.cpu.dtb.write_misses 7511426 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225711350 # DTB write accesses -system.cpu.dtb.data_hits 864510487 # DTB hits -system.cpu.dtb.data_misses 19664317 # DTB misses +system.cpu.dtb.write_accesses 225721282 # DTB write accesses +system.cpu.dtb.data_hits 864738111 # DTB hits +system.cpu.dtb.data_misses 19662020 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884174804 # DTB accesses -system.cpu.itb.fetch_hits 422619736 # ITB hits -system.cpu.itb.fetch_misses 46 # ITB misses +system.cpu.dtb.data_accesses 884400131 # DTB accesses +system.cpu.itb.fetch_hits 422614397 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422619782 # ITB accesses +system.cpu.itb.fetch_accesses 422614441 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -343,139 +350,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1345763040 # number of cpu cycles simulated +system.cpu.numCycles 1343509607 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433914332 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3420599858 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410709882 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305847708 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 888768265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 46015780 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 433913722 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3420789895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410738673 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305849126 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 886512749 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 46016020 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422619736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8427195 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1345692377 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.541888 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.149351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1692 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422614397 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8419525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1343436257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.546299 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150257 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 718495980 53.39% 53.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48031633 3.57% 56.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24393578 1.81% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45267643 3.36% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 143041045 10.63% 72.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66223895 4.92% 77.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43793513 3.25% 80.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29627313 2.20% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226817777 16.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 716181443 53.31% 53.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48040729 3.58% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24412482 1.82% 58.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45272149 3.37% 62.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 143062816 10.65% 72.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66221905 4.93% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43789018 3.26% 80.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29632862 2.21% 83.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226822853 16.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1345692377 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305187 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.541755 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355603714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 406294583 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525817435 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34969591 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23007054 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62310888 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 895 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264812656 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2282 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23007054 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373973816 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212778142 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7997 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538797541 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 197127827 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181847820 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1862600 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20249864 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 150635497 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31416943 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377870821 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4127617004 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4127447466 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169537 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1343436257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305721 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.546160 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355607674 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 404003493 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525762782 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 35055109 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23007199 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62310513 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 875 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3265200378 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2135 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23007199 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373983702 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 211600441 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6939 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538809166 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 196028810 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3182220984 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1833786 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20271739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 149993150 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30859152 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2378179455 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4128151916 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4127979405 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 172510 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001667858 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 209 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99280769 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719325488 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272942348 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90808423 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 59047660 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2890368727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1154325126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1345692377 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.950220 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.146970 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001976492 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 195 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 195 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99605318 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719399499 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272964536 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90785513 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58783416 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2890757443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 174 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624793649 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1589988 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1154713835 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 506306579 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 145 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1343436257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953791 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.147325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 540762104 40.18% 40.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169795677 12.62% 52.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158437148 11.77% 64.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149383051 11.10% 75.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126329288 9.39% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84501883 6.28% 91.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68040537 5.06% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34033784 2.53% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14408905 1.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 538259461 40.07% 40.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 170012804 12.66% 52.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158478310 11.80% 64.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149374624 11.12% 75.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126330762 9.40% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84386661 6.28% 91.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68107665 5.07% 96.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34089750 2.54% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14396220 1.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1345692377 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1343436257 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13165371 35.79% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19036657 51.75% 87.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4585623 12.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13176390 35.76% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19068779 51.75% 87.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4600766 12.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719509054 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719677353 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896832 0.03% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 25 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 897887 0.03% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 22 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued @@ -497,84 +504,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 673114194 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230876222 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 673327193 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230890880 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624396643 # Type of FU issued -system.cpu.iq.rate 1.950118 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4043543263 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1297099 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69569005 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624793649 # Type of FU issued +system.cpu.iq.rate 1.953684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36845935 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014038 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6629473751 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4044314699 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2522399915 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1985727 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1304235 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 894550 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2660653801 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 985783 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69567792 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274729825 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379855 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 148630 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112213846 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274803836 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379517 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 149864 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112236034 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 321 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6130129 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 312 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6300661 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23007054 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 150994559 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20053347 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3041642230 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6687101 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719325488 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272942348 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 819254 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19491023 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 148630 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10888571 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8843177 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19731748 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578706854 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658463458 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45689789 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23007199 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150535686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19606000 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3042042837 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6687461 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719399499 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272964536 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 174 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 810054 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19058140 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 149864 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10895731 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8841524 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19737255 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2579092054 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658678856 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45701595 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151273322 # number of nop insts executed -system.cpu.iew.exec_refs 884174883 # number of memory reference insts executed -system.cpu.iew.exec_branches 315972780 # Number of branches executed -system.cpu.iew.exec_stores 225711425 # Number of stores executed -system.cpu.iew.exec_rate 1.916167 # Inst execution rate -system.cpu.iew.wb_sent 2553063246 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2523069590 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489308587 # num instructions producing a value -system.cpu.iew.wb_consumers 1920703402 # num instructions consuming a value +system.cpu.iew.exec_nop 151285220 # number of nop insts executed +system.cpu.iew.exec_refs 884400225 # number of memory reference insts executed +system.cpu.iew.exec_branches 315980786 # Number of branches executed +system.cpu.iew.exec_stores 225721369 # Number of stores executed +system.cpu.iew.exec_rate 1.919668 # Inst execution rate +system.cpu.iew.wb_sent 2553280591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2523294465 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489396348 # num instructions producing a value +system.cpu.iew.wb_consumers 1920808747 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874825 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775397 # average fanout of values written-back +system.cpu.iew.wb_rate 1.878137 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775401 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005912526 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1006176660 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16276987 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1206693157 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.508072 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.543192 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16276166 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1204408845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.510932 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.544476 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 717446911 59.46% 59.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159887401 13.25% 72.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79830197 6.62% 79.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52027392 4.31% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28503242 2.36% 85.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19553290 1.62% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20023421 1.66% 89.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23140213 1.92% 91.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106281090 8.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 715098033 59.37% 59.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159881136 13.27% 72.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79829015 6.63% 79.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52096588 4.33% 83.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28578407 2.37% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19544658 1.62% 87.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20010855 1.66% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23112076 1.92% 91.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106258077 8.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1206693157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1204408845 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -620,340 +627,344 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3840325519 # The number of ROB reads -system.cpu.rob.rob_writes 5790523687 # The number of ROB writes -system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 70663 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 106258077 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3838328354 # The number of ROB reads +system.cpu.rob.rob_writes 5791077348 # The number of ROB writes +system.cpu.timesIdled 692 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 73350 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.775190 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.775190 # CPI: Total CPI of All Threads -system.cpu.ipc 1.290007 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.290007 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3468053564 # number of integer regfile reads -system.cpu.int_regfile_writes 2022530151 # number of integer regfile writes -system.cpu.fp_regfile_reads 45442 # number of floating regfile reads -system.cpu.fp_regfile_writes 563 # number of floating regfile writes +system.cpu.cpi 0.773892 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.773892 # CPI: Total CPI of All Threads +system.cpu.ipc 1.292171 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.292171 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3468538615 # number of integer regfile reads +system.cpu.int_regfile_writes 2022734233 # number of integer regfile writes +system.cpu.fp_regfile_reads 46009 # number of floating regfile reads +system.cpu.fp_regfile_writes 540 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9208756 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.479772 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713775439 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9212852 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.476056 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5132407000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.479772 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997920 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997920 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9208722 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.471997 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713777147 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9212818 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.476527 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5130746500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.471997 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997918 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997918 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 697 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 709 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2958 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472909430 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472909430 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558274718 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558274718 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155500717 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155500717 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713775435 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713775435 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713775435 # number of overall hits -system.cpu.dcache.overall_hits::total 713775435 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12845064 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12845064 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5227785 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5227785 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1473023486 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1473023486 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558278644 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558278644 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155498498 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155498498 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713777142 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713777142 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713777142 # number of overall hits +system.cpu.dcache.overall_hits::total 713777142 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12898182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12898182 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230004 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230004 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18072849 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18072849 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18072849 # number of overall misses -system.cpu.dcache.overall_misses::total 18072849 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 414536288750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 414536288750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 316664843212 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 316664843212 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 18128186 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18128186 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18128186 # number of overall misses +system.cpu.dcache.overall_misses::total 18128186 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 411532558500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 411532558500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 315240579886 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 315240579886 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 731201131962 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 731201131962 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 731201131962 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 731201131962 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571119782 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571119782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 726773138386 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 726773138386 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 726773138386 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 726773138386 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571176826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571176826 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731848284 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731848284 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731848284 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731848284 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022491 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022491 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032526 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032526 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024695 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024695 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024695 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024695 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32272.029844 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32272.029844 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60573.425114 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60573.425114 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731905328 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731905328 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731905328 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731905328 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022582 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022582 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032539 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032539 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31906.245275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31906.245275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60275.399385 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60275.399385 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40458.542644 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40458.542644 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15275634 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9588635 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1068737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67992 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.293165 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 141.025930 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40090.781195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40090.781195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40090.781195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40090.781195 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15662934 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9568706 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1102908 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67982 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.201487 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 140.753523 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742849 # number of writebacks -system.cpu.dcache.writebacks::total 3742849 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5511228 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5511228 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3348770 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3348770 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8859998 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8859998 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8859998 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8859998 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333836 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333836 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879015 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879015 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3728522 # number of writebacks +system.cpu.dcache.writebacks::total 3728522 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5564399 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5564399 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3350970 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3350970 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8915369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8915369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8915369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8915369 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333783 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333783 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879034 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9212851 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9212851 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9212851 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9212851 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180521790750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 180521790750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83364623703 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83364623703 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263886414453 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 263886414453 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263886414453 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 263886414453 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012841 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9212817 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9212817 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9212817 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9212817 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183008143000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183008143000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84351384400 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84351384400 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267359527400 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 267359527400 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267359527400 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 267359527400 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012840 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012840 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012588 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012588 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24614.920589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24614.920589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.129969 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.129969 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012587 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012587 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012587 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012587 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.125722 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.125722 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44890.823902 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44890.823902 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29020.388378 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29020.388378 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29020.388378 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29020.388378 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 773.497223 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422618194 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 774.831914 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422612882 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 975 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 433454.557949 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 433449.109744 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 773.497223 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377684 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377684 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 774.831914 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.378336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.378336 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 974 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 909 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.475586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 845240447 # Number of tag accesses -system.cpu.icache.tags.data_accesses 845240447 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422618194 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422618194 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422618194 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422618194 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422618194 # number of overall hits -system.cpu.icache.overall_hits::total 422618194 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1542 # number of overall misses -system.cpu.icache.overall_misses::total 1542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 116278500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 116278500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 116278500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 116278500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 116278500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 116278500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422619736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422619736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422619736 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422619736 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422619736 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422619736 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 845229769 # Number of tag accesses +system.cpu.icache.tags.data_accesses 845229769 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422612882 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422612882 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422612882 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422612882 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422612882 # number of overall hits +system.cpu.icache.overall_hits::total 422612882 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1515 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1515 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1515 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1515 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1515 # number of overall misses +system.cpu.icache.overall_misses::total 1515 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 116523500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 116523500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 116523500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 116523500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 116523500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 116523500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422614397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422614397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422614397 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422614397 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422614397 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422614397 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75407.587549 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75407.587549 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75407.587549 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75407.587549 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 435 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76913.201320 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76913.201320 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76913.201320 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76913.201320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76913.201320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76913.201320 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 961 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 120.125000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 567 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 567 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 567 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 567 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 567 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 567 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 540 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 540 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 540 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 540 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 975 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 975 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79199000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 79199000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79199000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 79199000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79199000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 79199000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 82864500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 82864500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 82864500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 82864500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 82864500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 82864500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81229.743590 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81229.743590 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84989.230769 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84989.230769 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84989.230769 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84989.230769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84989.230769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84989.230769 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1936457 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31413.219008 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9110872 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1966244 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.633643 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28158140750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14523.555801 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.886283 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16862.776924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.443224 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.514611 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958655 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29787 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71646500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156278918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156350565000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71646500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156278918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156350565000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162055 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.213719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.212910 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.213719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67722.564103 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77417.461932 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77409.570689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77261.583374 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77261.583374 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.212910 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79804.456260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79804.456260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73483.589744 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73483.589744 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79639.208580 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79639.208580 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73483.589744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79704.293647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79701.201860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73483.589744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79704.293647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79701.201860 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7334797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7334797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879030 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1950 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22170503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 7334745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4752776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6384952 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 975 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333770 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27634358 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27636309 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829164864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829227264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12956676 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828245760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 828308160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1929005 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20351521 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.094784 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.292917 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12956676 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18422516 90.52% 90.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1929005 9.48% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12956676 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221187000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20351521 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12939780000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1462500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14136511250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13819227000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1197850 # Transaction distribution -system.membus.trans_dist::ReadResp 1197850 # Transaction distribution -system.membus.trans_dist::Writeback 1020253 # Transaction distribution -system.membus.trans_dist::ReadExReq 771321 # Transaction distribution -system.membus.trans_dist::ReadExResp 771321 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958595 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4958595 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191323136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191323136 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1189447 # Transaction distribution +system.membus.trans_dist::Writeback 1024254 # Transaction distribution +system.membus.trans_dist::CleanEvict 903687 # Transaction distribution +system.membus.trans_dist::ReadExReq 772262 # Transaction distribution +system.membus.trans_dist::ReadExResp 772262 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189447 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851359 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5851359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191101632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191101632 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989424 # Request fanout histogram +system.membus.snoop_fanout::samples 3889650 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989424 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3889650 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989424 # Request fanout histogram -system.membus.reqLayer0.occupancy 7771933000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 10726595500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3889650 # Request fanout histogram +system.membus.reqLayer0.occupancy 8475841500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 10684260000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 6346aa78f..018ebe8b0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.623365 # Number of seconds simulated -sim_ticks 2623365440500 # Number of ticks simulated -final_tick 2623365440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.623057 # Number of seconds simulated +sim_ticks 2623057163500 # Number of ticks simulated +final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1411989 # Simulator instruction rate (inst/s) -host_op_rate 1411989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2035500124 # Simulator tick rate (ticks/s) -host_mem_usage 294160 # Number of bytes of host memory used -host_seconds 1288.81 # Real time elapsed on the host +host_inst_rate 1251674 # Simulator instruction rate (inst/s) +host_op_rate 1251674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1804181213 # Simulator tick rate (ticks/s) +host_mem_usage 294596 # Number of bytes of host memory used +host_seconds 1453.88 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory -system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory +system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65156928 # Number of bytes written to this memory -system.physmem.bytes_written::total 65156928 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory +system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958861 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959663 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47788654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47808220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24837153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24837153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24837153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47788654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72645373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47613206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47632774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19568 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19568 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24934862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24934862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24934862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47613206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72567635 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5246730881 # number of cpu cycles simulated +system.cpu.numCycles 5246114327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246730881 # Number of busy cycles +system.cpu.num_busy_cycles 5246114327 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -129,14 +129,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.262739 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4079.260769 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40977437000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262739 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 40977438500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.260769 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995913 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id @@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143355355000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143355355000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57375808000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57375808000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200731163000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200731163000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200731163000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200731163000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143001525000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57421337000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57421337000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200422862000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200422862000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200422862000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200422862000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19848.675941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19848.675941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30368.496602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30368.496602 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22029.963013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22029.963013 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21996.127411 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21996.127411 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks -system.cpu.dcache.writebacks::total 3693497 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks +system.cpu.dcache.writebacks::total 3679426 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132521734000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 132521734000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54541828000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 54541828000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187063562000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 187063562000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187063562000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187063562000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55532017000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 55532017000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191311128000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191311128000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -228,24 +228,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18348.675941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18348.675941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28868.496602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28868.496602 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.458786 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.447387 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.458786 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 612.447387 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299047 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299047 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44139500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44139500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44139500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44139500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44139500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44139500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44163500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44163500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44163500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44163500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44163500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44163500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55036.783042 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55036.783042 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55036.783042 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55036.783042 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55066.708229 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55066.708229 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,114 +302,119 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42936500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42936500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42936500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42936500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42936500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42936500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43361500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43361500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43361500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43361500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43361500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43361500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.783042 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53536.783042 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54066.708229 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54066.708229 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1926937 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30535.253333 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218167126000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15221.864156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064589 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.324589 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.464534 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1919524 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30534.757407 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1949316 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.377078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218167130000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15101.273798 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.972607 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15394.511002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.460854 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001189 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.469803 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.931847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27300 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106294313 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693497 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108019 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108019 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152873 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152873 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152873 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152873 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1177560 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1178362 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 781301 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 781301 # number of ReadExReq misses +system.cpu.l2cache.tags.tag_accesses 149600036 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149600036 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 3679426 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3679426 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6053359 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7160294 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7160294 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7160294 # number of overall hits +system.cpu.l2cache.overall_hits::total 7160294 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 782385 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782385 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1169055 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1169055 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1958861 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102460440000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102502590500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 3679426 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3679426 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414109 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161865 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161865 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214982 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.215051 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214237 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52536.783042 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52505.479976 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52505.501281 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007679 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007679 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52503.311028 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52503.311028 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.008947 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.008947 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52556.733167 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52556.733167 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52508.411067 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52508.411067 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52505.063665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52505.063665 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,105 +423,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018077 # number of writebacks -system.cpu.l2cache.writebacks::total 1018077 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177560 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178362 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781301 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 781301 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks +system.cpu.l2cache.writebacks::total 1021962 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1169055 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1169055 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958861 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951440 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1952242 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32510000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47697633000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47730143000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642696500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642696500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32510000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79340329500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 79372839500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32510000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79340329500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 79372839500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413536 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413536 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33251369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33251369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34130500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34130500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49694670500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49694670500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82946040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82980170500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82946040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82980170500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414109 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161865 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40536.159601 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40505.479976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40505.500856 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007679 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007679 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.008947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.008947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42556.733167 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42556.733167 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42508.411067 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42508.411067 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12806033 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919524 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.095310 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.293643 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12806033 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18220175 90.47% 90.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1919524 9.53% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12806033 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1178362 # Transaction distribution -system.membus.trans_dist::ReadResp 1178362 # Transaction distribution -system.membus.trans_dist::Writeback 1018077 # Transaction distribution -system.membus.trans_dist::ReadExReq 781301 # Transaction distribution -system.membus.trans_dist::ReadExResp 781301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1169857 # Transaction distribution +system.membus.trans_dist::Writeback 1021962 # Transaction distribution +system.membus.trans_dist::CleanEvict 896683 # Transaction distribution +system.membus.trans_dist::ReadExReq 782385 # Transaction distribution +system.membus.trans_dist::ReadExResp 782385 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2977740 # Request fanout histogram +system.membus.snoop_fanout::samples 3872712 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3872712 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2977740 # Request fanout histogram -system.membus.reqLayer0.occupancy 7156873500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3872712 # Request fanout histogram +system.membus.reqLayer0.occupancy 7960873524 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9798315500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9761522024 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index fd798006f..27ca4a2ca 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.119236 # Number of seconds simulated -sim_ticks 1119236001500 # Number of ticks simulated -final_tick 1119236001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.117365 # Number of seconds simulated +sim_ticks 1117365374500 # Number of ticks simulated +final_tick 1117365374500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240571 # Simulator instruction rate (inst/s) -host_op_rate 259178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174324523 # Simulator tick rate (ticks/s) -host_mem_usage 314620 # Number of bytes of host memory used -host_seconds 6420.42 # Real time elapsed on the host +host_inst_rate 236504 # Simulator instruction rate (inst/s) +host_op_rate 254797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171091237 # Simulator tick rate (ticks/s) +host_mem_usage 314716 # Number of bytes of host memory used +host_seconds 6530.82 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 131457472 # Number of bytes read from this memory -system.physmem.bytes_read::total 131507904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66959680 # Number of bytes written to this memory -system.physmem.bytes_written::total 66959680 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2054023 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2054811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046245 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046245 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117452862 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117497922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 59826239 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59826239 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59826239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117452862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177324160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2054811 # Number of read requests accepted -system.physmem.writeReqs 1046245 # Number of write requests accepted -system.physmem.readBursts 2054811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046245 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131422592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 85312 # Total number of bytes read from write queue -system.physmem.bytesWritten 66958080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131507904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66959680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1333 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130973248 # Number of bytes read from this memory +system.physmem.bytes_read::total 131024000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67225152 # Number of bytes written to this memory +system.physmem.bytes_written::total 67225152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2046457 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2047250 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050393 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050393 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45421 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117216133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117261554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45421 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45421 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60163984 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60163984 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60163984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117216133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177425537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2047250 # Number of read requests accepted +system.physmem.writeReqs 1050393 # Number of write requests accepted +system.physmem.readBursts 2047250 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1050393 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 130939136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue +system.physmem.bytesWritten 67223488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131024000 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67225152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127863 # Per bank write bursts -system.physmem.perBankRdBursts::1 125217 # Per bank write bursts -system.physmem.perBankRdBursts::2 122173 # Per bank write bursts -system.physmem.perBankRdBursts::3 124176 # Per bank write bursts -system.physmem.perBankRdBursts::4 123271 # Per bank write bursts -system.physmem.perBankRdBursts::5 123280 # Per bank write bursts -system.physmem.perBankRdBursts::6 123668 # Per bank write bursts -system.physmem.perBankRdBursts::7 124134 # Per bank write bursts -system.physmem.perBankRdBursts::8 131770 # Per bank write bursts -system.physmem.perBankRdBursts::9 134069 # Per bank write bursts -system.physmem.perBankRdBursts::10 132400 # Per bank write bursts -system.physmem.perBankRdBursts::11 133571 # Per bank write bursts -system.physmem.perBankRdBursts::12 133882 # Per bank write bursts -system.physmem.perBankRdBursts::13 133894 # Per bank write bursts -system.physmem.perBankRdBursts::14 129882 # Per bank write bursts -system.physmem.perBankRdBursts::15 130228 # Per bank write bursts -system.physmem.perBankWrBursts::0 65769 # Per bank write bursts -system.physmem.perBankWrBursts::1 64155 # Per bank write bursts -system.physmem.perBankWrBursts::2 62373 # Per bank write bursts -system.physmem.perBankWrBursts::3 62858 # Per bank write bursts -system.physmem.perBankWrBursts::4 62829 # Per bank write bursts -system.physmem.perBankWrBursts::5 62965 # Per bank write bursts -system.physmem.perBankWrBursts::6 64230 # Per bank write bursts -system.physmem.perBankWrBursts::7 65234 # Per bank write bursts -system.physmem.perBankWrBursts::8 67002 # Per bank write bursts -system.physmem.perBankWrBursts::9 67576 # Per bank write bursts -system.physmem.perBankWrBursts::10 67286 # Per bank write bursts -system.physmem.perBankWrBursts::11 67640 # Per bank write bursts -system.physmem.perBankWrBursts::12 67022 # Per bank write bursts -system.physmem.perBankWrBursts::13 67467 # Per bank write bursts -system.physmem.perBankWrBursts::14 66208 # Per bank write bursts -system.physmem.perBankWrBursts::15 65606 # Per bank write bursts +system.physmem.perBankRdBursts::0 127156 # Per bank write bursts +system.physmem.perBankRdBursts::1 124552 # Per bank write bursts +system.physmem.perBankRdBursts::2 121687 # Per bank write bursts +system.physmem.perBankRdBursts::3 123679 # Per bank write bursts +system.physmem.perBankRdBursts::4 122821 # Per bank write bursts +system.physmem.perBankRdBursts::5 122785 # Per bank write bursts +system.physmem.perBankRdBursts::6 123231 # Per bank write bursts +system.physmem.perBankRdBursts::7 123758 # Per bank write bursts +system.physmem.perBankRdBursts::8 131446 # Per bank write bursts +system.physmem.perBankRdBursts::9 133531 # Per bank write bursts +system.physmem.perBankRdBursts::10 132174 # Per bank write bursts +system.physmem.perBankRdBursts::11 133285 # Per bank write bursts +system.physmem.perBankRdBursts::12 133312 # Per bank write bursts +system.physmem.perBankRdBursts::13 133367 # Per bank write bursts +system.physmem.perBankRdBursts::14 129415 # Per bank write bursts +system.physmem.perBankRdBursts::15 129725 # Per bank write bursts +system.physmem.perBankWrBursts::0 66071 # Per bank write bursts +system.physmem.perBankWrBursts::1 64336 # Per bank write bursts +system.physmem.perBankWrBursts::2 62582 # Per bank write bursts +system.physmem.perBankWrBursts::3 63010 # Per bank write bursts +system.physmem.perBankWrBursts::4 63074 # Per bank write bursts +system.physmem.perBankWrBursts::5 63174 # Per bank write bursts +system.physmem.perBankWrBursts::6 64441 # Per bank write bursts +system.physmem.perBankWrBursts::7 65447 # Per bank write bursts +system.physmem.perBankWrBursts::8 67324 # Per bank write bursts +system.physmem.perBankWrBursts::9 67820 # Per bank write bursts +system.physmem.perBankWrBursts::10 67591 # Per bank write bursts +system.physmem.perBankWrBursts::11 67884 # Per bank write bursts +system.physmem.perBankWrBursts::12 67359 # Per bank write bursts +system.physmem.perBankWrBursts::13 67795 # Per bank write bursts +system.physmem.perBankWrBursts::14 66531 # Per bank write bursts +system.physmem.perBankWrBursts::15 65928 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1119235907000 # Total gap between requests +system.physmem.totGap 1117365281000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2054811 # Read request sizes (log2) +system.physmem.readPktSize::6 2047250 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046245 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1925781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1050393 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1917221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,108 +193,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1918760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.389572 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.724365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 124.748032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1494097 77.87% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305195 15.91% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52958 2.76% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21140 1.10% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13031 0.68% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7420 0.39% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5500 0.29% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5087 0.27% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14332 0.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1918760 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60963 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.636353 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.963797 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60925 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1911200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.683951 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.443095 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1486351 77.77% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305207 15.97% 93.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52508 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21149 1.11% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13340 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7581 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5505 0.29% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5122 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14437 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1911200 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61162 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.403649 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.275472 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61115 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 22 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60963 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60963 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.161557 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.126473 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.099462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27343 44.85% 44.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1128 1.85% 46.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28298 46.42% 93.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3779 6.20% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 354 0.58% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61162 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61162 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.173523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.138356 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.100510 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27168 44.42% 44.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1036 1.69% 46.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28675 46.88% 93.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3829 6.26% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 390 0.64% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60963 # Writes before turning the bus around for reads -system.physmem.totQLat 38392697500 # Total ticks spent queuing -system.physmem.totMemAccLat 76895410000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10267390000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18696.43 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61162 # Writes before turning the bus around for reads +system.physmem.totQLat 38200049000 # Total ticks spent queuing +system.physmem.totMemAccLat 76561124000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10229620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18671.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37446.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 117.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 59.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 117.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37421.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.38 # Data bus utilization in percentage +system.physmem.busUtil 1.39 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing -system.physmem.readRowHits 774740 # Number of row buffer hits during reads -system.physmem.writeRowHits 406194 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.82 # Row buffer hit rate for writes -system.physmem.avgGap 360920.90 # Average gap between requests -system.physmem.pageHitRate 38.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7079751000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3862959375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7751413800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3307476240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 422173404720 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301213311750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 818491274085 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.295434 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498371051250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37373700000 # Time in different power states +system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing +system.physmem.readRowHits 773325 # Number of row buffer hits during reads +system.physmem.writeRowHits 411756 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.20 # Row buffer hit rate for writes +system.physmem.avgGap 360714.67 # Average gap between requests +system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7043954400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3843427500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7719106200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318634800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72980394240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 421878506670 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 300346094250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 817130118060 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.305386 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 496942671500 # Time in different power states +system.physmem_0.memoryStateTime::REF 37311040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583490028750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583108431500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7426074600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4051925625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8265605400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3472029360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 430406880300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293990964750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 820716437235 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.283545 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 486308465000 # Time in different power states -system.physmem_1.memoryStateTime::REF 37373700000 # Time in different power states +system.physmem_1.actEnergy 7404702480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4040264250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8238734400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3487743360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72980394240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 429447905460 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293706270750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 819306014940 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.252744 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485853174500 # Time in different power states +system.physmem_1.memoryStateTime::REF 37311040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 595553667000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 594197830000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239764270 # Number of BP lookups -system.cpu.branchPred.condPredicted 186476421 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14595676 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130796554 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122091083 # Number of BTB hits +system.cpu.branchPred.lookups 239770012 # Number of BP lookups +system.cpu.branchPred.condPredicted 186474623 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14592511 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 129773424 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122091028 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.344266 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15654091 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.080147 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15653619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -414,68 +412,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2238472003 # number of cpu cycles simulated +system.cpu.numCycles 2234730749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41626992 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41613452 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.449259 # CPI: cycles per instruction -system.cpu.ipc 0.690008 # IPC: instructions per cycle -system.cpu.tickCycles 1834950604 # Number of cycles that the object actually ticked -system.cpu.idleCycles 403521399 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9221835 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.627405 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624240644 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9225931 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.661534 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9809256250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.627405 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997468 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997468 # Average percentage of cache occupancy +system.cpu.cpi 1.446837 # CPI: cycles per instruction +system.cpu.ipc 0.691163 # IPC: instructions per cycle +system.cpu.tickCycles 1834912752 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399817997 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9221614 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.621118 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624237491 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9225710 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.662813 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.621118 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997466 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997466 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1227 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276887063 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276887063 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453909121 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453909121 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331400 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331400 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276880692 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276880692 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453906230 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453906230 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331138 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331138 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624240521 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624240521 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624240522 # number of overall hits -system.cpu.dcache.overall_hits::total 624240522 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7335273 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7335273 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254647 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624237368 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624237368 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624237369 # number of overall hits +system.cpu.dcache.overall_hits::total 624237369 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7335089 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7335089 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254909 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254909 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589920 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589920 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589922 # number of overall misses -system.cpu.dcache.overall_misses::total 9589922 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192354012246 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192354012246 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109627439500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109627439500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 301981451746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 301981451746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 301981451746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 301981451746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461244394 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461244394 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589998 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589998 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590000 # number of overall misses +system.cpu.dcache.overall_misses::total 9590000 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 191000565000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 191000565000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109144177000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109144177000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 300144742000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 300144742000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 300144742000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 300144742000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461241319 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461241319 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -484,28 +482,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633830441 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633830441 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633830444 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633830444 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633827366 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633827366 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633827369 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633827369 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015903 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015903 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013064 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013065 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013065 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26223.156554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26223.156554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48622.883981 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48622.883981 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31489.465162 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31489.465162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31489.458595 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31489.458595 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26039.297546 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26039.297546 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48402.918699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48402.918699 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31297.685568 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31297.685568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31297.679041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31297.679041 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,38 +512,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700642 # number of writebacks -system.cpu.dcache.writebacks::total 3700642 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363775 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 363775 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 363990 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 363990 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 363990 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 363990 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7335058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7335058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890872 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890872 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3684549 # number of writebacks +system.cpu.dcache.writebacks::total 3684549 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364078 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364078 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364289 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364289 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364289 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364289 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334878 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334878 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890831 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890831 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9225930 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9225930 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9225931 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9225931 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180934230004 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 180934230004 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83925664500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83925664500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264859894504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 264859894504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264859968254 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 264859968254 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015903 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9225709 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9225709 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9225710 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9225710 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183660145000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183660145000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84822237000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84822237000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268482382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268482382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268482456000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268482456000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses @@ -554,69 +552,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014556 system.cpu.dcache.demand_mshr_miss_rate::total 0.014556 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014556 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24667.048305 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24667.048305 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44384.635502 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44384.635502 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28708.205515 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28708.205515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28708.210397 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28708.210397 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25039.291042 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25039.291042 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44859.766420 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44859.766420 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29101.544608 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29101.544608 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29101.549474 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29101.549474 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 662.446494 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465464024 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 821 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 566947.654080 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 32 # number of replacements +system.cpu.icache.tags.tagsinuse 663.200919 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465452181 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 826 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 563501.429782 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 662.446494 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.323460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.323460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 663.200919 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.323829 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.323829 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 794 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 755 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.386719 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930930511 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930930511 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465464024 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465464024 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465464024 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465464024 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465464024 # number of overall hits -system.cpu.icache.overall_hits::total 465464024 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 821 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 821 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 821 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 821 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 821 # number of overall misses -system.cpu.icache.overall_misses::total 821 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63001249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63001249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63001249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63001249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63001249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63001249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465464845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465464845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465464845 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465464845 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465464845 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465464845 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 756 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.387695 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 930906840 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930906840 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465452181 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465452181 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465452181 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465452181 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465452181 # number of overall hits +system.cpu.icache.overall_hits::total 465452181 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 826 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 826 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 826 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 826 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 826 # number of overall misses +system.cpu.icache.overall_misses::total 826 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62820500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62820500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62820500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62820500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62820500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62820500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465453007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465453007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465453007 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465453007 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465453007 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465453007 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76737.209501 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76737.209501 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76737.209501 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76737.209501 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76737.209501 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76737.209501 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.874092 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76053.874092 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.874092 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76053.874092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.874092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76053.874092 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -625,123 +623,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 821 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 821 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 821 # 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average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87305.998336 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76093.198992 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87565.003926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87560.554743 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76093.198992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87565.003926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87560.554743 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -750,114 +754,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 788 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254070 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1254858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 799953 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 799953 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 788 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2054023 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2054811 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 788 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2054023 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2054811 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50399250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93887019000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 93937418250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60414024000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60414024000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50399250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154301043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 154351442250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50399250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154301043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 154351442250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.170969 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171058 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222701 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222701 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63958.439086 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74865.851986 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74859.002572 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75521.966916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75521.966916 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 246 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 246 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801299 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 801299 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 793 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 793 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1245158 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1245158 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2046457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2047250 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2046457 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2047250 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62475264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62475264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52472500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52472500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96258268000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96258268000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52472500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158733532000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158786004500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52472500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158733532000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158786004500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.960048 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169758 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169758 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221821 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.221887 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221821 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.221887 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77967.480304 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77967.480304 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66169.609079 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66169.609079 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77306.067182 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77306.067182 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66169.609079 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77565.046322 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77560.632312 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66169.609079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77565.046322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77560.632312 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7335880 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7335880 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890872 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1642 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22152504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22154146 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827300672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827353216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12927394 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7335705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4734942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6499660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334879 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1684 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671440 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27673124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826256576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 826309440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2014550 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20462732 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.098450 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.297922 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12927394 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18448182 90.16% 90.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2014550 9.84% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12927394 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10164339000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1397749 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20462732 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12908640000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1239499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14187903746 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1254858 # Transaction distribution -system.membus.trans_dist::ReadResp 1254858 # Transaction distribution -system.membus.trans_dist::Writeback 1046245 # Transaction distribution -system.membus.trans_dist::ReadExReq 799953 # Transaction distribution -system.membus.trans_dist::ReadExResp 799953 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5155867 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5155867 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198467584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198467584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 13838566996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1245951 # Transaction distribution +system.membus.trans_dist::Writeback 1050393 # Transaction distribution +system.membus.trans_dist::CleanEvict 963109 # Transaction distribution +system.membus.trans_dist::ReadExReq 801299 # Transaction distribution +system.membus.trans_dist::ReadExResp 801299 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1245951 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6108002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6108002 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198249152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198249152 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3101056 # Request fanout histogram +system.membus.snoop_fanout::samples 4060752 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3101056 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4060752 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3101056 # Request fanout histogram -system.membus.reqLayer0.occupancy 7929911000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 11237799750 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4060752 # Request fanout histogram +system.membus.reqLayer0.occupancy 8665729500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 11195509250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d2f403426..493c10cfc 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.771725 # Number of seconds simulated -sim_ticks 771725169000 # Number of ticks simulated -final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770277 # Number of seconds simulated +sim_ticks 770277033000 # Number of ticks simulated +final_tick 770277033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137392 # Simulator instruction rate (inst/s) -host_op_rate 148019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68646343 # Simulator tick rate (ticks/s) -host_mem_usage 311812 # Number of bytes of host memory used -host_seconds 11242.04 # Real time elapsed on the host +host_inst_rate 139677 # Simulator instruction rate (inst/s) +host_op_rate 150481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69657391 # Simulator tick rate (ticks/s) +host_mem_usage 313196 # Number of bytes of host memory used +host_seconds 11058.08 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238609216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63286144 # Number of bytes read from this memory -system.physmem.bytes_read::total 301961664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104822848 # Number of bytes written to this memory -system.physmem.bytes_written::total 104822848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3728269 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 988846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4718151 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1637857 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1637857 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309189366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82006065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 391281347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 135829246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 135829246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 135829246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309189366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82006065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 527110594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4718151 # Number of read requests accepted -system.physmem.writeReqs 1637857 # Number of write requests accepted -system.physmem.readBursts 4718151 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1637857 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301519872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 441792 # Total number of bytes read from write queue -system.physmem.bytesWritten 104820544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 301961664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104822848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6903 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 19 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238802560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63353600 # Number of bytes read from this memory +system.physmem.bytes_read::total 302222208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104930816 # Number of bytes written to this memory +system.physmem.bytes_written::total 104930816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3731290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 989900 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4722222 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1639544 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1639544 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310021654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82247811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 392355211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136224776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136224776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136224776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310021654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82247811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 528579987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4722222 # Number of read requests accepted +system.physmem.writeReqs 1639544 # Number of write requests accepted +system.physmem.readBursts 4722222 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1639544 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301770432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 451776 # Total number of bytes read from write queue +system.physmem.bytesWritten 104928448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302222208 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104930816 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7059 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296668 # Per bank write bursts -system.physmem.perBankRdBursts::1 294562 # Per bank write bursts -system.physmem.perBankRdBursts::2 288307 # Per bank write bursts -system.physmem.perBankRdBursts::3 292737 # Per bank write bursts -system.physmem.perBankRdBursts::4 290232 # Per bank write bursts -system.physmem.perBankRdBursts::5 289394 # Per bank write bursts -system.physmem.perBankRdBursts::6 285167 # Per bank write bursts -system.physmem.perBankRdBursts::7 280683 # Per bank write bursts -system.physmem.perBankRdBursts::8 297292 # Per bank write bursts -system.physmem.perBankRdBursts::9 302920 # Per bank write bursts -system.physmem.perBankRdBursts::10 295430 # Per bank write bursts -system.physmem.perBankRdBursts::11 301815 # Per bank write bursts -system.physmem.perBankRdBursts::12 303322 # Per bank write bursts -system.physmem.perBankRdBursts::13 302849 # Per bank write bursts -system.physmem.perBankRdBursts::14 297025 # Per bank write bursts -system.physmem.perBankRdBursts::15 292845 # Per bank write bursts -system.physmem.perBankWrBursts::0 103942 # Per bank write bursts -system.physmem.perBankWrBursts::1 102053 # Per bank write bursts -system.physmem.perBankWrBursts::2 99317 # Per bank write bursts -system.physmem.perBankWrBursts::3 99871 # Per bank write bursts -system.physmem.perBankWrBursts::4 99169 # Per bank write bursts -system.physmem.perBankWrBursts::5 98963 # Per bank write bursts -system.physmem.perBankWrBursts::6 102735 # Per bank write bursts -system.physmem.perBankWrBursts::7 104389 # Per bank write bursts -system.physmem.perBankWrBursts::8 105226 # Per bank write bursts -system.physmem.perBankWrBursts::9 104532 # Per bank write bursts -system.physmem.perBankWrBursts::10 102159 # Per bank write bursts -system.physmem.perBankWrBursts::11 102806 # Per bank write bursts -system.physmem.perBankWrBursts::12 103028 # Per bank write bursts -system.physmem.perBankWrBursts::13 102702 # Per bank write bursts -system.physmem.perBankWrBursts::14 104263 # Per bank write bursts -system.physmem.perBankWrBursts::15 102666 # Per bank write bursts +system.physmem.perBankRdBursts::0 297173 # Per bank write bursts +system.physmem.perBankRdBursts::1 295012 # Per bank write bursts +system.physmem.perBankRdBursts::2 289245 # Per bank write bursts +system.physmem.perBankRdBursts::3 293018 # Per bank write bursts +system.physmem.perBankRdBursts::4 289731 # Per bank write bursts +system.physmem.perBankRdBursts::5 289594 # Per bank write bursts +system.physmem.perBankRdBursts::6 284433 # Per bank write bursts +system.physmem.perBankRdBursts::7 281274 # Per bank write bursts +system.physmem.perBankRdBursts::8 297880 # Per bank write bursts +system.physmem.perBankRdBursts::9 304149 # Per bank write bursts +system.physmem.perBankRdBursts::10 295533 # Per bank write bursts +system.physmem.perBankRdBursts::11 302217 # Per bank write bursts +system.physmem.perBankRdBursts::12 302962 # Per bank write bursts +system.physmem.perBankRdBursts::13 302377 # Per bank write bursts +system.physmem.perBankRdBursts::14 297334 # Per bank write bursts +system.physmem.perBankRdBursts::15 293231 # Per bank write bursts +system.physmem.perBankWrBursts::0 104274 # Per bank write bursts +system.physmem.perBankWrBursts::1 102166 # Per bank write bursts +system.physmem.perBankWrBursts::2 99582 # Per bank write bursts +system.physmem.perBankWrBursts::3 100201 # Per bank write bursts +system.physmem.perBankWrBursts::4 99226 # Per bank write bursts +system.physmem.perBankWrBursts::5 98958 # Per bank write bursts +system.physmem.perBankWrBursts::6 102876 # Per bank write bursts +system.physmem.perBankWrBursts::7 104542 # Per bank write bursts +system.physmem.perBankWrBursts::8 105498 # Per bank write bursts +system.physmem.perBankWrBursts::9 104632 # Per bank write bursts +system.physmem.perBankWrBursts::10 102325 # Per bank write bursts +system.physmem.perBankWrBursts::11 102766 # Per bank write bursts +system.physmem.perBankWrBursts::12 102939 # Per bank write bursts +system.physmem.perBankWrBursts::13 102535 # Per bank write bursts +system.physmem.perBankWrBursts::14 104418 # Per bank write bursts +system.physmem.perBankWrBursts::15 102569 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 771725022000 # Total gap between requests +system.physmem.totGap 770276886500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4718151 # Read request sizes (log2) +system.physmem.readPktSize::6 4722222 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1637857 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2774626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1044189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 331696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 153773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 84990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1639544 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2779707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1048806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 150885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 83926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 38903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 195 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 113547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 106733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 103419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -197,122 +197,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4287400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.775232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.917076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.448471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3413764 79.62% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 675374 15.75% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96809 2.26% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35249 0.82% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22885 0.53% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12087 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7187 0.17% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5043 0.12% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19002 0.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4287400 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98767 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.700609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.313411 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.282358 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 94950 96.14% 96.14% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1367 1.38% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 428 0.43% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 356 0.36% 99.09% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 374 0.38% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 247 0.25% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 145 0.15% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 66 0.07% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 31 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 13 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 9 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4293402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.726038 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.887603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.441683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3419558 79.65% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 676188 15.75% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96097 2.24% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35320 0.82% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22691 0.53% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12222 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7184 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5103 0.12% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19039 0.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4293402 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98787 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.730481 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.341812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.609970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 94999 96.17% 96.17% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1343 1.36% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 771 0.78% 98.31% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 397 0.40% 98.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 383 0.39% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 367 0.37% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 255 0.26% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 139 0.14% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 71 0.07% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 36 0.04% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 14 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1920-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2688-2815 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2944-3071 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3199 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3200-3327 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98767 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98767 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.582674 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.549780 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.086524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73305 74.22% 74.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1806 1.83% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18343 18.57% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3630 3.68% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 937 0.95% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 387 0.39% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 162 0.16% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 107 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 60 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3968-4095 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98787 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98787 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.596384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.562558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.102794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 72931 73.83% 73.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1712 1.73% 75.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18497 18.72% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3886 3.93% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1013 1.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 377 0.38% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 169 0.17% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 93 0.09% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 49 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 46 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98767 # Writes before turning the bus around for reads -system.physmem.totQLat 132285118194 # Total ticks spent queuing -system.physmem.totMemAccLat 220621018194 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23556240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28078.57 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98787 # Writes before turning the bus around for reads +system.physmem.totQLat 131372718643 # Total ticks spent queuing +system.physmem.totMemAccLat 219782024893 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23575815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27861.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46828.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 390.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 135.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 391.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 135.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46611.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 391.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 392.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.11 # Data bus utilization in percentage -system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads +system.physmem.busUtil 4.12 # Data bus utilization in percentage +system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing -system.physmem.readRowHits 1709073 # Number of row buffer hits during reads -system.physmem.writeRowHits 352585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.28 # Row buffer hit rate for reads +system.physmem.readRowHits 1708262 # Number of row buffer hits during reads +system.physmem.writeRowHits 352995 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes -system.physmem.avgGap 121416.62 # Average gap between requests -system.physmem.pageHitRate 32.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16073195040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8770096500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18077007000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5251294800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 410674128390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102790850250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 612041479260 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.088667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 168453702129 # Time in different power states -system.physmem_0.memoryStateTime::REF 25769380000 # Time in different power states +system.physmem.avgGap 121079.10 # Average gap between requests +system.physmem.pageHitRate 32.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16098316920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8783803875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18090555600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5260230720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409970854125 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102538812000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 611052888360 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.296379 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168045428834 # Time in different power states +system.physmem_0.memoryStateTime::REF 25721020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 577496605871 # Time in different power states +system.physmem_0.memoryStateTime::ACT 576504578166 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16339027320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8915143875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18669222000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5361163200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 412008151545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101620654500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 613318269720 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.743144 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 166509885283 # Time in different power states -system.physmem_1.memoryStateTime::REF 25769380000 # Time in different power states +system.physmem_1.actEnergy 16359303240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8926207125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18686249400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5363152560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 411485095035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101210530500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612340852980 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.968472 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165832482361 # Time in different power states +system.physmem_1.memoryStateTime::REF 25721020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 579440435717 # Time in different power states +system.physmem_1.memoryStateTime::ACT 578718185889 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286277860 # Number of BP lookups -system.cpu.branchPred.condPredicted 223409255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14633591 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157407621 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150346120 # Number of BTB hits +system.cpu.branchPred.lookups 286281176 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407845 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631280 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158010784 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150352507 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.513876 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641206 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.153320 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641956 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -431,128 +430,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1543450339 # number of cpu cycles simulated +system.cpu.numCycles 1540554067 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13927699 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067517377 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286277860 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166987326 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1514795150 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29291799 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 907 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656942032 # Number of cache lines fetched +system.cpu.fetch.icacheStallCycles 13926810 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067510841 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286281176 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166994463 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1511903145 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287205 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 944 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656946227 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1543369835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.435149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229340 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 1540474684 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.437849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 460957271 29.87% 29.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465455811 30.16% 60.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101360614 6.57% 66.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515596139 33.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458056876 29.73% 29.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465435106 30.21% 59.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101413024 6.58% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515569678 33.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1543369835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185479 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.339543 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74619350 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 545977788 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 850086533 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58040967 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14645197 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42200501 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 754 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037190940 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52475133 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14645197 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139685845 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 464851768 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13523 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837895691 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86277811 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976364426 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26735694 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45105241 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125505 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1481556 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25500508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985835865 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128071192 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432849079 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1540474684 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185830 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.342057 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74648924 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 543079640 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849978540 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58124682 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642898 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203677 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 755 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037193143 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52473156 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642898 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139724503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462464867 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13004 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837848817 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 85780595 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976362381 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26752450 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45148759 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125663 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1475660 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 24911172 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985832580 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128057886 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432844380 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310936920 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 149 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 140 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111342876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542549398 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199301403 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26926926 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29153523 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947926711 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857446823 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13498178 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283894503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 646939215 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1543369835 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.203501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151095 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310933635 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 157 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111445716 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542550479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199301883 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26937332 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29252722 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947933921 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857470724 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13498979 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283901721 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647143115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1540474684 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150877 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 590630846 38.27% 38.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325771475 21.11% 59.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378267234 24.51% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219666416 14.23% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29027688 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 587582159 38.14% 38.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326005186 21.16% 59.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378227465 24.55% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219635075 14.26% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29018612 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6187 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1543369835 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540474684 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166059149 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1996 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191393147 47.24% 88.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47682914 11.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166090735 41.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2011 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191466761 47.26% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47541933 11.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138268714 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801071 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138243565 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801032 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -574,90 +573,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532058987 28.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186318001 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532113978 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312098 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857446823 # Type of FU issued -system.cpu.iq.rate 1.203438 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405137206 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5676898637 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231834122 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805736851 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 228 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 232 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262583902 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 127 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17817639 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857470724 # Type of FU issued +system.cpu.iq.rate 1.205716 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405101440 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218093 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674016313 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231848584 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805694743 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 238 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262572030 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17810782 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84243064 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66651 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24454358 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84244145 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13196 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24454838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4525889 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4805394 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4507141 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4884537 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14645197 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25323327 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1332663 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947926995 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642898 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25317454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1284847 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947934221 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542549398 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199301403 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 146 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158839 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1172731 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701738 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8706499 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16408237 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827783249 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516881888 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29663574 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542550479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199301883 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159143 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1124751 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13196 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700546 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8704736 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16405282 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827804607 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516933891 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29666117 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 76 # number of nop insts executed -system.cpu.iew.exec_refs 698636146 # number of memory reference insts executed -system.cpu.iew.exec_branches 229555717 # Number of branches executed -system.cpu.iew.exec_stores 181754258 # Number of stores executed -system.cpu.iew.exec_rate 1.184219 # Inst execution rate -system.cpu.iew.wb_sent 1808767141 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805736919 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169322951 # num instructions producing a value -system.cpu.iew.wb_consumers 1689713401 # num instructions consuming a value +system.cpu.iew.exec_nop 84 # number of nop insts executed +system.cpu.iew.exec_refs 698685293 # number of memory reference insts executed +system.cpu.iew.exec_branches 229544445 # Number of branches executed +system.cpu.iew.exec_stores 181751402 # Number of stores executed +system.cpu.iew.exec_rate 1.186459 # Inst execution rate +system.cpu.iew.wb_sent 1808724876 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805694813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169261823 # num instructions producing a value +system.cpu.iew.wb_consumers 1689660637 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.169935 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692024 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172107 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692010 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 258002520 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258006259 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14632889 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1503882923 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.106491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.024391 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1500991330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.108622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025694 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 923604765 61.41% 61.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250635322 16.67% 78.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110056363 7.32% 85.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55280526 3.68% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29292132 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34092515 2.27% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24716046 1.64% 94.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18126603 1.21% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58078651 3.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 920697347 61.34% 61.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250635150 16.70% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110066020 7.33% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55280178 3.68% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29318113 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34079049 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24716376 1.65% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18134019 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58065078 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1503882923 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1500991330 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -703,76 +702,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58078651 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3367838627 # The number of ROB reads -system.cpu.rob.rob_writes 3883562090 # The number of ROB writes -system.cpu.timesIdled 851 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80504 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58065078 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3364964346 # The number of ROB reads +system.cpu.rob.rob_writes 3883565961 # The number of ROB writes +system.cpu.timesIdled 839 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79383 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.999280 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.999280 # CPI: Total CPI of All Threads -system.cpu.ipc 1.000721 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.000721 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175739809 # number of integer regfile reads -system.cpu.int_regfile_writes 1261583749 # number of integer regfile writes -system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965641029 # number of cc regfile reads -system.cpu.cc_regfile_writes 551880821 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853491 # number of misc regfile reads +system.cpu.cpi 0.997404 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.997404 # CPI: Total CPI of All Threads +system.cpu.ipc 1.002602 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.002602 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175788919 # number of integer regfile reads +system.cpu.int_regfile_writes 1261560913 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965670330 # number of cc regfile reads +system.cpu.cc_regfile_writes 551865131 # number of cc regfile writes +system.cpu.misc_regfile_reads 675839076 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17005885 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964949 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638186886 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17006397 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.526284 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78340000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964949 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 17004565 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965160 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638055083 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17005077 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.521446 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77552500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965160 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335687679 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335687679 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469400845 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469400845 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168785923 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168785923 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335687503 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335687503 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469335942 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469335942 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168719023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168719023 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638186768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638186768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638186768 # number of overall hits -system.cpu.dcache.overall_hits::total 638186768 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17353625 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17353625 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3800124 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3800124 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638054965 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638054965 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638054965 # number of overall hits +system.cpu.dcache.overall_hits::total 638054965 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17419100 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17419100 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867024 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867024 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21153749 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21153749 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21153751 # number of overall misses -system.cpu.dcache.overall_misses::total 21153751 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 417050356298 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149886013526 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 566936369824 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 566936369824 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 566936369824 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 566936369824 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486754470 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486754470 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21286124 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21286124 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21286126 # number of overall misses +system.cpu.dcache.overall_misses::total 21286126 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 415512136500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 415512136500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149273741664 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149273741664 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 290000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 564785878164 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 564785878164 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 564785878164 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 564785878164 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486755042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486755042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -781,417 +780,434 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659340517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659340517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659340519 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659340519 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035652 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022019 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659341089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659341089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659341091 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659341091 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032083 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032083 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032083 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26800.751480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26800.748946 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20736521 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3309459 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 945396 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67047 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.934217 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49.360285 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032284 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032284 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032284 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032284 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23853.823475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23853.823475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38601.710686 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38601.710686 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26533.054029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26533.054029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26533.051536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26533.051536 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20783046 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3318451 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 945637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67068 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.977827 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.478902 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4830628 # number of writebacks -system.cpu.dcache.writebacks::total 4830628 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3084713 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3084713 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1062640 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1062640 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4838877 # number of writebacks +system.cpu.dcache.writebacks::total 4838877 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151642 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151642 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129406 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1129406 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4147353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4147353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4147353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4147353 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268912 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14268912 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737484 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737484 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14267458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737618 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737618 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17006396 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17006396 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17006397 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17006397 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 444043827535 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 444043895285 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17005076 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17005076 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17005077 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17005077 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335579712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335579712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116324734517 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116324734517 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451904447017 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451904447017 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451904515017 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451904515017 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23520.637839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23520.637839 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42491.222120 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42491.222120 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26574.679644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26574.679644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26574.682080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26574.682080 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 589 # number of replacements -system.cpu.icache.tags.tagsinuse 446.078018 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656940406 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 609972.521820 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 585 # number of replacements +system.cpu.icache.tags.tagsinuse 445.973645 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656944607 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 612250.332712 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.078018 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.871246 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.871246 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 445.973645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871042 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871042 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313885139 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313885139 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656940406 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656940406 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656940406 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656940406 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656940406 # number of overall hits -system.cpu.icache.overall_hits::total 656940406 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1625 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1625 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1625 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1625 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1625 # number of overall misses -system.cpu.icache.overall_misses::total 1625 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 105016775 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 105016775 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 105016775 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 105016775 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 105016775 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 105016775 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656942031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656942031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656942031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656942031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656942031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656942031 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313893525 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313893525 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656944607 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656944607 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656944607 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656944607 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656944607 # number of overall hits +system.cpu.icache.overall_hits::total 656944607 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1619 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1619 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1619 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1619 # number of overall misses +system.cpu.icache.overall_misses::total 1619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 105131986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 105131986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 105131986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 105131986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 105131986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 105131986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656946226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656946226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656946226 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656946226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656946226 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656946226 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64625.707692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64625.707692 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17596 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 547 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 191 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.125654 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 60.777778 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64936.371834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64936.371834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64936.371834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64936.371834 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17916 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 510 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.312500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 63.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 548 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 548 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 548 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 548 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76192959 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 76192959 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76192959 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 76192959 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76192959 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 76192959 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 546 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 546 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 546 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 546 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 546 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 546 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1073 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1073 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1073 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1073 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1073 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1073 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76698989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 76698989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76698989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76698989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76698989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76698989 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70745.551532 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71480.884436 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71480.884436 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71480.884436 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71480.884436 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71480.884436 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71480.884436 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 10938258 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11626730 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 430783 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 10956462 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11638997 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 427337 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # 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number of ReadExReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 38390 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 38390 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 42289 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 42289 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 42289 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 42289 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 100257 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 100257 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993873 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 993873 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981601 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 981601 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1032 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1032 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2748969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2748969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1032 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3730570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3731602 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1032 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3730570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4725475 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72684245482 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72684245482 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93518423498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93518423498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 69157500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 69157500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 219665951000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 219665951000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69157500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 313184374498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 313253531998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69157500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 313184374498 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72684245482 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385937777480 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.219238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358554 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358554 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.961789 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.192675 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.192675 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219427 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219380 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277614 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277869 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 73132.327251 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95271.320524 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95271.320524 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67013.081395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67013.081395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79908.486054 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79908.486054 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67013.081395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83950.810331 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83946.126087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67013.081395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83950.810331 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81671.742519 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 14269946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14269946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4830628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1298291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737528 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38843422 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38845576 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397569600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1298291 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 14268485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 6478421 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 15219349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1327311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737665 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737665 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267412 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2727 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50995885 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398013056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1398081728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6041496 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 40052798 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.150838 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.357891 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 34011302 84.92% 84.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 6041496 15.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1817030 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40052798 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21844528998 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1609500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 26101043977 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3736842 # Transaction distribution -system.membus.trans_dist::ReadResp 3736842 # Transaction distribution -system.membus.trans_dist::Writeback 1637857 # Transaction distribution -system.membus.trans_dist::ReadExReq 981309 # Transaction distribution -system.membus.trans_dist::ReadExResp 981309 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11074159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11074159 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406784512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 406784512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 25507619991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3740347 # Transaction distribution +system.membus.trans_dist::Writeback 1639544 # Transaction distribution +system.membus.trans_dist::CleanEvict 3065371 # Transaction distribution +system.membus.trans_dist::ReadExReq 981875 # Transaction distribution +system.membus.trans_dist::ReadExResp 981875 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3740347 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14149359 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14149359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407153024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 407153024 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6356008 # Request fanout histogram +system.membus.snoop_fanout::samples 9427137 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6356008 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9427137 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6356008 # Request fanout histogram -system.membus.reqLayer0.occupancy 14483850639 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 25655332661 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9427137 # Request fanout histogram +system.membus.reqLayer0.occupancy 17268043532 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 25679820043 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 144026919..939603453 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363663 # Number of seconds simulated -sim_ticks 2363662967500 # Number of ticks simulated -final_tick 2363662967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363367 # Number of seconds simulated +sim_ticks 2363367211500 # Number of ticks simulated +final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734295 # Simulator instruction rate (inst/s) -host_op_rate 791306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127938114 # Simulator tick rate (ticks/s) -host_mem_usage 305424 # Number of bytes of host memory used -host_seconds 2095.56 # Real time elapsed on the host +host_inst_rate 1091670 # Simulator instruction rate (inst/s) +host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1676685643 # Simulator tick rate (ticks/s) +host_mem_usage 312924 # Number of bytes of host memory used +host_seconds 1409.55 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory -system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124870144 # Number of bytes read from this memory +system.physmem.bytes_read::total 124909568 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory -system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory +system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1951096 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951712 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4727325935 # number of cpu cycles simulated +system.cpu.numCycles 4726734423 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4727325934.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733673 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164659000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733673 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,8 +302,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks -system.cpu.dcache.writebacks::total 3697418 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks +system.cpu.dcache.writebacks::total 3681379 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,117 +411,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33250000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33250000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33250000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33250000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951096 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951712 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214100 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214100 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919018 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12813292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1177898 # Transaction distribution -system.membus.trans_dist::ReadResp 1177898 # Transaction distribution -system.membus.trans_dist::Writeback 1017198 # Transaction distribution -system.membus.trans_dist::ReadExReq 780876 # Transaction distribution -system.membus.trans_dist::ReadExResp 780876 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1169580 # Transaction distribution +system.membus.trans_dist::Writeback 1021127 # Transaction distribution +system.membus.trans_dist::CleanEvict 897054 # Transaction distribution +system.membus.trans_dist::ReadExReq 782132 # Transaction distribution +system.membus.trans_dist::ReadExResp 782132 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5821605 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190261696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2975972 # Request fanout histogram +system.membus.snoop_fanout::samples 3870264 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870264 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870264 # Request fanout histogram +system.membus.reqLayer0.occupancy 7969342268 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9772290268 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index b101e64c0..6d8265542 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.882580 # Number of seconds simulated -sim_ticks 5882580398500 # Number of ticks simulated -final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.882285 # Number of seconds simulated +sim_ticks 5882284743500 # Number of ticks simulated +final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 739516 # Simulator instruction rate (inst/s) -host_op_rate 1152234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1446192754 # Simulator tick rate (ticks/s) -host_mem_usage 314252 # Number of bytes of host memory used -host_seconds 4067.63 # Real time elapsed on the host +host_inst_rate 724530 # Simulator instruction rate (inst/s) +host_op_rate 1128884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1416814365 # Simulator tick rate (ticks/s) +host_mem_usage 314268 # Number of bytes of host memory used +host_seconds 4151.77 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory -system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124876416 # Number of bytes read from this memory +system.physmem.bytes_read::total 124919616 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory -system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65426432 # Number of bytes written to this memory +system.physmem.bytes_written::total 65426432 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 1951194 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951869 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022288 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022288 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21312106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21229237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21236581 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 11122622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11122622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11122622 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32392098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21229237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32359203 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11765160797 # number of cpu cycles simulated +system.cpu.numCycles 11764569487 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 1677713084 # nu system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11765160796.998001 # Number of busy cycles +system.cpu.num_busy_cycles 11764569486.998001 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 248500691 # Number of branches fetched @@ -100,14 +100,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.587033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4084.586459 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58853917000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 58853917500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.586459 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997213 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997213 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id @@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328499000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143328499000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382147000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57382147000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200710646000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200710646000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200710646000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200710646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 142985038000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57429949000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57429949000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200414987000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200414987000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200414987000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200414987000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) @@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.759596 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.759596 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.703662 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.703662 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.431824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.431824 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21992.987022 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21992.987022 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks -system.cpu.dcache.writebacks::total 3697956 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3682721 # number of writebacks +system.cpu.dcache.writebacks::total 3682721 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132494224000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 132494224000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54547406500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 54547406500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187041630500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 187041630500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187041630500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187041630500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55540122000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 55540122000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191302310000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191302310000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18343.759596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18343.759596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28863.703662 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28863.703662 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 555.701425 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 555.701425 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271339 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271339 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37138500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37138500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37138500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37138500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37138500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37138500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37142500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37142500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37142500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37142500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37142500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37142500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55020 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55020 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55020 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55020 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55025.925926 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55025.925926 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -273,114 +273,119 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36126000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36126000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36126000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36126000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36126000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36126000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36467500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36467500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36467500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36467500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36467500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36467500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53520 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53520 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1926197 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31136.249311 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 340768621000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795346 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812949 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1919162 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31136.006197 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14382006 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1948945 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.379380 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 340768623000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.605704 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.465892 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000781 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.483522 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950196 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 996 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 997 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27921 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27920 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106336271 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106336271 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108532 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7154443 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7154443 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7154443 # number of overall hits -system.cpu.l2cache.overall_hits::total 7154443 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1176939 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1177614 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses +system.cpu.l2cache.tags.tag_accesses 149614316 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149614316 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 3682721 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3682721 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054089 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6054089 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102437723000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102473176500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 3682721 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3682721 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161814 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161814 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52520 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.009346 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.020805 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007680 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007680 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.015570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.015570 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,107 +394,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks -system.cpu.l2cache.writebacks::total 1018421 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1176939 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1177614 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1022288 # number of writebacks +system.cpu.l2cache.writebacks::total 1022288 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 218 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 218 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168761 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168761 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951869 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27350500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47666040500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47693391000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27350500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79308494000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 79335844500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27350500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79308494000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 79335844500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951194 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951869 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33253414500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33253414500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28703500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28703500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49672368500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49672368500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28703500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82925783000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82954486500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28703500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82925783000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82954486500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161814 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161814 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.009346 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.020380 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007680 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007680 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.095286 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.293609 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12811308 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18221943 90.47% 90.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1919162 9.53% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1177614 # Transaction distribution -system.membus.trans_dist::ReadResp 1177614 # Transaction distribution -system.membus.trans_dist::Writeback 1018421 # Transaction distribution -system.membus.trans_dist::ReadExReq 781295 # Transaction distribution -system.membus.trans_dist::ReadExResp 781295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1169436 # Transaction distribution +system.membus.trans_dist::Writeback 1022288 # Transaction distribution +system.membus.trans_dist::CleanEvict 896090 # Transaction distribution +system.membus.trans_dist::ReadExReq 782433 # Transaction distribution +system.membus.trans_dist::ReadExResp 782433 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169436 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5822116 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190346048 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2977330 # Request fanout histogram +system.membus.snoop_fanout::samples 3870262 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870262 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2977330 # Request fanout histogram -system.membus.reqLayer0.occupancy 7158077000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870262 # Request fanout histogram +system.membus.reqLayer0.occupancy 7959418124 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9794545500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9759348624 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 874972c77..f4338fb5a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052048 # Number of seconds simulated -sim_ticks 52048460500 # Number of ticks simulated -final_tick 52048460500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052057 # Number of seconds simulated +sim_ticks 52057006500 # Number of ticks simulated +final_tick 52057006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 350030 # Simulator instruction rate (inst/s) -host_op_rate 350030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 198236020 # Simulator tick rate (ticks/s) -host_mem_usage 300292 # Number of bytes of host memory used -host_seconds 262.56 # Real time elapsed on the host +host_inst_rate 338250 # Simulator instruction rate (inst/s) +host_op_rate 338250 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191596351 # Simulator tick rate (ticks/s) +host_mem_usage 300296 # Number of bytes of host memory used +host_seconds 271.70 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory -system.physmem.bytes_read::total 340352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 340480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3894217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2644920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6539137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3894217 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3894217 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3894217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2644920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6539137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5318 # Number of read requests accepted +system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3896037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2644486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6540522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3896037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3896037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3896037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2644486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6540522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5320 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340352 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340352 # Total read bytes from the system interface side +system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -49,11 +49,11 @@ system.physmem.perBankRdBursts::4 224 # Pe system.physmem.perBankRdBursts::5 238 # Per bank write bursts system.physmem.perBankRdBursts::6 222 # Per bank write bursts system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 251 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 255 # Per bank write bursts system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 409 # Per bank write bursts +system.physmem.perBankRdBursts::12 410 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts system.physmem.perBankRdBursts::14 500 # Per bank write bursts system.physmem.perBankRdBursts::15 448 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52048372000 # Total gap between requests +system.physmem.totGap 52056919000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5318 # Read request sizes (log2) +system.physmem.readPktSize::6 5320 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.672131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.149483 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.651264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 303 31.05% 31.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 210 21.52% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 100 10.25% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 9.43% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 7.27% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 4.00% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 3.07% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 1.95% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 112 11.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 976 # Bytes accessed per row activation -system.physmem.totQLat 32254250 # Total ticks spent queuing -system.physmem.totMemAccLat 131966750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6065.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.809866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.712248 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.458818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 301 30.94% 30.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 209 21.48% 52.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 98 10.07% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 92 9.46% 71.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 7.40% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 4.62% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.47% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 1.95% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 113 11.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 973 # Bytes accessed per row activation +system.physmem.totQLat 31528250 # Total ticks spent queuing +system.physmem.totMemAccLat 131278250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5926.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24815.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24676.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4336 # Number of row buffer hits during reads +system.physmem.readRowHits 4340 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9787207.97 # Average gap between requests -system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19851000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9785135.15 # Average gap between requests +system.physmem.pageHitRate 81.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3492720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1905750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1773582930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29670358500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34868440995 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.985765 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49355972750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1737840000 # Time in different power states +system.physmem_0.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1761174315 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29685915000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34872054585 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.954967 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49382007750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1738100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 949756000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 931384250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 21231600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1774901340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29669193750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34870438740 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.024328 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49353927250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1737840000 # Time in different power states +system.physmem_1.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1805818995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29646744750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34879431555 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.096868 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49317281000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1738100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 951967750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 996955000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11467285 # Number of BP lookups -system.cpu.branchPred.condPredicted 8228909 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 787075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6498554 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5367359 # Number of BTB hits +system.cpu.branchPred.lookups 11466165 # Number of BP lookups +system.cpu.branchPred.condPredicted 8229222 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 788767 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6698071 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5372970 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.593128 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1175694 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.216677 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1174312 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20428735 # DTB read hits -system.cpu.dtb.read_misses 47112 # DTB read misses +system.cpu.dtb.read_hits 20431374 # DTB read hits +system.cpu.dtb.read_misses 46957 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20475847 # DTB read accesses -system.cpu.dtb.write_hits 6580361 # DTB write hits -system.cpu.dtb.write_misses 271 # DTB write misses +system.cpu.dtb.read_accesses 20478331 # DTB read accesses +system.cpu.dtb.write_hits 6580300 # DTB write hits +system.cpu.dtb.write_misses 270 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580632 # DTB write accesses -system.cpu.dtb.data_hits 27009096 # DTB hits -system.cpu.dtb.data_misses 47383 # DTB misses +system.cpu.dtb.write_accesses 6580570 # DTB write accesses +system.cpu.dtb.data_hits 27011674 # DTB hits +system.cpu.dtb.data_misses 47227 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27056479 # DTB accesses -system.cpu.itb.fetch_hits 23055300 # ITB hits -system.cpu.itb.fetch_misses 88 # ITB misses +system.cpu.dtb.data_accesses 27058901 # DTB accesses +system.cpu.itb.fetch_hits 23067346 # ITB hits +system.cpu.itb.fetch_misses 89 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23055388 # ITB accesses +system.cpu.itb.fetch_accesses 23067435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104096921 # number of cpu cycles simulated +system.cpu.numCycles 104114013 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2232007 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2234090 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.132681 # CPI: cycles per instruction -system.cpu.ipc 0.882861 # IPC: instructions per cycle -system.cpu.tickCycles 102361178 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1735743 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.132867 # CPI: cycles per instruction +system.cpu.ipc 0.882716 # IPC: instructions per cycle +system.cpu.tickCycles 102384742 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1729271 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.464460 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26584631 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.483845 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26587292 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11921.359193 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11922.552466 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.464460 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353629 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353629 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.483845 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353634 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353634 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,56 +320,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53178348 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53178348 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20086436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20086436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26584631 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26584631 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26584631 # number of overall hits -system.cpu.dcache.overall_hits::total 26584631 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53183674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53183674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20089099 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20089099 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26587292 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26587292 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26587292 # number of overall hits +system.cpu.dcache.overall_hits::total 26587292 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 520 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3428 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3428 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3428 # number of overall misses -system.cpu.dcache.overall_misses::total 3428 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41644750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41644750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 214147250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 214147250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 255792000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 255792000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 255792000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 255792000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20086956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20086956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses +system.cpu.dcache.overall_misses::total 3430 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40189000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40189000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 213917000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 213917000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254106000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254106000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254106000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254106000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20089619 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20089619 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26588059 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26588059 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26588059 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26588059 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26590722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26590722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26590722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26590722 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80086.057692 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 80086.057692 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73640.732462 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73640.732462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74618.436406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74618.436406 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77286.538462 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77286.538462 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73510.996564 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73510.996564 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74083.381924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74083.381924 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1198 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1198 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1198 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1198 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38003250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38003250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129542250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129542250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 167545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167545500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 167545500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36729500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36729500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 130660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167390000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167390000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167390000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 167390000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,69 +412,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78357.216495 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78357.216495 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74236.246418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74236.246418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75730.927835 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.927835 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74877.077364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74877.077364 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13853 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.586076 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23039482 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15817 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1456.627806 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13848 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.495432 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23051532 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15813 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1457.758300 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.586076 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801067 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801067 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.495432 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 669 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46126417 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46126417 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23039482 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23039482 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23039482 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23039482 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23039482 # number of overall hits -system.cpu.icache.overall_hits::total 23039482 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15818 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15818 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15818 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15818 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23055300 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23055300 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23055300 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 950 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 46150505 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46150505 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23051532 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23051532 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85545.717593 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75474.090025 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74185.136707 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74185.136707 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74100.252605 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76466.759647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75057.446408 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74100.252605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76466.759647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75057.446408 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.294851 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74328.097731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74328.097731 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73928.526349 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73928.526349 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82035.879630 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82035.879630 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73928.526349 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75876.104138 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74715.977444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73928.526349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75876.104138 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74715.977444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -608,102 +614,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3167 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 432 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3599 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195052500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31544750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226597250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 106089750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 106089750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 332687000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195052500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137634500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 332687000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110580000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110580000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202589500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202589500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31119500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31119500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202589500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 141699500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 344289000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202589500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 141699500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 344289000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200405 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294675 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294851 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294675 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61589.043259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73020.254630 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62961.169769 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61715.968586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61715.968586 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294851 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64328.097731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64328.097731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63928.526349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63928.526349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72035.879630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72035.879630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 16302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 16302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16298 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 13898 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 36201 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15813 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45474 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1161600 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18154 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 32048 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18154 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32048 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18154 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9184000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 32048 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 16131000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24412500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23719500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3745500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3599 # Transaction distribution -system.membus.trans_dist::ReadResp 3599 # Transaction distribution +system.membus.trans_dist::ReadResp 3601 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10636 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10636 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340352 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5318 # Request fanout histogram +system.membus.snoop_fanout::samples 5320 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5318 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6399500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5320 # Request fanout histogram +system.membus.reqLayer0.occupancy 6410500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28155000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28166750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index f5ac38df0..2afb0af07 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022229 # Number of seconds simulated -sim_ticks 22228749500 # Number of ticks simulated -final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022173 # Number of seconds simulated +sim_ticks 22172615500 # Number of ticks simulated +final_tick 22172615500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192800 # Simulator instruction rate (inst/s) -host_op_rate 192800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50911418 # Simulator tick rate (ticks/s) -host_mem_usage 230228 # Number of bytes of host memory used -host_seconds 436.62 # Real time elapsed on the host +host_inst_rate 207826 # Simulator instruction rate (inst/s) +host_op_rate 207826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54740698 # Simulator tick rate (ticks/s) +host_mem_usage 301824 # Number of bytes of host memory used +host_seconds 405.05 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8818850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6233369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15052219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8818850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8818850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8818850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6233369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15052219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5228 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory +system.physmem.bytes_read::total 334656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196224 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5229 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8849836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6243377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15093213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8849836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8849836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8849836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6243377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15093213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5229 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334656 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -44,18 +44,18 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 472 # Per bank write bursts system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 525 # Per bank write bursts -system.physmem.perBankRdBursts::4 219 # Per bank write bursts +system.physmem.perBankRdBursts::3 526 # Per bank write bursts +system.physmem.perBankRdBursts::4 217 # Per bank write bursts system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::6 217 # Per bank write bursts system.physmem.perBankRdBursts::7 285 # Per bank write bursts -system.physmem.perBankRdBursts::8 238 # Per bank write bursts -system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::8 239 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 252 # Per bank write bursts +system.physmem.perBankRdBursts::11 253 # Per bank write bursts system.physmem.perBankRdBursts::12 398 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::14 493 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22228653000 # Total gap between requests +system.physmem.totGap 22172520500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5228 # Read request sizes (log2) +system.physmem.readPktSize::6 5229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 225.895164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.482180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 274 31.64% 31.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 174 20.09% 51.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 9.12% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 66 7.62% 68.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29 3.35% 71.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.27% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 4.16% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 45 5.20% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 126 14.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 39875750 # Total ticks spent queuing -system.physmem.totMemAccLat 137900750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7627.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.112399 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.773233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.004147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 257 29.78% 29.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 196 22.71% 52.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 76 8.81% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.60% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.29% 72.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 34 3.94% 76.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 3.36% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 50 5.79% 85.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 127 14.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 863 # Bytes accessed per row activation +system.physmem.totQLat 43111750 # Total ticks spent queuing +system.physmem.totMemAccLat 141155500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8244.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26377.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26994.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.09 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.05 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.09 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4353 # Number of row buffer hits during reads +system.physmem.readRowHits 4356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4251846.40 # Average gap between requests -system.physmem.pageHitRate 83.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19476600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4240298.43 # Average gap between requests +system.physmem.pageHitRate 83.30 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3160080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1724250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19492200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 894518100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12548665500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14918939715 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.352430 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20873521000 # Time in different power states -system.physmem_0.memoryStateTime::REF 742040000 # Time in different power states +system.physmem_0.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 926205255 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12488167500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14886619605 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.545103 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20772765250 # Time in different power states +system.physmem_0.memoryStateTime::REF 740220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 606815000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 654868750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3349080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1827375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20794800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20810400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 919030095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12527163750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14923595340 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.561933 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20841181500 # Time in different power states -system.physmem_1.memoryStateTime::REF 742040000 # Time in different power states +system.physmem_1.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 909735390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12502614750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14886148890 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.523868 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20796420250 # Time in different power states +system.physmem_1.memoryStateTime::REF 740220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 642887000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 631087250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16323961 # Number of BP lookups -system.cpu.branchPred.condPredicted 11865379 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 978310 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9045215 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7641567 # Number of BTB hits +system.cpu.branchPred.lookups 16296711 # Number of BP lookups +system.cpu.branchPred.condPredicted 11841199 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 977322 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9230824 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7630427 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 84.481872 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1608650 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 453 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.662469 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1605836 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 456 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24152698 # DTB read hits -system.cpu.dtb.read_misses 236585 # DTB read misses +system.cpu.dtb.read_hits 24148862 # DTB read hits +system.cpu.dtb.read_misses 238971 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24389283 # DTB read accesses -system.cpu.dtb.write_hits 7160578 # DTB write hits -system.cpu.dtb.write_misses 1214 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7161792 # DTB write accesses -system.cpu.dtb.data_hits 31313276 # DTB hits -system.cpu.dtb.data_misses 237799 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 31551075 # DTB accesses -system.cpu.itb.fetch_hits 16159751 # ITB hits -system.cpu.itb.fetch_misses 85 # ITB misses +system.cpu.dtb.read_accesses 24387833 # DTB read accesses +system.cpu.dtb.write_hits 7164238 # DTB write hits +system.cpu.dtb.write_misses 1251 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 7165489 # DTB write accesses +system.cpu.dtb.data_hits 31313100 # DTB hits +system.cpu.dtb.data_misses 240222 # DTB misses +system.cpu.dtb.data_acv 3 # DTB access violations +system.cpu.dtb.data_accesses 31553322 # DTB accesses +system.cpu.itb.fetch_hits 16134293 # ITB hits +system.cpu.itb.fetch_misses 87 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16159836 # ITB accesses +system.cpu.itb.fetch_accesses 16134380 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44457500 # number of cpu cycles simulated +system.cpu.numCycles 44345232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16896881 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139613933 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16323961 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9250217 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26293708 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2036816 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 16871286 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139358892 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16296711 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9236263 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26208155 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2034698 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 203 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2338 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16159751 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382144 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44211553 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.157861 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.431266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2379 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16134293 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382507 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44099332 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.160113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.432013 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19722112 44.61% 44.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2663068 6.02% 50.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1345508 3.04% 53.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1957580 4.43% 58.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3052640 6.90% 65.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1306785 2.96% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1385791 3.13% 71.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 896674 2.03% 73.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11881395 26.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19660436 44.58% 44.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2660444 6.03% 50.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1334517 3.03% 53.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1958294 4.44% 58.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3041312 6.90% 64.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1304304 2.96% 67.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1378179 3.13% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 896078 2.03% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11865768 26.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44211553 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367181 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.140391 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13076592 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8324763 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19681975 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2121490 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1006733 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2681054 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12065 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133596496 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 48387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1006733 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14226924 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4752424 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9184 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20532599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3683689 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 130038627 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69797 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2001155 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1372929 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 55394 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95511389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168978901 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161414982 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7563918 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44099332 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367496 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.142590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13096074 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8205573 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19698619 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2093424 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1005642 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2679978 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12191 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133453867 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 48806 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1005642 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14231650 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4726220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9532 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20537255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3589033 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 129931841 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 72505 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1962504 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1321371 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55153 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95440121 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168856219 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161261081 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7595137 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27084028 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 772 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 782 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8280120 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27136625 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8757663 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3565364 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1670156 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112744524 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28567051 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.265132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.094303 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27012760 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 775 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8114171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27101259 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8744711 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3477099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1649521 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112647261 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1499 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100144647 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120164 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28469050 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21866284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1110 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44099332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.270888 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.097444 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11585483 26.20% 26.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7800031 17.64% 43.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7580714 17.15% 60.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5746471 13.00% 73.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4482670 10.14% 84.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2978699 6.74% 90.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2013201 4.55% 95.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1153505 2.61% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 870779 1.97% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11543505 26.18% 26.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7764590 17.61% 43.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7534716 17.09% 60.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5714671 12.96% 73.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4493321 10.19% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2994712 6.79% 90.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2021459 4.58% 95.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1167850 2.65% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 864508 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44211553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44099332 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 481856 20.25% 20.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 350 0.01% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34531 1.45% 21.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11644 0.49% 22.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1006485 42.29% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 687304 28.88% 93.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 157568 6.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 476525 19.98% 19.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 437 0.02% 20.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34852 1.46% 21.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11487 0.48% 21.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1008602 42.30% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 692685 29.05% 93.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159938 6.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60921013 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491088 0.49% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2841000 2.84% 64.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115643 0.12% 64.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2440640 2.44% 66.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314095 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766051 0.76% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24991126 24.95% 92.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7264038 7.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60907964 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491070 0.49% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2843610 2.84% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115460 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2441189 2.44% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314170 0.31% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765827 0.76% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24997693 24.96% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7267338 7.26% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100145020 # Type of FU issued -system.cpu.iq.rate 2.252601 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131706335 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9649243 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1902679 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100144647 # Type of FU issued +system.cpu.iq.rate 2.258296 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2384526 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023811 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231229628 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131456710 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90023404 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15663688 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9702849 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7180664 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94162135 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8367031 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1912696 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7140427 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11100 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42139 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2256560 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7105061 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11423 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2243608 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42760 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1687 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42789 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1006733 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3731793 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 447885 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123749930 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 277756 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27136625 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8757663 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2237 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43684 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 396903 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42139 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 560048 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 524506 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1084554 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98770041 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24389817 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1374979 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1005642 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3713444 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 450339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123646937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 273080 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27101259 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8744711 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1499 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41770 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 401874 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 559712 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1083769 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98766968 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24388350 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1377679 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11003169 # number of nop insts executed -system.cpu.iew.exec_refs 31551638 # number of memory reference insts executed -system.cpu.iew.exec_branches 12536484 # Number of branches executed -system.cpu.iew.exec_stores 7161821 # Number of stores executed -system.cpu.iew.exec_rate 2.221673 # Inst execution rate -system.cpu.iew.wb_sent 97959187 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97215047 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67118954 # num instructions producing a value -system.cpu.iew.wb_consumers 95176065 # num instructions consuming a value +system.cpu.iew.exec_nop 10998177 # number of nop insts executed +system.cpu.iew.exec_refs 31553871 # number of memory reference insts executed +system.cpu.iew.exec_branches 12528994 # Number of branches executed +system.cpu.iew.exec_stores 7165521 # Number of stores executed +system.cpu.iew.exec_rate 2.227229 # Inst execution rate +system.cpu.iew.wb_sent 97952857 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97204068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67107593 # num instructions producing a value +system.cpu.iew.wb_consumers 95129025 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.186696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705208 # average fanout of values written-back +system.cpu.iew.wb_rate 2.191985 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705438 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31848480 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31745312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 966635 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39567002 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.322720 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.905630 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 965615 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39467684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.328565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.908680 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15032687 37.99% 37.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8622118 21.79% 59.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917590 9.90% 69.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1951695 4.93% 74.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1384336 3.50% 78.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1033619 2.61% 80.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694183 1.75% 82.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 726057 1.84% 84.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6204717 15.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14970260 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8589907 21.76% 59.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3909988 9.91% 69.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1952996 4.95% 74.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1374473 3.48% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034336 2.62% 80.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694993 1.76% 82.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731194 1.85% 84.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6209537 15.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39567002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39467684 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,344 +571,350 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 157112780 # The number of ROB reads -system.cpu.rob.rob_writes 252206838 # The number of ROB writes -system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 245947 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6209537 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 156905474 # The number of ROB reads +system.cpu.rob.rob_writes 251988235 # The number of ROB writes +system.cpu.timesIdled 4640 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245900 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.528126 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.528126 # CPI: Total CPI of All Threads -system.cpu.ipc 1.893487 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.893487 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133407543 # number of integer regfile reads -system.cpu.int_regfile_writes 73150911 # number of integer regfile writes -system.cpu.fp_regfile_reads 6256040 # number of floating regfile reads -system.cpu.fp_regfile_writes 6161921 # number of floating regfile writes -system.cpu.misc_regfile_reads 718993 # number of misc regfile reads +system.cpu.cpi 0.526792 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.526792 # CPI: Total CPI of All Threads +system.cpu.ipc 1.898281 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.898281 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133413106 # number of integer regfile reads +system.cpu.int_regfile_writes 73139309 # number of integer regfile writes +system.cpu.fp_regfile_reads 6258544 # number of floating regfile reads +system.cpu.fp_regfile_writes 6168597 # number of floating regfile writes +system.cpu.misc_regfile_reads 718994 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1458.668074 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28697534 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2246 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12777.174533 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1454.905467 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28683797 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12782.440731 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1458.668074 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.356120 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.356120 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1454.905467 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355202 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355202 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57416312 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57416312 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22204643 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22204643 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492628 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 263 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 263 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28697271 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28697271 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28697271 # number of overall hits -system.cpu.dcache.overall_hits::total 28697271 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1023 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1023 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8475 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8475 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1386 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57388820 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57388820 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22190893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22190893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492625 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492625 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 279 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 279 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28683518 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28683518 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28683518 # number of overall hits +system.cpu.dcache.overall_hits::total 28683518 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1012 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1012 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8478 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8478 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9498 # number of overall misses -system.cpu.dcache.overall_misses::total 9498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69711000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69711000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 550954965 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 550954965 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9490 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9490 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9490 # number of overall misses +system.cpu.dcache.overall_misses::total 9490 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 67994000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 67994000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 547632747 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 547632747 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 620665965 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 620665965 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 620665965 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 620665965 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22205666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22205666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 615626747 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 615626747 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 615626747 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 615626747 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22191905 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22191905 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 264 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 264 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28706769 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28706769 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28706769 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28706769 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 280 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 280 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28693008 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28693008 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28693008 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28693008 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003788 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003571 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68143.695015 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68143.695015 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65009.435398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65009.435398 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67187.747036 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67187.747036 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64594.567941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64594.567941 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65347.016740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65347.016740 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33287 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64871.100843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64871.100843 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33428 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 426 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 398 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.138498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.989950 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 175220995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175220995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 175220995 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39245500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39245500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137397495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 137397495 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78710.781430 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78710.781430 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 83500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 83500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77103.143418 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77103.143418 # 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Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32331281 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32331281 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16144798 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16144798 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16144798 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16144798 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16144798 # number of overall hits -system.cpu.icache.overall_hits::total 16144798 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14951 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14951 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14951 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14951 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14951 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29882.014581 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29882.014581 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 934 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 32280293 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32280293 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16119452 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16119452 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16119452 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16119452 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16119452 # number of overall hits +system.cpu.icache.overall_hits::total 16119452 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14840 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14840 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14840 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14840 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14840 # number of overall misses +system.cpu.icache.overall_misses::total 14840 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 447595000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 447595000 # 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miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000920 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000920 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000920 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000920 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000920 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30161.388140 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30161.388140 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30161.388140 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30161.388140 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30161.388140 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30161.388140 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 223 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3168 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3168 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3168 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3168 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3168 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3168 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11783 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11783 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11783 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11783 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11783 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11783 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 332403750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 332403750 # 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mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28210.451498 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28210.451498 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3131 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3131 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3131 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3131 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3131 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339198000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 339198000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000726 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000726 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000726 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000726 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000726 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000726 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28968.998207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28968.998207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28968.998207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28968.998207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28968.998207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28968.998207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2407.331968 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8790 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.450516 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2400.828541 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18535 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 914 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2430 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109467 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 118425 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 118425 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8720 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8775 # number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2424 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109497 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 196394 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 196394 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222851750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 113271750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 113271750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 190854250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145269250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 336123500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 190854250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145269250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 336123500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892578 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.286295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3066 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3066 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 455 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 455 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3066 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5229 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3066 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5229 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 117301000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 117301000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200218000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200218000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33419000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33419000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200218000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350938000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200218000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350938000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.372657 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.372657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62309.582109 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70016.411379 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63310.156250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66318.354801 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66318.354801 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.261850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.892157 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.892157 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.374758 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.374758 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68677.400468 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68677.400468 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65302.674494 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65302.674494 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73448.351648 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73448.351648 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 12295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12219 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 9822 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23566 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4601 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 28167 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 754112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 904832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11709 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 749376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 899968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 14138 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 23884 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 14138 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 23884 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 14138 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7178000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18279750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23884 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12051000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17563500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3635750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3520 # Transaction distribution -system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3521 # Transaction distribution system.membus.trans_dist::ReadExReq 1708 # Transaction distribution system.membus.trans_dist::ReadExResp 1708 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3521 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10458 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10458 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334656 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5228 # Request fanout histogram +system.membus.snoop_fanout::samples 5229 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5228 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5229 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5228 # Request fanout histogram -system.membus.reqLayer0.occupancy 6467500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5229 # Request fanout histogram +system.membus.reqLayer0.occupancy 6267000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27502000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27480000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index d21841628..f9aa76ee3 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131586 # Number of seconds simulated -sim_ticks 131586268500 # Number of ticks simulated -final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131585 # Number of seconds simulated +sim_ticks 131584694500 # Number of ticks simulated +final_tick 131584694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246297 # Simulator instruction rate (inst/s) -host_op_rate 259636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188078312 # Simulator tick rate (ticks/s) -host_mem_usage 317920 # Number of bytes of host memory used -host_seconds 699.64 # Real time elapsed on the host +host_inst_rate 242795 # Simulator instruction rate (inst/s) +host_op_rate 255945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 185402255 # Simulator tick rate (ticks/s) +host_mem_usage 318276 # Number of bytes of host memory used +host_seconds 709.73 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138368 # Nu system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1051551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1882286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 830735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1882286 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3870 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131586174000 # Total gap between requests +system.physmem.totGap 131584601000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation -system.physmem.totQLat 26462250 # Total ticks spent queuing -system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.614035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.051598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.679496 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 270 29.61% 29.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 38.05% 67.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.54% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 54 5.92% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 40 4.39% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20 2.19% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.97% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation +system.physmem.totQLat 27229750 # Total ticks spent queuing +system.physmem.totMemAccLat 99792250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7036.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25786.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2963 # Number of row buffer hits during reads +system.physmem.readRowHits 2952 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34001595.35 # Average gap between requests -system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34001188.89 # Average gap between requests +system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.824061 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states +system.physmem_0.actBackEnergy 3579629355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75808025250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88002824835 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.815686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126113612750 # Time in different power states system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1075043250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3749760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2046000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.792204 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states +system.physmem_1.actBackEnergy 3571830900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75814874250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88000431150 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.797424 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126123074750 # Time in different power states system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1063297750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49889699 # Number of BP lookups -system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted +system.cpu.branchPred.lookups 49889701 # Number of BP lookups +system.cpu.branchPred.condPredicted 39633557 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24337782 # Number of BTB lookups system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 95.653737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263172537 # number of cpu cycles simulated +system.cpu.numCycles 263169389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11983759 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.527251 # CPI: cycles per instruction -system.cpu.ipc 0.654771 # IPC: instructions per cycle -system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.527233 # CPI: cycles per instruction +system.cpu.ipc 0.654779 # IPC: instructions per cycle +system.cpu.tickCycles 256740818 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6428571 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.711326 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40793911 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22538.072376 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.711326 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336355 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336355 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -408,36 +408,36 @@ system.cpu.dcache.tags.tag_accesses 81594514 # Nu system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40748634 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40748634 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40749098 # number of overall hits -system.cpu.dcache.overall_hits::total 40749098 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40748633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40748633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40749097 # number of overall hits +system.cpu.dcache.overall_hits::total 40749097 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2439 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2440 # number of overall misses -system.cpu.dcache.overall_misses::total 2440 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57815734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126489000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184304734 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184304734 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57382000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57382000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126740000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126740000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184122000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184122000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184122000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184122000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72360.655738 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72360.655738 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76952.034001 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76952.034001 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75459.836066 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75459.836066 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75428.922573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75428.922573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 549 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 549 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 631 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 631 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 631 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51168764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51168764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84319000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84319000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 135487764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 135487764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 135557264 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136279500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136279500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136349500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136349500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71777.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71777.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77637.067395 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77637.067395 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75334.162521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75334.162521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75331.215470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75331.215470 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2889 # number of replacements -system.cpu.icache.tags.tagsinuse 1425.913177 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71538503 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1425.919952 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71538505 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15263.175379 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 15263.175805 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1425.913177 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.696247 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.696247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1425.919952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.696250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.696250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id @@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 493 system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143091069 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143091069 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71538503 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71538503 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71538503 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71538503 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71538503 # number of overall hits -system.cpu.icache.overall_hits::total 71538503 # number of overall hits +system.cpu.icache.tags.tag_accesses 143091073 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143091073 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71538505 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71538505 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71538505 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71538505 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71538505 # number of overall hits +system.cpu.icache.overall_hits::total 71538505 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4688 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4688 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4688 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4688 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4688 # number of overall misses system.cpu.icache.overall_misses::total 4688 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200735747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200735747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200735747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200735747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200735747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200735747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71543191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71543191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71543191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71543191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71543191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71543191 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 199914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 199914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 199914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 199914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 199914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 199914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71543193 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71543193 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71543193 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71543193 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71543193 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71543193 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42819.058660 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42819.058660 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42819.058660 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42819.058660 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.771331 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42643.771331 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42643.771331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42643.771331 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,117 +597,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4688 system.cpu.icache.demand_mshr_misses::total 4688 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4688 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4688 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192780753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192780753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192780753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192780753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192780753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192780753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41122.174275 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41122.174275 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.984642 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41643.984642 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41643.984642 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41643.984642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41643.984642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41643.984642 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2002.534339 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2603 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2002.545063 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5192 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.933644 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.862267 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.688891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.816250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029187 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.695895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.819981 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046042 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061112 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061113 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2788 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 523 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 154 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2006 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085083 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 55998 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 55998 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2522 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2602 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 76702 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76702 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2522 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2523 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2523 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2523 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2610 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2522 # number of overall hits +system.cpu.l2cache.demand_hits::total 2611 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2523 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits -system.cpu.l2cache.overall_hits::total 2610 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2166 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2798 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 2611 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2166 # number of demand (read+write) misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2165 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2165 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2165 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3888 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2166 # number of overall misses +system.cpu.l2cache.demand_misses::total 3887 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2165 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses -system.cpu.l2cache.overall_misses::total 3888 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161612750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49681750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 211294500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83135500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 83135500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 161612750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 132817250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 294430000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 161612750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 132817250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294430000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4688 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5400 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 3887 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83513000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83513000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161704000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 161704000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49184000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49184000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 132697000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294401000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 132697000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294401000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4688 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4688 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 4688 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 6498 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4688 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 6498 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462031 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.518148 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462031 # miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461817 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461817 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461817 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598338 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462031 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.598184 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598338 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74613.457987 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78610.363924 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75516.261615 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76271.100917 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76271.100917 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75727.880658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75727.880658 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.598184 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76617.431193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76617.431193 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74690.069284 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74690.069284 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.784810 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.784810 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74690.069284 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77059.814170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75739.902238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74690.069284 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77059.814170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75739.902238 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,93 +722,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2163 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2781 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3871 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3871 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134379750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40985000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175364750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134379750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110492000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 244871750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134379750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110492000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 244871750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139936000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139936000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42042000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42042000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139936000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 114655000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254591000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139936000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 114655000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254591000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461391 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66617.431193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66617.431193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64695.330559 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64695.330559 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68029.126214 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68029.126214 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2588 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11943 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15599 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9429 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9429 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9429 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4730500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7031498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2780 # Transaction distribution system.membus.trans_dist::ReadResp 2780 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2780 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes) @@ -818,9 +831,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3870 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4532500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20566750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a8c1caea2..b441da851 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085032 # Number of seconds simulated -sim_ticks 85032044000 # Number of ticks simulated -final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085019 # Number of seconds simulated +sim_ticks 85018904000 # Number of ticks simulated +final_tick 85018904000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135904 # Simulator instruction rate (inst/s) -host_op_rate 143266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67069129 # Simulator tick rate (ticks/s) -host_mem_usage 314096 # Number of bytes of host memory used -host_seconds 1267.83 # Real time elapsed on the host +host_inst_rate 135768 # Simulator instruction rate (inst/s) +host_op_rate 143122 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66991355 # Simulator tick rate (ticks/s) +host_mem_usage 315704 # Number of bytes of host memory used +host_seconds 1269.10 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory -system.physmem.bytes_read::total 245888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1494025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 558472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2891710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1494025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1494025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1494025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 558472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2891710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3842 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71296 # Number of bytes read from this memory +system.physmem.bytes_read::total 246144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1114 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3846 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1493503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 563075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 838590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2895168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1493503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1493503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1493503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 563075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 838590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2895168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3846 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3846 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246144 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246144 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,16 +48,16 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 309 # Per bank write bursts system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::3 309 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 233 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 291 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 191 # Per bank write bursts +system.physmem.perBankRdBursts::12 193 # Per bank write bursts system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85031900500 # Total gap between requests +system.physmem.totGap 85018760500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3842 # Read request sizes (log2) +system.physmem.readPktSize::6 3846 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,16 +94,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 763 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.083879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.433795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.783352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 232 30.41% 30.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191 25.03% 55.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 11.53% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 11.27% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 27 3.54% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.85% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11 1.44% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 2.23% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 74 9.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 763 # Bytes accessed per row activation -system.physmem.totQLat 43141443 # Total ticks spent queuing -system.physmem.totMemAccLat 115178943 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11228.90 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.211068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.877402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.919917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 237 30.50% 30.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 193 24.84% 55.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 10.81% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 88 11.33% 77.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.50% 81.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 40 5.15% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 20 2.57% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 1.67% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 67 8.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 777 # Bytes accessed per row activation +system.physmem.totQLat 39111678 # Total ticks spent queuing +system.physmem.totMemAccLat 111224178 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10169.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29978.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28919.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.30 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3071 # Number of row buffer hits during reads +system.physmem.readRowHits 3067 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22132196.90 # Average gap between requests -system.physmem.pageHitRate 79.93 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2729160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1489125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22105761.96 # Average gap between requests +system.physmem.pageHitRate 79.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2744280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1497375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16231800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2330695800 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48971187750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56875754235 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.921152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81466351731 # Time in different power states -system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states +system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2336092560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48961790250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56871322905 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.930183 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81450773508 # Time in different power states +system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 720558269 # Time in different power states +system.physmem_0.memoryStateTime::ACT 728623992 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3016440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1645875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13548600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13712400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2293230555 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49004052000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56868968670 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.841346 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81522647918 # Time in different power states -system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states +system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2289194100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49002929250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56863639980 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.839816 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81519548908 # Time in different power states +system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 665486082 # Time in different power states +system.physmem_1.memoryStateTime::ACT 659848592 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85925704 # Number of BP lookups -system.cpu.branchPred.condPredicted 68401753 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6018362 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40106814 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39018678 # Number of BTB hits +system.cpu.branchPred.lookups 85912123 # Number of BP lookups +system.cpu.branchPred.condPredicted 68393040 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6015536 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40101118 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014565 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.286905 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3705148 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81894 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.290467 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3703089 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,130 +381,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170064089 # number of cpu cycles simulated +system.cpu.numCycles 170037809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5613343 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349288276 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85925704 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42723826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158284040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12050671 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5613511 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349250633 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85912123 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42717654 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158261511 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12044973 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2225 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78959765 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169926703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2368 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78950648 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169901476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17361476 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30212798 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31840839 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90511590 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17358895 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30204196 17.78% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31835534 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90502851 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169926703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505255 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053863 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17566577 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17110905 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122676579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722207 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5850435 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11136607 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190140 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306627324 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27647944 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5850435 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37756146 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8468505 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108935441 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8337063 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278668040 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13416082 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3052051 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841470 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187697 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36000 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26450 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483113762 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196983953 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297587542 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006013 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169901476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505253 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17563828 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17110473 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122657456 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6722156 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5847563 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11134699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190129 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306600036 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27639970 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5847563 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37745979 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8468798 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579877 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108923634 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8335625 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278650711 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13412582 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051453 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842711 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2185712 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 35165 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483080894 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196921588 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297573906 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190136833 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23525 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23424 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13336678 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34143660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476609 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2548114 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1810648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264825192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45854 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214913936 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5193552 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83235092 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219939501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 638 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169926703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264745 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190103965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13336347 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34142095 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476543 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549376 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214902718 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219925398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169901476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264867 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.017460 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52848454 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36099011 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65787739 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13574201 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1569834 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47276 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52832101 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36093158 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65784259 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13574357 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570220 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47195 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169926703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169901476 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35606881 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152777 0.28% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35605011 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35731 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 243 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1036 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34373 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1037 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14081261 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945561 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078469 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945889 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167354642 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918991 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167344164 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -525,91 +525,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165174 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165202 0.08% 78.39% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460494 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206680 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32007537 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373732 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32006921 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373534 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214913936 # Type of FU issued -system.cpu.iq.rate 1.263723 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53859137 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654855291 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346101904 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204603491 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3951973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011176 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806361 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266640239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2132834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601131 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214902718 # Type of FU issued +system.cpu.iq.rate 1.263853 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53854775 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654798543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204597394 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953764 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266623027 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134466 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1601141 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6247516 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7571 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7104 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1831975 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6245951 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7537 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1831909 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25920 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 745 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 804 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5850435 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682032 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37041 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264886958 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5847563 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681873 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37049 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34143660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476609 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7104 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3234550 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6482668 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207528127 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7385809 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34142095 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476543 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29963 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207521850 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720954 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380868 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15912 # number of nop insts executed -system.cpu.iew.exec_refs 43861162 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936179 # Number of branches executed -system.cpu.iew.exec_stores 13139666 # Number of stores executed -system.cpu.iew.exec_rate 1.220294 # Inst execution rate -system.cpu.iew.wb_sent 206744895 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409852 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129477271 # num instructions producing a value -system.cpu.iew.wb_consumers 221697359 # num instructions consuming a value +system.cpu.iew.exec_nop 15987 # number of nop insts executed +system.cpu.iew.exec_refs 43860782 # number of memory reference insts executed +system.cpu.iew.exec_branches 44934590 # Number of branches executed +system.cpu.iew.exec_stores 13139828 # Number of stores executed +system.cpu.iew.exec_rate 1.220445 # Inst execution rate +system.cpu.iew.wb_sent 206738830 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206403837 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129472700 # num instructions producing a value +system.cpu.iew.wb_consumers 221699640 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213718 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584027 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213870 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584000 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69541697 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69532932 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5843462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158482976 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646662 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158460459 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646701 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73704941 46.51% 46.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41274815 26.04% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22552900 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9628649 6.08% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3549516 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148015 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986897 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3356952 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73681032 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41276330 26.05% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22553900 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9626912 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147757 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1281176 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3356651 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158482976 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158460459 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,374 +655,380 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3356952 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406312862 # The number of ROB reads -system.cpu.rob.rob_writes 513841850 # The number of ROB writes -system.cpu.timesIdled 3415 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 137386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3356651 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406281881 # The number of ROB reads +system.cpu.rob.rob_writes 513821502 # The number of ROB writes +system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 136333 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.987006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.987006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218961575 # number of integer regfile reads -system.cpu.int_regfile_writes 114515726 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904225 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441500 # number of floating regfile writes -system.cpu.cc_regfile_reads 709589041 # number of cc regfile reads -system.cpu.cc_regfile_writes 229545726 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313943 # number of misc regfile reads +system.cpu.cpi 0.986853 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986853 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013322 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013322 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218956398 # number of integer regfile reads +system.cpu.int_regfile_writes 114512064 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes +system.cpu.cc_regfile_reads 709567727 # number of cc regfile reads +system.cpu.cc_regfile_writes 229536120 # number of cc regfile writes +system.cpu.misc_regfile_reads 59314176 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72899 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418278 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41116599 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73411 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.087712 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418278 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72863 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.419653 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73375 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.346698 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504093500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.419653 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998867 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998867 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82531693 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82531693 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28730266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28730266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341417 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341417 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529747 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529747 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729201 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729201 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341321 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41071683 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41071683 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41072044 # number of overall hits -system.cpu.dcache.overall_hits::total 41072044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89294 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89294 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22870 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22870 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112164 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112164 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112282 # number of overall misses -system.cpu.dcache.overall_misses::total 112282 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 853196487 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 853196487 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241173427 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241173427 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1094369914 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1094369914 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1094369914 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1094369914 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819560 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41070883 # number of overall hits +system.cpu.dcache.overall_hits::total 41070883 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89405 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22966 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22966 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112488 # number of overall misses +system.cpu.dcache.overall_misses::total 112488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853901000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853901000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 240852499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 240852499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1094753499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1094753499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1094753499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1094753499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 478 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41183847 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41183847 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41184326 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41184326 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001850 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001850 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011603 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011603 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9554.913958 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9554.913958 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10545.405641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10545.405641 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9756.873097 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9756.873097 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9746.619351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9746.619351 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9765 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182893 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182893 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183371 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183371 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9550.931156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9550.931156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10487.350823 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10487.350823 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9742.313399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9742.313399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9732.180313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9732.180313 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10552 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 848 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11.515330 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.198844 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64878 # number of writebacks -system.cpu.dcache.writebacks::total 64878 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24567 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24567 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14301 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14301 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38868 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38868 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38868 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38868 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64727 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64727 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8569 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8569 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73411 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73411 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526755010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 526755010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81248758 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81248758 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 920500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 920500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608003768 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 608003768 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 608924268 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 608924268 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks +system.cpu.dcache.writebacks::total 64850 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24706 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24706 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14404 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14404 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39110 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39110 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39110 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39110 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64699 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64699 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 643478499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 643478499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 644448499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 644448499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8138.103264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8138.103264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9481.708251 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9481.708251 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8004.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8004.347826 # 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Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603252 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997272 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997272 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54433 # number of replacements +system.cpu.icache.tags.tagsinuse 510.604366 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78892637 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.847429 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84263927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.604366 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997274 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157974458 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157974458 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78902001 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 55224 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 157956201 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157956201 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78892637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78892637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78892637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78892637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78892637 # number of overall hits +system.cpu.icache.overall_hits::total 78892637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57991 # number of overall misses +system.cpu.icache.overall_misses::total 57991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 602655456 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 602655456 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 602655456 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 602655456 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 602655456 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 602655456 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78950628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78950628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78950628 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10392.223897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10392.223897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 58612 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2764 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2849 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.979740 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.572833 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2767 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2767 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2767 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2767 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2767 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2767 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54974 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54974 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54974 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54974 # 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number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3046 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3046 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3046 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54945 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54945 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54945 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54945 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54945 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54945 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 535420965 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 535420965 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 535420965 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 417.075318 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 175.258376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 701.934591 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.049531 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 421.061183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 161.231311 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.042843 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083985 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.025456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010697 # 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number of ReadReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::total 2 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1985 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 505 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2490 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1805 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1805 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 237 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 237 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1985 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 742 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2727 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1985 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 742 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1805 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4532 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 119139257 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 32909250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 152048507 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70744400 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70744400 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 119139257 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48849500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 167988757 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119139257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48849500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70744400 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 238733157 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007796 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020793 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1818 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1818 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1984 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1984 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 513 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 513 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1984 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1984 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1818 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4550 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70301588 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16173000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16173000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 123686500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 123686500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33594500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33594500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 123686500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 173454000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 123686500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49767500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 243755588 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021241 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027218 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027218 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036109 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007924 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021291 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035300 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60019.776826 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65166.831683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61063.657430 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39193.573407 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67258.438819 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67258.438819 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61602.037770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52677.219109 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035458 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38669.740374 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68821.276596 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68821.276596 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62341.985887 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62341.985887 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65486.354776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65486.354776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63489.751098 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53572.656703 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3518336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2153 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011018 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 119686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64741 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217450 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12362880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2160 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 257776 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.008379 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.091155 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 193263 98.90% 98.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2153 1.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 255616 99.16% 99.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2160 0.84% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 257776 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192658000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82870477 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82430973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110219231 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110066991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3605 # Transaction distribution -system.membus.trans_dist::ReadResp 3605 # Transaction distribution -system.membus.trans_dist::ReadExReq 237 # Transaction distribution -system.membus.trans_dist::ReadExResp 237 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3611 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3611 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7692 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7692 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3842 # Request fanout histogram +system.membus.snoop_fanout::samples 3846 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3846 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3842 # Request fanout histogram -system.membus.reqLayer0.occupancy 4969720 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3846 # Request fanout histogram +system.membus.reqLayer0.occupancy 5081597 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20244552 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20277583 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 1d32cdbce..8e968af2a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.081225 # Number of seconds simulated -sim_ticks 81224844500 # Number of ticks simulated -final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.081371 # Number of seconds simulated +sim_ticks 81371461000 # Number of ticks simulated +final_tick 81371461000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91947 # Simulator instruction rate (inst/s) -host_op_rate 154111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56548085 # Simulator tick rate (ticks/s) -host_mem_usage 347388 # Number of bytes of host memory used -host_seconds 1436.39 # Real time elapsed on the host +host_inst_rate 90424 # Simulator instruction rate (inst/s) +host_op_rate 151559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55711800 # Simulator tick rate (ticks/s) +host_mem_usage 348672 # Number of bytes of host memory used +host_seconds 1460.58 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125760 # Number of bytes read from this memory -system.physmem.bytes_read::total 350528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2767232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1548295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4315527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2767232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2767232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2767232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1548295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4315527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5477 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 224128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory +system.physmem.bytes_read::total 349632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224128 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5463 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2754381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1542359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4296740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2754381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2754381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2754381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1542359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4296740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5463 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5463 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 350528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 349632 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 350528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 349632 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 298 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 295 # Per bank write bursts -system.physmem.perBankRdBursts::1 355 # Per bank write bursts -system.physmem.perBankRdBursts::2 457 # Per bank write bursts -system.physmem.perBankRdBursts::3 353 # Per bank write bursts -system.physmem.perBankRdBursts::4 337 # Per bank write bursts -system.physmem.perBankRdBursts::5 331 # Per bank write bursts -system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 389 # Per bank write bursts -system.physmem.perBankRdBursts::8 346 # Per bank write bursts -system.physmem.perBankRdBursts::9 296 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 312 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 292 # Per bank write bursts +system.physmem.perBankRdBursts::1 354 # Per bank write bursts +system.physmem.perBankRdBursts::2 456 # Per bank write bursts +system.physmem.perBankRdBursts::3 360 # Per bank write bursts +system.physmem.perBankRdBursts::4 330 # Per bank write bursts +system.physmem.perBankRdBursts::5 342 # Per bank write bursts +system.physmem.perBankRdBursts::6 399 # Per bank write bursts +system.physmem.perBankRdBursts::7 387 # Per bank write bursts +system.physmem.perBankRdBursts::8 324 # Per bank write bursts +system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 240 # Per bank write bursts -system.physmem.perBankRdBursts::11 297 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts system.physmem.perBankRdBursts::12 220 # Per bank write bursts -system.physmem.perBankRdBursts::13 472 # Per bank write bursts -system.physmem.perBankRdBursts::14 395 # Per bank write bursts -system.physmem.perBankRdBursts::15 294 # Per bank write bursts +system.physmem.perBankRdBursts::13 487 # Per bank write bursts +system.physmem.perBankRdBursts::14 392 # Per bank write bursts +system.physmem.perBankRdBursts::15 328 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 81224754500 # Total gap between requests +system.physmem.totGap 81371407000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5477 # Read request sizes (log2) +system.physmem.readPktSize::6 5463 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,174 +186,173 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.296820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.870491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.897635 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 457 40.37% 40.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 236 20.85% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 108 9.54% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.12% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 52 4.59% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 5.04% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 1.33% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.59% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 131 11.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1132 # Bytes accessed per row activation -system.physmem.totQLat 39829000 # Total ticks spent queuing -system.physmem.totMemAccLat 142522750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7272.05 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.177405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.606569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.434363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 453 39.98% 39.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241 21.27% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 107 9.44% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 66 5.83% 76.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 3.71% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 53 4.68% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 2.65% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.59% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 123 10.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1133 # Bytes accessed per row activation +system.physmem.totQLat 39364000 # Total ticks spent queuing +system.physmem.totMemAccLat 141795250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27315000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7205.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26022.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25955.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4337 # Number of row buffer hits during reads +system.physmem.readRowHits 4322 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.11 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14830154.19 # Average gap between requests -system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4944240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2697750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22612200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14895004.03 # Average gap between requests +system.physmem.pageHitRate 79.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22627800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2574291285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 46473030000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 54382364835 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.579902 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 77308994750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2712060000 # Time in different power states +system.physmem_0.refreshEnergy 5314452000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2576418525 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 46559935500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 54481005705 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.574677 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 77452365250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2717000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1198731250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1197234500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3598560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1963500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19773000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3643920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1988250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19640400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2411784000 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 46615580250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 54357488670 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.273616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 77550451000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2712060000 # Time in different power states +system.physmem_1.refreshEnergy 5314452000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2400589485 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 46714163250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 54454477305 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.248755 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 77713281250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2717000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 960225000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 939125250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 21757824 # Number of BP lookups -system.cpu.branchPred.condPredicted 21757824 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1548941 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13682195 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12857487 # Number of BTB hits +system.cpu.branchPred.lookups 21769917 # Number of BP lookups +system.cpu.branchPred.condPredicted 21769917 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1549122 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 13731962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12878566 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.972400 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1522808 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.785331 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1523299 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21478 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 162449690 # number of cpu cycles simulated +system.cpu.numCycles 162742923 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27167357 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 241462052 # Number of instructions fetch has processed -system.cpu.fetch.Branches 21757824 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14380295 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 133204520 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3672137 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 11 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 3242 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 32817 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27183337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 241535825 # Number of instructions fetch has processed +system.cpu.fetch.Branches 21769917 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14401865 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 133481172 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3672135 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 3449 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 35973 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 121 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26014450 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320059 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162244149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.449323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26033005 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 162540128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.445335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.347989 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 96544935 59.51% 59.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4966288 3.06% 62.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3924303 2.42% 64.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4589791 2.83% 67.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4444336 2.74% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5042325 3.11% 73.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5076481 3.13% 76.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3889378 2.40% 79.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33766312 20.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96819226 59.57% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4970692 3.06% 62.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3926504 2.42% 65.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4600449 2.83% 67.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4436163 2.73% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5045508 3.10% 73.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5083113 3.13% 76.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3898601 2.40% 79.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33759872 20.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162244149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133936 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.486381 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16503411 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96610290 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 25882430 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21411950 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1836068 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 352729241 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1836068 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24442767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33233774 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38303751 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 64396780 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 343252745 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1943 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 56953505 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7545423 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 167940 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 397342568 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 949709399 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 627052131 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4618257 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 162540128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133769 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.484156 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16504764 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96892991 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 25874540 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21431766 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1836067 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 352818767 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1836067 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24444805 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33422530 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30828 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38315708 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 64490190 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 343379412 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1374 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57139077 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7429063 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 172376 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 397453727 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 950141626 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 627304694 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4642412 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 137913118 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2060 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120010907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 87039709 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31137080 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 61853756 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20927707 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331596276 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4834 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 264603975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 77857 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 110237726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 225639096 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3589 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162244149 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.630900 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.539803 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 138024277 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2171 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2092 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 120106098 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 87123680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31143046 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 62089518 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21014033 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 331702995 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4700 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 264529155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 75427 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 110344311 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 226235086 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3455 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162540128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.627470 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.538199 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 42788422 26.37% 26.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47622129 29.35% 55.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33320454 20.54% 76.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18328192 11.30% 87.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11302199 6.97% 94.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4922011 3.03% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2609014 1.61% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 930397 0.57% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 421331 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 42962851 26.43% 26.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47766675 29.39% 55.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33381943 20.54% 76.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18299706 11.26% 87.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11254917 6.92% 94.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4928041 3.03% 97.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2601211 1.60% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 925935 0.57% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 418849 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162244149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162540128 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 230632 7.18% 7.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 228422 7.18% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.18% # attempts to use FU when none available @@ -382,118 +381,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.18% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2590896 80.61% 87.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 392432 12.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2563241 80.56% 87.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 390075 12.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211493 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 165364025 62.49% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 786761 0.30% 63.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038559 2.66% 65.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1211557 0.46% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66257169 25.04% 91.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22734411 8.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211775 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 165335672 62.50% 62.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 786316 0.30% 63.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038827 2.66% 65.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1212035 0.46% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66231753 25.04% 91.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22712777 8.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 264603975 # Type of FU issued -system.cpu.iq.rate 1.628836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3213960 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 689757647 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 437892717 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 258330357 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4986269 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4261617 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2393080 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 264097165 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2509277 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18796485 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 264529155 # Type of FU issued +system.cpu.iq.rate 1.625442 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3181738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012028 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 689869496 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 438078029 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 258256761 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4986107 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4289171 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2392105 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263990006 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2509112 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18745493 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30390155 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14027 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 322538 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10621363 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30474102 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13683 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 322031 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10627329 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52082 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52743 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1836068 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 14114838 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 500285 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331601110 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108836 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 87039742 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31137080 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2060 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 401860 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 61208 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 322538 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 680213 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 929259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1609472 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 262268386 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65330198 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2335589 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1836067 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 14124717 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 495168 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 331707695 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 107609 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 87123689 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31143046 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 394182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 62934 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 322031 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 682027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 925981 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1608008 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 262198462 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65303975 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2330693 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87858182 # number of memory reference insts executed -system.cpu.iew.exec_branches 14520351 # Number of branches executed -system.cpu.iew.exec_stores 22527984 # Number of stores executed -system.cpu.iew.exec_rate 1.614459 # Inst execution rate -system.cpu.iew.wb_sent 261554043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 260723437 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208617070 # num instructions producing a value -system.cpu.iew.wb_consumers 375029707 # num instructions consuming a value +system.cpu.iew.exec_refs 87811155 # number of memory reference insts executed +system.cpu.iew.exec_branches 14511685 # Number of branches executed +system.cpu.iew.exec_stores 22507180 # Number of stores executed +system.cpu.iew.exec_rate 1.611121 # Inst execution rate +system.cpu.iew.wb_sent 261483321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 260648866 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208559295 # num instructions producing a value +system.cpu.iew.wb_consumers 374938421 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.604949 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.556268 # average fanout of values written-back +system.cpu.iew.wb_rate 1.601599 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.556249 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110244875 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110351288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1552031 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147195030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.503878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.943897 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1552443 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147477365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.500999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.940236 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 47434016 32.23% 32.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57618157 39.14% 71.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14262797 9.69% 81.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11889308 8.08% 89.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4213027 2.86% 92.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2877009 1.95% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 914800 0.62% 94.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1061572 0.72% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6924344 4.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 47558134 32.25% 32.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57784481 39.18% 71.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14247523 9.66% 81.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11907169 8.07% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4233466 2.87% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2889588 1.96% 93.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 908406 0.62% 94.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1058674 0.72% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6889924 4.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147195030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147477365 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -539,75 +538,74 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6924344 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 471878945 # The number of ROB reads -system.cpu.rob.rob_writes 678308439 # The number of ROB writes -system.cpu.timesIdled 2694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 205541 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6889924 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 472302113 # The number of ROB reads +system.cpu.rob.rob_writes 678534776 # The number of ROB writes +system.cpu.timesIdled 2601 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 202795 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.230016 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.230016 # CPI: Total CPI of All Threads -system.cpu.ipc 0.812998 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.812998 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 454025160 # number of integer regfile reads -system.cpu.int_regfile_writes 236935746 # number of integer regfile writes -system.cpu.fp_regfile_reads 3267968 # number of floating regfile reads -system.cpu.fp_regfile_writes 2053127 # number of floating regfile writes -system.cpu.cc_regfile_reads 102766500 # number of cc regfile reads -system.cpu.cc_regfile_writes 60037026 # number of cc regfile writes -system.cpu.misc_regfile_reads 135494920 # number of misc regfile reads +system.cpu.cpi 1.232236 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.232236 # CPI: Total CPI of All Threads +system.cpu.ipc 0.811533 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.811533 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 453858264 # number of integer regfile reads +system.cpu.int_regfile_writes 236894069 # number of integer regfile writes +system.cpu.fp_regfile_reads 3268800 # number of floating regfile reads +system.cpu.fp_regfile_writes 2052370 # number of floating regfile writes +system.cpu.cc_regfile_reads 102728686 # number of cc regfile reads +system.cpu.cc_regfile_writes 60021475 # number of cc regfile writes +system.cpu.misc_regfile_reads 135450288 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 56 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.236298 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66889390 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2008 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33311.449203 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 22 # number of replacements +system.cpu.dcache.tags.tagsinuse 1449.922463 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66913357 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1999 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33473.415208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.236298 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1952 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 484 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.476562 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 133785736 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 133785736 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46375033 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46375033 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513891 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513891 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66888924 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66888924 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66888924 # number of overall hits -system.cpu.dcache.overall_hits::total 66888924 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1100 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1100 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1840 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1840 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2940 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2940 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2940 # number of overall misses -system.cpu.dcache.overall_misses::total 2940 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68941167 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68941167 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128874548 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128874548 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 197815715 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 197815715 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 197815715 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 197815715 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46376133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46376133 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1449.922463 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 483 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1444 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.482666 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 133833717 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 133833717 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46399026 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46399026 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513875 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513875 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66912901 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66912901 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66912901 # number of overall hits +system.cpu.dcache.overall_hits::total 66912901 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1856 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1856 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2958 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2958 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2958 # number of overall misses +system.cpu.dcache.overall_misses::total 2958 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 70369000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 70369000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128824000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128824000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 199193000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 199193000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 199193000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 199193000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46400128 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46400128 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66891864 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66891864 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66891864 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66891864 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66915859 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66915859 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66915859 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66915859 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses @@ -616,258 +614,264 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62673.788182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62673.788182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70040.515217 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70040.515217 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67284.256803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67284.256803 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63855.716878 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63855.716878 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69409.482759 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69409.482759 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67340.432725 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67340.432725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67340.432725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67340.432725 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 318 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 52 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1839 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1839 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2307 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2307 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2307 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2307 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36256250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36256250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125371702 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125371702 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161627952 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161627952 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161627952 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161627952 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 11 # number of writebacks +system.cpu.dcache.writebacks::total 11 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 641 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 641 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 643 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 643 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 643 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1854 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1854 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2315 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2315 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2315 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2315 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36642000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36642000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126830000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126830000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163472000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163472000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163472000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163472000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77470.619658 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77470.619658 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68173.845568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68173.845568 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79483.731020 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79483.731020 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68408.845739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68408.845739 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70614.254860 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70614.254860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70614.254860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70614.254860 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5865 # number of replacements -system.cpu.icache.tags.tagsinuse 1646.159130 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26003921 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7839 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3317.249777 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5619 # number of replacements +system.cpu.icache.tags.tagsinuse 1637.148267 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26022644 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7593 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3427.188726 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1646.159130 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.803789 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.803789 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1637.148267 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.799389 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.799389 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1974 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 898 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 773 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 882 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 786 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.963867 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 52037036 # Number of tag accesses -system.cpu.icache.tags.data_accesses 52037036 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26003921 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26003921 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26003921 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26003921 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26003921 # number of overall hits -system.cpu.icache.overall_hits::total 26003921 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10528 # number of overall misses -system.cpu.icache.overall_misses::total 10528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 430452747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 430452747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 430452747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 430452747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 430452747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 430452747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26014449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26014449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26014449 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26014449 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26014449 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26014449 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000405 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000405 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000405 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000405 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000405 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000405 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40886.469130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40886.469130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40886.469130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40886.469130 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1891 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 52073916 # Number of tag accesses +system.cpu.icache.tags.data_accesses 52073916 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26022649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26022649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26022649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26022649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26022649 # number of overall hits +system.cpu.icache.overall_hits::total 26022649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10355 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10355 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10355 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10355 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10355 # number of overall misses +system.cpu.icache.overall_misses::total 10355 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419159499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419159499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419159499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419159499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419159499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419159499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26033004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26033004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26033004 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26033004 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26033004 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26033004 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40478.947272 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40478.947272 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40478.947272 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40478.947272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40478.947272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40478.947272 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.535714 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 51.538462 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2389 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2389 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2389 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2389 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2389 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2389 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8139 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8139 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8139 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8139 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8139 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8139 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322188751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322188751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322188751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322188751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322188751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322188751 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39585.790761 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39585.790761 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2445 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2445 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2445 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2445 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2445 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2445 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 320594000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 320594000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 320594000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 320594000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 320594000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 320594000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000304 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000304 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000304 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000304 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000304 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000304 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40530.214918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40530.214918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40530.214918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40530.214918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40530.214918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40530.214918 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2629.714027 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4366 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3947 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.106157 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2621.537078 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9541 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3929 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.428353 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2.821104 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2311.277195 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 315.615728 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000086 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 230285500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 230285500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31255500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31255500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130354500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 360640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130354500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 360640000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987342 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987342 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461285 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.930435 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.930435 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980990 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569582 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980990 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569582 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20717.948718 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20717.948718 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65739.508992 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65739.508992 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73026.869159 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73026.869159 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65739.508992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66473.482917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66002.928258 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65739.508992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66473.482917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66002.928258 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 8606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4627 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 299 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 8368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 460 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4651 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 25555 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 485888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 614528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 316 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 15866 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10459 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15866 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 15866 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7944000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12871748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11862000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3552548 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3157498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3944 # Transaction distribution -system.membus.trans_dist::ReadResp 3944 # Transaction distribution -system.membus.trans_dist::UpgradeReq 298 # Transaction distribution -system.membus.trans_dist::UpgradeResp 298 # Transaction distribution +system.membus.trans_dist::ReadResp 3929 # Transaction distribution +system.membus.trans_dist::UpgradeReq 312 # Transaction distribution +system.membus.trans_dist::UpgradeResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 1533 # Transaction distribution system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11550 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 350528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3930 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11549 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11549 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11549 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 349568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 5775 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram @@ -983,9 +993,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5775 # Request fanout histogram -system.membus.reqLayer0.occupancy 6990000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7111000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29627952 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29581688 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |