diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/se | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/se')
36 files changed, 9186 insertions, 8017 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index e070ad588..ab0c1f304 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6e907f4cc..a6e3b7d23 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026913 # Number of seconds simulated -sim_ticks 26912680500 # Number of ticks simulated -final_tick 26912680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026911 # Number of seconds simulated +sim_ticks 26911413000 # Number of ticks simulated +final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145850 # Simulator instruction rate (inst/s) -host_op_rate 146897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43329539 # Simulator tick rate (ticks/s) -host_mem_usage 407732 # Number of bytes of host memory used -host_seconds 621.12 # Real time elapsed on the host +host_inst_rate 116759 # Simulator instruction rate (inst/s) +host_op_rate 117598 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34685583 # Simulator tick rate (ticks/s) +host_mem_usage 427272 # Number of bytes of host memory used +host_seconds 775.87 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1681289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35211951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36893241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1681289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1681289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1681289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35211951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36893241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15514 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory +system.physmem.bytes_read::total 993152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15518 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1688503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35215988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36904491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1688503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1688503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1688503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35215988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36904491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15518 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15518 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 993152 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side +system.physmem.bytesReadSys 993152 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 988 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 987 # Per bank write bursts system.physmem.perBankRdBursts::1 886 # Per bank write bursts -system.physmem.perBankRdBursts::2 943 # Per bank write bursts +system.physmem.perBankRdBursts::2 942 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1080 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 956 # Per bank write bursts +system.physmem.perBankRdBursts::9 959 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts @@ -73,14 +73,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26912480500 # Total gap between requests +system.physmem.totGap 26911220500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15514 # Read request sizes (log2) +system.physmem.readPktSize::6 15518 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -88,9 +88,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -152,125 +152,126 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1603.423015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 482.832317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2202.245443 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 156 25.28% 25.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 69 11.18% 36.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 40 6.48% 42.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 21 3.40% 46.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 12 1.94% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 0.97% 49.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 26 4.21% 53.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 13 2.11% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.81% 56.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 9 1.46% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.65% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.65% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.81% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.30% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.49% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.49% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.49% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 19 3.08% 69.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.49% 71.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.49% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.49% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.49% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.49% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.49% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.49% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.16% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.49% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.32% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 3 0.49% 84.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.49% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.81% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.49% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 7 1.13% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.32% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.49% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.49% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.49% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.32% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1598.759289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 481.680955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2200.761860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 153 24.72% 24.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 75 12.12% 36.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 40 6.46% 43.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 20 3.23% 46.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 12 1.94% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 0.97% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 27 4.36% 53.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 12 1.94% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.81% 56.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.62% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.48% 58.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.65% 59.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.81% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.29% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.48% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 19 3.07% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.48% 71.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.81% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 6 0.97% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 617 # Bytes accessed per row activation -system.physmem.totQLat 103133500 # Total ticks spent queuing -system.physmem.totMemAccLat 356414750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers -system.physmem.totBankLat 175711250 # Total ticks spent accessing banks -system.physmem.avgQLat 6647.77 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11325.98 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 619 # Bytes accessed per row activation +system.physmem.totQLat 103760250 # Total ticks spent queuing +system.physmem.totMemAccLat 357130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77590000 # Total ticks spent in databus transfers +system.physmem.totBankLat 175780000 # Total ticks spent accessing banks +system.physmem.avgQLat 6686.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11327.49 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22973.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23013.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage @@ -278,37 +279,39 @@ system.physmem.busUtilRead 0.29 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14897 # Number of row buffer hits during reads +system.physmem.readRowHits 14899 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.01 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734722.22 # Average gap between requests -system.physmem.pageHitRate 96.02 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.95 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36893241 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 976 # Transaction distribution -system.membus.trans_dist::ReadResp 976 # Transaction distribution +system.physmem.avgGap 1734193.87 # Average gap between requests +system.physmem.pageHitRate 96.01 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36904491 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 980 # Transaction distribution +system.membus.trans_dist::ReadResp 980 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31028 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992896 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31038 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 993152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 993152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19247000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19253000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145153250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26684421 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003515 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11361703 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11279248 # Number of BTB hits +system.cpu.branchPred.lookups 26686306 # Number of BP lookups +system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11366672 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11283030 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.274273 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70578 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 175 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.264147 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70474 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 170 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -352,99 +355,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53825362 # number of cpu cycles simulated +system.cpu.numCycles 53822827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14170521 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127888749 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26684421 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11349826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24033756 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4765472 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11324127 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 14174375 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127897951 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26686306 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11353504 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24037647 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4766390 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11312706 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 108 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13841798 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 328713 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53434811 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13845393 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329438 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53431463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410222 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29439353 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3386965 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028576 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1554110 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668608 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2917595 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511603 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1091436 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9836565 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29432152 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389873 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028658 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1553769 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668148 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2920061 5.47% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1509677 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090745 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9838380 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53434811 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495759 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.375994 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16934142 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9169646 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22402191 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031199 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897633 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442994 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8719 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126071688 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42592 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897633 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18714767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3594336 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 187938 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21550636 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5489501 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123153089 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 427273 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4600360 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1278 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143605134 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536434214 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 500014017 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 784 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53431463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495818 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.376277 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937925 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9159010 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22405754 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1030805 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897969 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444268 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8691 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126081524 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42632 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897969 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18719458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3589629 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186437 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21552986 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5484984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123156725 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 425837 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4596994 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1284 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143603336 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536446832 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 500029218 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 672 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36190948 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4612 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4610 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12546346 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29477793 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5522687 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2151443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1269536 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118168344 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8478 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105154526 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78994 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26741749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65618769 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 260 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53434811 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908534 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36189150 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4635 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4633 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12540789 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29477429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5520545 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2151265 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1294097 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118170448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8500 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105167442 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79307 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26742090 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65583646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53431463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968268 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908949 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15376938 28.78% 28.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11654897 21.81% 50.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8243564 15.43% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6824643 12.77% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4966766 9.30% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2946722 5.51% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2453138 4.59% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 526074 0.98% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442069 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15374280 28.77% 28.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11649569 21.80% 50.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8250468 15.44% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6827782 12.78% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4953380 9.27% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2948609 5.52% 93.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2456731 4.60% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528512 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442132 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53434811 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53431463 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45800 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45750 6.92% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available @@ -473,13 +476,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340417 51.39% 58.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276226 41.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340320 51.44% 58.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275443 41.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74421271 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74429619 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10979 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -501,90 +504,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 129 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 165 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25608548 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5113387 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25613153 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5113394 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105154526 # Type of FU issued -system.cpu.iq.rate 1.953624 # Inst issue rate -system.cpu.iq.fu_busy_cnt 662470 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264484578 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144923147 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102682900 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 749 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 323 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105816623 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105167442 # Type of FU issued +system.cpu.iq.rate 1.953956 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661540 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264506537 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144925816 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102691564 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 657 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 923 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105828655 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441760 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6903827 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6492 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6312 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 777843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6903463 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6716 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6442 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 775701 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31495 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31606 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897633 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 959563 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126871 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118189516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310121 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29477793 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5522687 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65719 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6709 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6312 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446751 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446217 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892968 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104180481 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25289750 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 974045 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3897969 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 957023 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126637 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118191644 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310003 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29477429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5520545 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4612 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6738 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6442 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447212 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446019 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 893231 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104191675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25292948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 975767 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12694 # number of nop insts executed -system.cpu.iew.exec_refs 30346354 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325110 # Number of branches executed -system.cpu.iew.exec_stores 5056604 # Number of stores executed -system.cpu.iew.exec_rate 1.935528 # Inst execution rate -system.cpu.iew.wb_sent 102961531 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102683223 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62241416 # num instructions producing a value -system.cpu.iew.wb_consumers 104299638 # num instructions consuming a value +system.cpu.iew.exec_nop 12696 # number of nop insts executed +system.cpu.iew.exec_refs 30349771 # number of memory reference insts executed +system.cpu.iew.exec_branches 21326762 # Number of branches executed +system.cpu.iew.exec_stores 5056823 # Number of stores executed +system.cpu.iew.exec_rate 1.935827 # Inst execution rate +system.cpu.iew.wb_sent 102970942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102691851 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62249009 # num instructions producing a value +system.cpu.iew.wb_consumers 104309545 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907711 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596756 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26939491 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26941617 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834010 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49537178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540648 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834570 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49533494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842248 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20048697 40.47% 40.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13146284 26.54% 67.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4166513 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3429547 6.92% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533299 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 729419 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954733 1.93% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253168 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275518 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20042935 40.46% 40.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13146551 26.54% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4167484 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431298 6.93% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1535317 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726626 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 954928 1.93% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253259 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275096 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49537178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49533494 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -595,218 +598,222 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275518 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275096 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162448377 # The number of ROB reads -system.cpu.rob.rob_writes 240302265 # The number of ROB writes -system.cpu.timesIdled 46020 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 390551 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162447241 # The number of ROB reads +system.cpu.rob.rob_writes 240306728 # The number of ROB writes +system.cpu.timesIdled 46009 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 391364 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594166 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594166 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683032 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683032 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495553334 # number of integer regfile reads -system.cpu.int_regfile_writes 120547287 # number of integer regfile writes -system.cpu.fp_regfile_reads 170 # number of floating regfile reads -system.cpu.fp_regfile_writes 410 # number of floating regfile writes -system.cpu.misc_regfile_reads 29088502 # number of misc regfile reads +system.cpu.cpi 0.594138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594138 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683111 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683111 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495604527 # number of integer regfile reads +system.cpu.int_regfile_writes 120552200 # number of integer regfile writes +system.cpu.fp_regfile_reads 148 # number of floating regfile reads +system.cpu.fp_regfile_writes 360 # number of floating regfile writes +system.cpu.misc_regfile_reads 29090078 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4497529557 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43698 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838143 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888541000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4497665284 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942892 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43700 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1472 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120991360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121038400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121038400 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888506500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1222499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424134990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424110491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 633.195127 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13840808 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 732 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18908.207650 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 632.612747 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13844401 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 735 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18835.919728 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 633.195127 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.309177 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.309177 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13840808 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13840808 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13840808 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13840808 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13840808 # number of overall hits -system.cpu.icache.overall_hits::total 13840808 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 989 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 989 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 989 # number of overall misses -system.cpu.icache.overall_misses::total 989 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66791248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66791248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66791248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66791248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66791248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66791248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13841797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13841797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13841797 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13841797 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13841797 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13841797 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67534.123357 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67534.123357 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67534.123357 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67534.123357 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13844401 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13844401 # number of overall hits +system.cpu.icache.overall_hits::total 13844401 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 991 # number of overall misses +system.cpu.icache.overall_misses::total 991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67770748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67770748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67770748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67770748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67770748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67770748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13845392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13845392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13845392 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13845392 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13845392 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13845392 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68386.224016 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68386.224016 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 651 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 256 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 256 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 256 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 256 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50590750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50590750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50590750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50590750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50590750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50590750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51712250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51712250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51712250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51712250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51712250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51712250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69018.758527 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69018.758527 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70165.875170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70165.875170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10730.387703 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831429 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.179583 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10730.950237 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831391 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15501 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.146636 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9881.039169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 619.212620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 230.135914 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018897 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.327465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9880.493814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.630242 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 231.826182 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.301529 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018879 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327483 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903638 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903662 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903618 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903642 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942892 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942892 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29160 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29160 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 29162 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29162 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932798 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932822 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932780 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932804 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932798 # number of overall hits -system.cpu.l2cache.overall_hits::total 932822 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 987 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 932780 # number of overall hits +system.cpu.l2cache.overall_hits::total 932804 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 711 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 280 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15525 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses -system.cpu.l2cache.overall_misses::total 15525 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49612500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21119250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70731750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962947000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 962947000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 49612500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 984066250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1033678750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 49612500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 984066250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1033678750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903917 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904649 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942911 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942911 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43698 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43698 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947615 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948347 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 732 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947615 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948347 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967213 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332693 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.332693 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967213 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967213 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70074.152542 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75696.236559 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71663.373860 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66236.552483 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66236.552483 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66581.561997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66581.561997 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 711 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14818 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15529 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 711 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14818 # number of overall misses +system.cpu.l2cache.overall_misses::total 15529 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50729000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21404500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 72133500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962429750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 962429750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50729000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 983834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1034563250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50729000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 983834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1034563250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903898 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904633 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43700 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43700 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 735 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947598 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948333 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 735 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947598 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948333 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967347 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000310 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332677 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.332677 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967347 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015637 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016375 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967347 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015637 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016375 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71348.804501 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76444.642857 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72788.597376 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66200.973311 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66200.973311 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66621.369695 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66621.369695 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,176 +831,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 976 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 270 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 980 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40706750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17150500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57857250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780571000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780571000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40706750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797721500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 838428250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40706750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797721500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 838428250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332693 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332693 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57576.732673 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63756.505576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59279.969262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53691.773284 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53691.773284 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15518 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41786750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59224750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780053750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780053750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41786750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 839278500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41786750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797491750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 839278500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332677 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332677 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58854.577465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64585.185185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943519 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.753264 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28141899 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947615 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.697608 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8006034000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.753264 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896424 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23601231 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23601231 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532867 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532867 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 943502 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.733270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28144425 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947598 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.700807 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532846 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3913 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3913 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28134098 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28134098 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28134098 # number of overall hits -system.cpu.dcache.overall_hits::total 28134098 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173780 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173780 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202114 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202114 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28136618 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28136618 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28136618 # number of overall hits +system.cpu.dcache.overall_hits::total 28136618 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173981 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173981 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202135 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202135 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375894 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375894 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375894 # number of overall misses -system.cpu.dcache.overall_misses::total 1375894 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893621478 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13893621478 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458573839 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8458573839 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376116 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376116 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376116 # number of overall misses +system.cpu.dcache.overall_misses::total 1376116 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13894448479 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13894448479 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458649331 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8458649331 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22352195317 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22352195317 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22352195317 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22352195317 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24775011 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24775011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22353097810 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22353097810 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22353097810 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22353097810 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24777753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24777753 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3920 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3920 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29509992 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29509992 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29509992 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29509992 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047378 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047378 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042685 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042685 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.648672 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.648672 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41850.509312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41850.509312 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29512734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29512734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29512734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29512734 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042690 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042690 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046628 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046628 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046628 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046628 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16245.579468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16245.579468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154256 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16243.614499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16243.614499 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154190 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23957 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.440483 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.436115 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks -system.cpu.dcache.writebacks::total 942911 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269842 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269842 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158436 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158436 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks +system.cpu.dcache.writebacks::total 942892 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270066 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 270066 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428278 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428278 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428278 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428278 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903938 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903938 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43678 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43678 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994572760 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994572760 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319332173 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319332173 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313904933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11313904933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313904933 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11313904933 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.701632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.701632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30205.874193 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30205.874193 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 428516 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428516 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428516 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428516 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903915 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43685 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43685 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947600 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947600 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947600 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947600 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994483010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994483010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1318924416 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1318924416 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313407426 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11313407426 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 11900168b..a7b21f16f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1149689b6..999935db6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.065614 # Nu sim_ticks 65613727000 # Number of ticks simulated final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90206 # Simulator instruction rate (inst/s) -host_op_rate 158838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37463203 # Simulator tick rate (ticks/s) -host_mem_usage 416624 # Number of bytes of host memory used -host_seconds 1751.42 # Real time elapsed on the host +host_inst_rate 72100 # Simulator instruction rate (inst/s) +host_op_rate 126957 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29943715 # Simulator tick rate (ticks/s) +host_mem_usage 436724 # Number of bytes of host memory used +host_seconds 2191.24 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory @@ -296,9 +296,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1957440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu.branchPred.lookups 33859770 # Number of BP lookups system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted @@ -373,24 +373,24 @@ system.cpu.memDep0.insertedLoads 101555761 # Nu system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued +system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -427,12 +427,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued @@ -461,27 +461,27 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued +system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued system.cpu.iq.rate 2.288206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested +system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding @@ -491,35 +491,35 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed +system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed system.cpu.iew.exec_branches 30820824 # Number of branches executed -system.cpu.iew.exec_stores 32925944 # Number of stores executed +system.cpu.iew.exec_stores 32925943 # Number of stores executed system.cpu.iew.exec_rate 2.277516 # Inst execution rate -system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218260008 # num instructions producing a value -system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value +system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218260006 # num instructions producing a value +system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle @@ -551,8 +551,8 @@ system.cpu.commit.int_insts 278169481 # Nu system.cpu.commit.function_calls 4237596 # Number of function calls committed. system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415950983 # The number of ROB reads -system.cpu.rob.rob_writes 627545403 # The number of ROB writes +system.cpu.rob.rob_reads 415950981 # The number of ROB reads +system.cpu.rob.rob_writes 627545399 # The number of ROB writes system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated @@ -562,13 +562,13 @@ system.cpu.cpi 0.830614 # CP system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483744134 # number of integer regfile reads -system.cpu.int_regfile_writes 234595253 # number of integer regfile writes +system.cpu.int_regfile_reads 483744129 # number of integer regfile reads +system.cpu.int_regfile_writes 234595251 # number of integer regfile writes system.cpu.fp_regfile_reads 141 # number of floating regfile reads system.cpu.fp_regfile_writes 77 # number of floating regfile writes system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes -system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads +system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution @@ -611,12 +611,12 @@ system.cpu.icache.demand_misses::cpu.inst 1305 # n system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses system.cpu.icache.overall_misses::total 1305 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses @@ -629,12 +629,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -655,24 +655,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1011 system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 479 # number of replacements system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use @@ -711,17 +711,17 @@ system.cpu.l2cache.demand_misses::total 30419 # nu system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses system.cpu.l2cache.overall_misses::total 30419 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68041000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98030500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 68041000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 1974833000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 68041000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1974833000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses) @@ -746,17 +746,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014641 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -814,21 +814,21 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 2072514 # number of replacements system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits -system.cpu.dcache.overall_hits::total 71413624 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits +system.cpu.dcache.overall_hits::total 71413623 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses @@ -845,14 +845,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 01aecce27..34784c9a2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 293b4caca..3188dad03 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202724 # Number of seconds simulated -sim_ticks 202723760000 # Number of ticks simulated -final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202742 # Number of seconds simulated +sim_ticks 202741893000 # Number of ticks simulated +final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119496 # Simulator instruction rate (inst/s) -host_op_rate 134724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47946894 # Simulator tick rate (ticks/s) -host_mem_usage 278932 # Number of bytes of host memory used -host_seconds 4228.09 # Real time elapsed on the host +host_inst_rate 95210 # Simulator instruction rate (inst/s) +host_op_rate 107343 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38205910 # Simulator tick rate (ticks/s) +host_mem_usage 298452 # Number of bytes of host memory used +host_seconds 5306.56 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory -system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory -system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148203 # Number of read requests accepted -system.physmem.writeReqs 97674 # Number of write requests accepted -system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue -system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory +system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148209 # Number of read requests accepted +system.physmem.writeReqs 97655 # Number of write requests accepted +system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9589 # Per bank write bursts -system.physmem.perBankRdBursts::1 9263 # Per bank write bursts -system.physmem.perBankRdBursts::2 9230 # Per bank write bursts -system.physmem.perBankRdBursts::3 8983 # Per bank write bursts -system.physmem.perBankRdBursts::4 9781 # Per bank write bursts -system.physmem.perBankRdBursts::5 9608 # Per bank write bursts -system.physmem.perBankRdBursts::6 9123 # Per bank write bursts -system.physmem.perBankRdBursts::7 8333 # Per bank write bursts -system.physmem.perBankRdBursts::8 8801 # Per bank write bursts -system.physmem.perBankRdBursts::9 8921 # Per bank write bursts -system.physmem.perBankRdBursts::10 8939 # Per bank write bursts -system.physmem.perBankRdBursts::11 9732 # Per bank write bursts -system.physmem.perBankRdBursts::12 9670 # Per bank write bursts -system.physmem.perBankRdBursts::13 9771 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9585 # Per bank write bursts +system.physmem.perBankRdBursts::1 9243 # Per bank write bursts +system.physmem.perBankRdBursts::2 9257 # Per bank write bursts +system.physmem.perBankRdBursts::3 8972 # Per bank write bursts +system.physmem.perBankRdBursts::4 9761 # Per bank write bursts +system.physmem.perBankRdBursts::5 9639 # Per bank write bursts +system.physmem.perBankRdBursts::6 9125 # Per bank write bursts +system.physmem.perBankRdBursts::7 8321 # Per bank write bursts +system.physmem.perBankRdBursts::8 8799 # Per bank write bursts +system.physmem.perBankRdBursts::9 8911 # Per bank write bursts +system.physmem.perBankRdBursts::10 8951 # Per bank write bursts +system.physmem.perBankRdBursts::11 9736 # Per bank write bursts +system.physmem.perBankRdBursts::12 9644 # Per bank write bursts +system.physmem.perBankRdBursts::13 9766 # Per bank write bursts system.physmem.perBankRdBursts::14 8945 # Per bank write bursts -system.physmem.perBankRdBursts::15 9431 # Per bank write bursts -system.physmem.perBankWrBursts::0 6268 # Per bank write bursts -system.physmem.perBankWrBursts::1 6168 # Per bank write bursts -system.physmem.perBankWrBursts::2 6085 # Per bank write bursts -system.physmem.perBankWrBursts::3 5885 # Per bank write bursts -system.physmem.perBankWrBursts::4 6259 # Per bank write bursts -system.physmem.perBankWrBursts::5 6263 # Per bank write bursts -system.physmem.perBankWrBursts::6 6041 # Per bank write bursts -system.physmem.perBankWrBursts::7 5560 # Per bank write bursts +system.physmem.perBankRdBursts::15 9461 # Per bank write bursts +system.physmem.perBankWrBursts::0 6262 # Per bank write bursts +system.physmem.perBankWrBursts::1 6160 # Per bank write bursts +system.physmem.perBankWrBursts::2 6087 # Per bank write bursts +system.physmem.perBankWrBursts::3 5881 # Per bank write bursts +system.physmem.perBankWrBursts::4 6253 # Per bank write bursts +system.physmem.perBankWrBursts::5 6276 # Per bank write bursts +system.physmem.perBankWrBursts::6 6048 # Per bank write bursts +system.physmem.perBankWrBursts::7 5555 # Per bank write bursts system.physmem.perBankWrBursts::8 5811 # Per bank write bursts -system.physmem.perBankWrBursts::9 5905 # Per bank write bursts -system.physmem.perBankWrBursts::10 5991 # Per bank write bursts -system.physmem.perBankWrBursts::11 6522 # Per bank write bursts -system.physmem.perBankWrBursts::12 6386 # Per bank write bursts -system.physmem.perBankWrBursts::13 6332 # Per bank write bursts -system.physmem.perBankWrBursts::14 6056 # Per bank write bursts -system.physmem.perBankWrBursts::15 6134 # Per bank write bursts +system.physmem.perBankWrBursts::9 5907 # Per bank write bursts +system.physmem.perBankWrBursts::10 5994 # Per bank write bursts +system.physmem.perBankWrBursts::11 6518 # Per bank write bursts +system.physmem.perBankWrBursts::12 6370 # Per bank write bursts +system.physmem.perBankWrBursts::13 6328 # Per bank write bursts +system.physmem.perBankWrBursts::14 6055 # Per bank write bursts +system.physmem.perBankWrBursts::15 6145 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202723740000 # Total gap between requests +system.physmem.totGap 202741873000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148203 # Read request sizes (log2) +system.physmem.readPktSize::6 148209 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97674 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -127,177 +127,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation +system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation -system.physmem.totQLat 1733533250 # Total ticks spent queuing -system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks -system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation +system.physmem.totQLat 1735354000 # Total ticks spent queuing +system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks +system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing -system.physmem.readRowHits 118615 # Number of row buffer hits during reads -system.physmem.writeRowHits 57916 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes -system.physmem.avgGap 824492.49 # Average gap between requests -system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing +system.physmem.readRowHits 118629 # Number of row buffer hits during reads +system.physmem.writeRowHits 57942 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes +system.physmem.avgGap 824609.84 # Average gap between requests +system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 77623185 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46911 # Transaction distribution -system.membus.trans_dist::ReadResp 46910 # Transaction distribution -system.membus.trans_dist::Writeback 97674 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11 # Transaction distribution -system.membus.trans_dist::ReadExReq 101292 # Transaction distribution -system.membus.trans_dist::ReadExResp 101292 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15736064 # Total data (bytes) +system.membus.throughput 77612139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46927 # Transaction distribution +system.membus.trans_dist::ReadResp 46926 # Transaction distribution +system.membus.trans_dist::Writeback 97655 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101282 # Transaction distribution +system.membus.trans_dist::ReadExResp 101282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735232 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182800422 # Number of BP lookups -system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits +system.cpu.branchPred.lookups 182821881 # Number of BP lookups +system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -341,99 +339,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 405447521 # number of cpu cycles simulated +system.cpu.numCycles 405483787 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -462,15 +460,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -496,84 +494,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued -system.cpu.iq.rate 1.641040 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued +system.cpu.iq.rate 1.640858 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559155 # number of nop insts executed -system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed -system.cpu.iew.exec_branches 138495848 # Number of branches executed -system.cpu.iew.exec_stores 62487508 # Number of stores executed -system.cpu.iew.exec_rate 1.617786 # Inst execution rate -system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374730881 # num instructions producing a value -system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value +system.cpu.iew.exec_nop 1558919 # number of nop insts executed +system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed +system.cpu.iew.exec_branches 138505177 # Number of branches executed +system.cpu.iew.exec_stores 62475461 # Number of stores executed +system.cpu.iew.exec_rate 1.617619 # Inst execution rate +system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374710129 # num instructions producing a value +system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -584,225 +582,221 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104768676 # The number of ROB reads -system.cpu.rob.rob_writes 1548495185 # The number of ROB writes -system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104828701 # The number of ROB reads +system.cpu.rob.rob_writes 1548619548 # The number of ROB writes +system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads -system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads -system.cpu.int_regfile_writes 752016829 # number of integer regfile writes +system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads +system.cpu.int_regfile_writes 752019512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads +system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15073 # number of replacements -system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15017 # number of replacements +system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits -system.cpu.icache.overall_hits::total 114510320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses -system.cpu.icache.overall_misses::total 21232 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits +system.cpu.icache.overall_hits::total 114523215 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses +system.cpu.icache.overall_misses::total 21116 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4215 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4215 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4215 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4215 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4215 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4215 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17017 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17017 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17017 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17017 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17017 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17017 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 416333765 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 416333765 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 416333765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 416333765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 416333765 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 416333765 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24465.755715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24465.755715 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115458 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27089.677773 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1781255 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146702 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.141995 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102544951000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23009.492156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 363.276336 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.909282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.702194 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011086 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113431 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.826711 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13516 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804499 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 818015 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1111085 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1111085 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247576 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247576 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13516 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1052075 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065591 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13516 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1052075 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065591 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3400 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43535 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46935 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3400 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144828 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3400 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144828 # number of overall misses -system.cpu.l2cache.overall_misses::total 148228 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263796250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3483365500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3747161750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7556144249 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7556144249 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 263796250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11039509749 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11303305999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 263796250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11039509749 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11303305999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16916 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 848034 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864950 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1111085 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1111085 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16916 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196903 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213819 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16916 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196903 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213819 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200993 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051336 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054263 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119048 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119048 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290347 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290347 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200993 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.121002 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122117 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200993 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency +system.cpu.l2cache.tags.replacements 115463 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27089.747444 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1781862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146718 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.144808 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23009.564484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.930795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3719.252164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1110997 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1110997 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 57 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 57 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13491 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1051959 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065450 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13491 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1051959 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065450 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3369 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43584 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46953 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3369 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144867 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3369 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 144867 # number of overall misses +system.cpu.l2cache.overall_misses::total 148236 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260130750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3496707000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3756837750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7547454999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7547454999 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 260130750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11044161999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11304292749 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 260130750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11044161999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11304292749 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16860 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 847968 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864828 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1110997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1110997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 65 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 65 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348858 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348858 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16860 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213686 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16860 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196826 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213686 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.199822 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051398 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.054292 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.123077 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.123077 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290327 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290327 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199822 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.121043 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199822 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121043 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77213.045414 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80229.143722 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80012.730816 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74518.477918 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74518.477918 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76258.754614 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76258.754614 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -811,195 +805,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks -system.cpu.l2cache.writebacks::total 97674 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97655 # number of writebacks +system.cpu.l2cache.writebacks::total 97655 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290347 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290347 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122097 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122097 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3364 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43563 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46927 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144846 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148210 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3364 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144846 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148210 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 217499500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2949813250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3167312750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262853501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262853501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217499500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9212666751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9430166251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217499500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9212666751 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9430166251 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051373 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.123077 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.123077 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122116 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122116 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64655.023781 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67713.730689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67494.464807 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192807 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1192730 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits -system.cpu.dcache.overall_hits::total 187221113 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses -system.cpu.dcache.overall_misses::total 4954972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits +system.cpu.dcache.overall_hits::total 187223724 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses +system.cpu.dcache.overall_misses::total 4951929 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks -system.cpu.dcache.writebacks::total 1111085 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks +system.cpu.dcache.writebacks::total 1110997 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 60a82514d..6c434f44b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 09ddfe08f..d5a6aea3b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459344 # Number of seconds simulated -sim_ticks 459344378000 # Number of ticks simulated -final_tick 459344378000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.459341 # Number of seconds simulated +sim_ticks 459340600000 # Number of ticks simulated +final_tick 459340600000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78845 # Simulator instruction rate (inst/s) -host_op_rate 145792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43799497 # Simulator tick rate (ticks/s) -host_mem_usage 371908 # Number of bytes of host memory used -host_seconds 10487.44 # Real time elapsed on the host +host_inst_rate 64463 # Simulator instruction rate (inst/s) +host_op_rate 119200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35810129 # Simulator tick rate (ticks/s) +host_mem_usage 391936 # Number of bytes of host memory used +host_seconds 12827.11 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 201792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24475712 # Number of bytes read from this memory -system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 201792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 201792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18789056 # Number of bytes written to this memory -system.physmem.bytes_written::total 18789056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382433 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293579 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293579 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 439304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53284013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53723318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 439304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40904073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40904073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40904073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 439304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53284013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94627391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385586 # Number of read requests accepted -system.physmem.writeReqs 293579 # Number of write requests accepted -system.physmem.readBursts 385586 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293579 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24668096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 18787968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24677504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18789056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 203008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24478016 # Number of bytes read from this memory +system.physmem.bytes_read::total 24681024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 203008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 203008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18788608 # Number of bytes written to this memory +system.physmem.bytes_written::total 18788608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382469 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385641 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293572 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 441955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53289468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53731423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 441955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40903434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40903434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40903434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 441955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53289468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94634857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385641 # Number of read requests accepted +system.physmem.writeReqs 293572 # Number of write requests accepted +system.physmem.readBursts 385641 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293572 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24669632 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11392 # Total number of bytes read from write queue +system.physmem.bytesWritten 18788480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24681024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18788608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 178 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 137816 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24063 # Per bank write bursts -system.physmem.perBankRdBursts::1 26414 # Per bank write bursts -system.physmem.perBankRdBursts::2 24662 # Per bank write bursts -system.physmem.perBankRdBursts::3 24515 # Per bank write bursts -system.physmem.perBankRdBursts::4 23241 # Per bank write bursts -system.physmem.perBankRdBursts::5 23653 # Per bank write bursts -system.physmem.perBankRdBursts::6 24406 # Per bank write bursts -system.physmem.perBankRdBursts::7 24209 # Per bank write bursts -system.physmem.perBankRdBursts::8 23620 # Per bank write bursts -system.physmem.perBankRdBursts::9 23822 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 24074 # Per bank write bursts -system.physmem.perBankRdBursts::12 23251 # Per bank write bursts -system.physmem.perBankRdBursts::13 22944 # Per bank write bursts -system.physmem.perBankRdBursts::14 23767 # Per bank write bursts -system.physmem.perBankRdBursts::15 23995 # Per bank write bursts -system.physmem.perBankWrBursts::0 18528 # Per bank write bursts -system.physmem.perBankWrBursts::1 19811 # Per bank write bursts -system.physmem.perBankWrBursts::2 18936 # Per bank write bursts -system.physmem.perBankWrBursts::3 18914 # Per bank write bursts -system.physmem.perBankWrBursts::4 18031 # Per bank write bursts -system.physmem.perBankWrBursts::5 18401 # Per bank write bursts -system.physmem.perBankWrBursts::6 18972 # Per bank write bursts -system.physmem.perBankWrBursts::7 18946 # Per bank write bursts -system.physmem.perBankWrBursts::8 18539 # Per bank write bursts -system.physmem.perBankWrBursts::9 18111 # Per bank write bursts -system.physmem.perBankWrBursts::10 18827 # Per bank write bursts -system.physmem.perBankWrBursts::11 17725 # Per bank write bursts -system.physmem.perBankWrBursts::12 17351 # Per bank write bursts -system.physmem.perBankWrBursts::13 16948 # Per bank write bursts -system.physmem.perBankWrBursts::14 17708 # Per bank write bursts -system.physmem.perBankWrBursts::15 17814 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 135253 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24057 # Per bank write bursts +system.physmem.perBankRdBursts::1 26446 # Per bank write bursts +system.physmem.perBankRdBursts::2 24658 # Per bank write bursts +system.physmem.perBankRdBursts::3 24494 # Per bank write bursts +system.physmem.perBankRdBursts::4 23239 # Per bank write bursts +system.physmem.perBankRdBursts::5 23672 # Per bank write bursts +system.physmem.perBankRdBursts::6 24412 # Per bank write bursts +system.physmem.perBankRdBursts::7 24201 # Per bank write bursts +system.physmem.perBankRdBursts::8 23613 # Per bank write bursts +system.physmem.perBankRdBursts::9 23828 # Per bank write bursts +system.physmem.perBankRdBursts::10 24822 # Per bank write bursts +system.physmem.perBankRdBursts::11 24051 # Per bank write bursts +system.physmem.perBankRdBursts::12 23218 # Per bank write bursts +system.physmem.perBankRdBursts::13 22963 # Per bank write bursts +system.physmem.perBankRdBursts::14 23780 # Per bank write bursts +system.physmem.perBankRdBursts::15 24009 # Per bank write bursts +system.physmem.perBankWrBursts::0 18526 # Per bank write bursts +system.physmem.perBankWrBursts::1 19824 # Per bank write bursts +system.physmem.perBankWrBursts::2 18930 # Per bank write bursts +system.physmem.perBankWrBursts::3 18895 # Per bank write bursts +system.physmem.perBankWrBursts::4 18030 # Per bank write bursts +system.physmem.perBankWrBursts::5 18409 # Per bank write bursts +system.physmem.perBankWrBursts::6 18982 # Per bank write bursts +system.physmem.perBankWrBursts::7 18942 # Per bank write bursts +system.physmem.perBankWrBursts::8 18537 # Per bank write bursts +system.physmem.perBankWrBursts::9 18120 # Per bank write bursts +system.physmem.perBankWrBursts::10 18829 # Per bank write bursts +system.physmem.perBankWrBursts::11 17702 # Per bank write bursts +system.physmem.perBankWrBursts::12 17342 # Per bank write bursts +system.physmem.perBankWrBursts::13 16954 # Per bank write bursts +system.physmem.perBankWrBursts::14 17718 # Per bank write bursts +system.physmem.perBankWrBursts::15 17830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 459344352000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 459340574000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385586 # Read request sizes (log2) +system.physmem.readPktSize::6 385641 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293579 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293572 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -128,323 +128,323 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 13287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 13327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 13328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 13289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 13323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 13383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 13355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 13385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 13360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 13377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 13325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 13360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 13383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 13353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 13304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 13344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 13297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 13513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 13380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 13383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 13400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 13420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 13351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 13361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 13365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 13348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 13479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.394450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.776614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 442.926634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 63757 43.19% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 27975 18.95% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12431 8.42% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7117 4.82% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4833 3.27% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3554 2.41% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2743 1.86% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2234 1.51% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1986 1.35% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1585 1.07% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1916 1.30% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1217 0.82% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1133 0.77% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1065 0.72% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 945 0.64% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 876 0.59% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 1005 0.68% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1152 0.78% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1143 0.77% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 849 0.58% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 811 0.55% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 5222 3.54% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 320 0.22% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 205 0.14% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 175 0.12% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 129 0.09% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 96 0.07% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 103 0.07% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 90 0.06% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 59 0.04% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 49 0.03% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 46 0.03% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 39 0.03% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 37 0.03% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 41 0.03% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 25 0.02% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 33 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 21 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 11 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 24 0.02% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 23 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 26 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 13 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 15 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 22 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 19 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 16 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 15 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 21 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 9 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 16 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 10 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 11 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 14 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 17 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 17 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 11 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 7 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 9 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 7 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 6 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 12 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 24 0.02% 99.88% # Bytes accessed per row activation +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 147621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.388468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.710774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 443.499186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 63823 43.23% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 27954 18.94% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12395 8.40% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7134 4.83% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4845 3.28% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3604 2.44% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2701 1.83% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2191 1.48% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1897 1.29% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1561 1.06% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2008 1.36% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1215 0.82% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1176 0.80% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1069 0.72% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 885 0.60% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 912 0.62% 91.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1043 0.71% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1161 0.79% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1134 0.77% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 871 0.59% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 771 0.52% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 5235 3.55% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 297 0.20% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 223 0.15% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 174 0.12% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 140 0.09% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 99 0.07% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 107 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 67 0.05% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 49 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 50 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 49 0.03% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 40 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 28 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 31 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 21 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 22 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 31 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 30 0.02% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 16 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 18 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 20 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 17 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 18 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 17 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 21 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 13 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 13 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 16 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 15 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 9 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 14 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 17 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 16 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 8 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 10 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 11 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 6 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 17 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 7 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 17 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 18 0.01% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 1 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 9 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 3 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 8 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 4 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 6 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 5 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 4 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 8 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 5 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 8 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 10 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 14 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 18 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147608 # Bytes accessed per row activation -system.physmem.totQLat 3829490000 # Total ticks spent queuing -system.physmem.totMemAccLat 12088876250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1927195000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6332191250 # Total ticks spent accessing banks -system.physmem.avgQLat 9935.40 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16428.52 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7552 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147621 # Bytes accessed per row activation +system.physmem.totQLat 3824316500 # Total ticks spent queuing +system.physmem.totMemAccLat 12085472750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1927315000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6333841250 # Total ticks spent accessing banks +system.physmem.avgQLat 9921.36 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16431.77 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31363.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31353.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.72 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.73 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing -system.physmem.readRowHits 326974 # Number of row buffer hits during reads +system.physmem.avgWrQLen 9.23 # Average write queue length when enqueuing +system.physmem.readRowHits 326993 # Number of row buffer hits during reads system.physmem.writeRowHits 204419 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes -system.physmem.avgGap 676336.90 # Average gap between requests +system.physmem.avgGap 676283.54 # Average gap between requests system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 94627391 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178768 # Transaction distribution -system.membus.trans_dist::ReadResp 178768 # Transaction distribution -system.membus.trans_dist::Writeback 293579 # Transaction distribution -system.membus.trans_dist::UpgradeReq 137816 # Transaction distribution -system.membus.trans_dist::UpgradeResp 137816 # Transaction distribution -system.membus.trans_dist::ReadExReq 206818 # Transaction distribution -system.membus.trans_dist::ReadExResp 206818 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1340383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1340383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1340383 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43466560 # Total data (bytes) +system.membus.throughput 94634857 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178796 # Transaction distribution +system.membus.trans_dist::ReadResp 178796 # Transaction distribution +system.membus.trans_dist::Writeback 293572 # Transaction distribution +system.membus.trans_dist::UpgradeReq 135253 # Transaction distribution +system.membus.trans_dist::UpgradeResp 135253 # Transaction distribution +system.membus.trans_dist::ReadExReq 206845 # Transaction distribution +system.membus.trans_dist::ReadExResp 206845 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1335360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1335360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1335360 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469632 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3394511250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3391724500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3904983950 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205617659 # Number of BP lookups -system.cpu.branchPred.condPredicted 205617659 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9903777 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117094014 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114674529 # Number of BTB hits +system.membus.respLayer1.occupancy 3901051256 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.branchPred.lookups 205617807 # Number of BP lookups +system.cpu.branchPred.condPredicted 205617807 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9908418 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117215133 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114724662 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.933724 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25071350 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1805580 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.875299 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25059559 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1805276 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 918847215 # number of cpu cycles simulated +system.cpu.numCycles 918840117 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167424119 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131762166 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205617659 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139745879 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352279607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71096448 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 305445808 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47309 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248301 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162018331 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2527029 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 886385524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.375664 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167454161 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131890109 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205617807 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139784221 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352321921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71123589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 305412308 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 248697 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162055223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2523762 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 886447009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.375660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323512 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 538173800 60.72% 60.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23402088 2.64% 63.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25255439 2.85% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27875375 3.14% 69.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17753006 2.00% 71.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22920695 2.59% 73.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29402684 3.32% 77.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26636320 3.01% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174966117 19.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 538196407 60.71% 60.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23398337 2.64% 63.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25267875 2.85% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27893164 3.15% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17745237 2.00% 71.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22915160 2.59% 73.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29437572 3.32% 77.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26645476 3.01% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174947781 19.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 886385524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.223778 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.231720 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222535838 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 260614631 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295382827 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46911879 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60940349 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071401768 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60940349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256088737 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115827091 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17786 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306634612 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146876949 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035245404 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18048 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25034239 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106622478 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138089384 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150744592 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273505517 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 42043 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 886447009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223780 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.231868 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222604172 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 260544811 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295377211 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46958792 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60962023 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071584997 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60962023 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256124443 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 115849529 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18111 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306710232 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146782671 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035392094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19900 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24933273 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106586441 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138335278 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5151319538 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273897775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39701 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 524048530 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1277 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346982000 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495887036 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194435860 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195573190 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54925274 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975493038 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13839 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772240867 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 484864 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441634059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734815554 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13287 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 886385524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.999402 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.882776 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524294424 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1242 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1171 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346564705 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495938130 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194456766 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195343621 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54992684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975627132 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13244 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772183771 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484863 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441729805 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 735457697 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12692 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 886447009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.999199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.882883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 269512858 30.41% 30.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151842775 17.13% 47.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137668751 15.53% 63.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131788792 14.87% 77.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91572274 10.33% 88.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55974345 6.31% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34415050 3.88% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11842339 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1768340 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269548828 30.41% 30.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152175288 17.17% 47.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137113127 15.47% 63.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132050060 14.90% 77.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91550725 10.33% 88.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55998430 6.32% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34403840 3.88% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11839729 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1766982 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 886385524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 886447009 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4916629 32.41% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7656958 50.48% 82.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2596197 17.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4936288 32.45% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7665302 50.39% 82.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2609145 17.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2627446 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165802431 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352933 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880848 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2622898 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165798232 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 353842 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880856 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -471,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429321200 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170256004 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429305841 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170222097 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772240867 # Type of FU issued -system.cpu.iq.rate 1.928766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15169784 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008560 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4446506063 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417344315 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744979494 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15843 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 54000 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784775700 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7505 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172548732 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772183771 # Type of FU issued +system.cpu.iq.rate 1.928718 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15210735 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008583 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4446495646 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417577635 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744952561 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14503 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 50594 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3428 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784764794 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 6814 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172654482 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111785908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 387968 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 329381 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45275674 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111836934 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 389891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 330016 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45296580 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14622 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 560 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14646 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 570 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60940349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 68092505 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7152437 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975506877 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 797637 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495888065 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194435860 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3411 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4450354 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83339 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 329381 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5904947 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4426658 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10331605 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753082670 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424162697 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19158197 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60962023 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 68066484 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7196875 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975640376 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 789853 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495939091 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194456766 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3282 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4474777 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82775 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 330016 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5907886 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4422310 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10330196 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753064930 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424170565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19118841 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590975772 # number of memory reference insts executed -system.cpu.iew.exec_branches 167493044 # Number of branches executed -system.cpu.iew.exec_stores 166813075 # Number of stores executed -system.cpu.iew.exec_rate 1.907915 # Inst execution rate -system.cpu.iew.wb_sent 1749835931 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744983175 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325071563 # num instructions producing a value -system.cpu.iew.wb_consumers 1945952606 # num instructions consuming a value +system.cpu.iew.exec_refs 590955910 # number of memory reference insts executed +system.cpu.iew.exec_branches 167475793 # Number of branches executed +system.cpu.iew.exec_stores 166785345 # Number of stores executed +system.cpu.iew.exec_rate 1.907911 # Inst execution rate +system.cpu.iew.wb_sent 1749812928 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744955989 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325071537 # num instructions producing a value +system.cpu.iew.wb_consumers 1945900521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.899100 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680937 # average fanout of values written-back +system.cpu.iew.wb_rate 1.899086 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680955 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446546244 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446680078 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9931583 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 825445175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.852320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.435275 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9936737 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 825484986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.852231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435254 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 333247555 40.37% 40.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193457802 23.44% 63.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63161135 7.65% 71.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92621225 11.22% 82.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24986952 3.03% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27475927 3.33% 89.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9292263 1.13% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11354595 1.38% 91.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69847721 8.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 333347760 40.38% 40.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193315332 23.42% 63.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63291763 7.67% 71.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92551196 11.21% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24974559 3.03% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27516320 3.33% 89.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9293108 1.13% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11361813 1.38% 91.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69833135 8.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 825445175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825484986 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,228 +559,228 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69847721 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69833135 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2731132399 # The number of ROB reads -system.cpu.rob.rob_writes 4012169962 # The number of ROB writes -system.cpu.timesIdled 3361848 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32461691 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2731320630 # The number of ROB reads +system.cpu.rob.rob_writes 4012461124 # The number of ROB writes +system.cpu.timesIdled 3340699 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32393108 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.111226 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111226 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899907 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899907 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716502748 # number of integer regfile reads -system.cpu.int_regfile_writes 1420506154 # number of integer regfile writes -system.cpu.fp_regfile_reads 3672 # number of floating regfile reads -system.cpu.fp_regfile_writes 20 # number of floating regfile writes -system.cpu.cc_regfile_reads 597266892 # number of cc regfile reads -system.cpu.cc_regfile_writes 405440972 # number of cc regfile writes -system.cpu.misc_regfile_reads 964759802 # number of misc regfile reads +system.cpu.cpi 1.111217 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111217 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899914 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899914 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716389897 # number of integer regfile reads +system.cpu.int_regfile_writes 1420532102 # number of integer regfile writes +system.cpu.fp_regfile_reads 3421 # number of floating regfile reads +system.cpu.fp_regfile_writes 19 # number of floating regfile writes +system.cpu.cc_regfile_reads 597244921 # number of cc regfile reads +system.cpu.cc_regfile_writes 405448259 # number of cc regfile writes +system.cpu.misc_regfile_reads 964724023 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698195949 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1908531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1908530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330856 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 139237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 139237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7677656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7830553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 434176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311361216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311795392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311795392 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8916992 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4909747073 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 697845146 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1906044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1906043 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330771 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 136656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 136656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771758 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 150484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7672451 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7822935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 439424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311357120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311796544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311796544 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8752064 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4906973310 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 219630492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 215891495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3954804981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3953569925 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5269 # number of replacements -system.cpu.icache.tags.tagsinuse 1036.495304 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161868325 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6841 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23661.500512 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5335 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.583647 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161907582 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6916 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23410.581550 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1036.495304 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506101 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506101 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161870260 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161870260 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161870260 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161870260 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161870260 # number of overall hits -system.cpu.icache.overall_hits::total 161870260 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 148071 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 148071 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 148071 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 148071 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 148071 # number of overall misses -system.cpu.icache.overall_misses::total 148071 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 946797737 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 946797737 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 946797737 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 946797737 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 946797737 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 946797737 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162018331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162018331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162018331 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162018331 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162018331 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162018331 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6394.214512 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6394.214512 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6394.214512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6394.214512 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 466 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.583647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506633 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506633 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161909622 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161909622 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161909622 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161909622 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161909622 # number of overall hits +system.cpu.icache.overall_hits::total 161909622 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 145600 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 145600 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 145600 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 145600 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 145600 # number of overall misses +system.cpu.icache.overall_misses::total 145600 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 941474740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 941474740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 941474740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 941474740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 941474740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 941474740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162055222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162055222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162055222 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162055222 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162055222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162055222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000898 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000898 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000898 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000898 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000898 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000898 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6466.172665 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6466.172665 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6466.172665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6466.172665 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 250 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 170 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 77.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 170 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1958 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1958 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1958 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1958 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1958 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1958 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 146113 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 146113 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 146113 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 146113 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 146113 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 146113 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 564906008 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 564906008 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 564906008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 564906008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 564906008 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 564906008 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000902 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000902 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000902 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3866.226879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3866.226879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3866.226879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3866.226879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3866.226879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3866.226879 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1982 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1982 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1982 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1982 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1982 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1982 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 143618 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 143618 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 143618 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 143618 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 143618 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 143618 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 562974254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 562974254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 562974254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 562974254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 562974254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 562974254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000886 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000886 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000886 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3919.942166 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3919.942166 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352904 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29669.825336 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3696987 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385265 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.595959 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 199212130000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21123.439325 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.720045 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.665965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.253988 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905451 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590434 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2330856 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330856 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1444 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1444 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564904 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564904 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151707 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155338 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151707 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155338 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3154 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175615 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178769 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 137793 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 137793 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206841 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206841 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3154 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382456 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385610 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3154 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382456 # number of overall misses -system.cpu.l2cache.overall_misses::total 385610 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239723500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13195248212 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13434971712 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6538219 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 6538219 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15149801477 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15149801477 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239723500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28345049689 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28584773189 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239723500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28345049689 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28584773189 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6785 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762418 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2330856 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2330856 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 139237 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 139237 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6785 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2534163 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540948 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6785 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2534163 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540948 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.464849 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099644 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101045 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989629 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989629 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268017 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268017 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.464849 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150920 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151758 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.464849 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150920 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76006.182625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75137.364189 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75152.692648 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.449573 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.449573 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73243.706407 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73243.706407 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76006.182625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74113.230513 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74128.713438 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76006.182625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74113.230513 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74128.713438 # average overall miss latency +system.cpu.l2cache.tags.replacements 352959 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29669.713018 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3697218 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385325 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.595064 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 199249645000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21121.996968 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.213504 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8323.502546 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644592 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006842 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.254013 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905448 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3694 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586802 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590496 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2330771 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2330771 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1427 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564889 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564889 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3694 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151691 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2155385 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3694 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151691 # number of overall hits +system.cpu.l2cache.overall_hits::total 2155385 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178797 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 135229 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 135229 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206869 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206869 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3173 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382493 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385666 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3173 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382493 # number of overall misses +system.cpu.l2cache.overall_misses::total 385666 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 242389500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13196439955 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13438829455 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6577717 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 6577717 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15144418976 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15144418976 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 242389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28340858931 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28583248431 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 242389500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28340858931 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28583248431 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6867 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762426 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769293 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2330771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2330771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 136656 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 136656 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771758 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771758 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6867 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2534184 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2541051 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6867 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2534184 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2541051 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462065 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099649 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101056 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989558 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989558 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268049 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268049 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462065 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150933 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151774 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462065 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150933 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151774 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76391.270091 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75140.299475 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75162.499678 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48.641320 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48.641320 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73207.773886 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73207.773886 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76391.270091 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74095.104828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74113.996129 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76391.270091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74095.104828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74113.996129 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,168 +789,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293579 # number of writebacks -system.cpu.l2cache.writebacks::total 293579 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3154 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175615 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178769 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 137793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 137793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206841 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206841 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3154 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385610 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3154 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385610 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200295500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10955219212 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11155514712 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1381780092 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1381780092 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12524720523 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12524720523 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200295500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23479939735 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23680235235 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200295500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23479939735 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23680235235 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099644 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101045 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989629 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989629 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63505.231452 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62382.024383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62401.840990 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.941129 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.941129 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60552.407516 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60552.407516 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293572 # number of writebacks +system.cpu.l2cache.writebacks::total 293572 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3173 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175624 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178797 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 135229 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 135229 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206869 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206869 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382493 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385666 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382493 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385666 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 202707000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10956266955 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11158973955 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1356015260 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1356015260 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12518797024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12518797024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202707000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23475063979 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23677770979 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202707000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23475063979 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23677770979 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099649 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101056 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989558 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989558 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268049 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268049 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151774 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151774 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63884.966908 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62384.793394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62411.416047 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.547789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.547789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60515.577607 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60515.577607 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63884.966908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61373.839466 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61394.499331 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63884.966908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61373.839466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61394.499331 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2530067 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.247344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396095422 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534163 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.302267 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530088 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.247279 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 395994774 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534184 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.261256 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247279 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247349433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247349433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148232494 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148232494 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395581927 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395581927 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395581927 # number of overall hits -system.cpu.dcache.overall_hits::total 395581927 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2875523 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2875523 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 927708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 927708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3803231 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3803231 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3803231 # number of overall misses -system.cpu.dcache.overall_misses::total 3803231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57896671055 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57896671055 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26926543731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26926543731 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84823214786 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84823214786 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84823214786 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84823214786 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250224956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250224956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 247245006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247245006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148235012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148235012 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395480018 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395480018 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395480018 # number of overall hits +system.cpu.dcache.overall_hits::total 395480018 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2882280 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2882280 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 925190 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 925190 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3807470 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3807470 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3807470 # number of overall misses +system.cpu.dcache.overall_misses::total 3807470 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58083545125 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58083545125 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26852968678 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26852968678 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84936513803 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84936513803 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84936513803 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84936513803 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250127286 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250127286 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399385158 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399385158 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399385158 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399385158 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011492 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011492 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006220 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006220 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009523 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009523 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009523 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009523 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.309847 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.309847 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.804929 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.804929 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22302.935264 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22302.935264 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6209 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399287488 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399287488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399287488 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399287488 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011523 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011523 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006203 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006203 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009536 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009536 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20151.943991 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20151.943991 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.274666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.274666 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22307.861599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22307.861599 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5821 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 638 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 669 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.731975 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.701046 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330856 # number of writebacks -system.cpu.dcache.writebacks::total 2330856 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1112832 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1112832 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17000 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17000 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1129832 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1129832 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1129832 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1129832 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762691 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762691 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910708 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 910708 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2673399 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2673399 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2673399 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2673399 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862506500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862506500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24793543019 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24793543019 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55656049519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55656049519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55656049519 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55656049519 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006106 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006106 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.744584 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.744584 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27224.470433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27224.470433 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330771 # number of writebacks +system.cpu.dcache.writebacks::total 2330771 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1119584 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1119584 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17046 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17046 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1136630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1136630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1136630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1136630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762696 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762696 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 908144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 908144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2670840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2670840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2670840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2670840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862153254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862153254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24727931821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24727931821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55590085075 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55590085075 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55590085075 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55590085075 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007047 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007047 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006689 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006689 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.494519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.494519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27229.086820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27229.086820 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 14dada76e..427d7de3e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index c079ee28b..68636d517 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077516 # Nu sim_ticks 77516381000 # Number of ticks simulated final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185827 # Simulator instruction rate (inst/s) -host_op_rate 185827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38353496 # Simulator tick rate (ticks/s) -host_mem_usage 262456 # Number of bytes of host memory used -host_seconds 2021.10 # Real time elapsed on the host +host_inst_rate 154118 # Simulator instruction rate (inst/s) +host_op_rate 154118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31808931 # Simulator tick rate (ticks/s) +host_mem_usage 282024 # Number of bytes of host memory used +host_seconds 2436.94 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory @@ -210,14 +210,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation -system.physmem.totQLat 59913750 # Total ticks spent queuing -system.physmem.totMemAccLat 199861250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 59914250 # Total ticks spent queuing +system.physmem.totMemAccLat 199861750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers system.physmem.totBankLat 102712500 # Total ticks spent accessing banks -system.physmem.avgQLat 8045.35 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8045.42 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26837.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26837.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s @@ -248,15 +248,15 @@ system.membus.data_through_bus 476608 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69563000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50307165 # Number of BP lookups +system.cpu.branchPred.lookups 50307155 # Number of BP lookups system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26317362 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 26317352 # Number of BTB lookups system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.414014 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.414047 # BTB Hit Percentage system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits @@ -295,23 +295,23 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 155032764 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51194246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449183514 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50307165 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 51194259 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449183474 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50307155 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78871438 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6172162 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19742012 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 78871433 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6172161 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19742008 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 412893 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 412894 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154739151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75867710 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75867718 49.03% 49.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) @@ -319,24 +319,24 @@ system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Nu system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35290903 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35290898 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 154739151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897346 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56553427 # Number of cycles decode is idle +system.cpu.fetch.rate 2.897345 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56553436 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3941388 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4916501 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9487391 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4280 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445247205 # Number of instructions handled by decode +system.cpu.decode.UnblockCycles 3941383 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4916500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9487386 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4275 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445247195 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4916501 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59699524 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 4916500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59699528 # Number of cycles rename is idle system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running @@ -360,28 +360,28 @@ system.cpu.memDep0.conflictingLoads 8938676 # Nu system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401961013 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 974296 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 401961016 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 974295 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15321619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 15321612 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154739148 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 154739151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28425453 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28425455 18.37% 18.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25580332 16.53% 51.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25580333 16.53% 51.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21279906 13.75% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15505584 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21279905 13.75% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15505585 10.02% 91.07% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154739148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154739151 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available @@ -412,12 +412,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5077907 42.90% 74.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5077908 42.90% 74.99% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155836210 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155836212 38.77% 38.78% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued @@ -446,21 +446,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103415840 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103415841 25.73% 80.27% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401961013 # Type of FU issued +system.cpu.iq.FU_type_0::total 401961016 # Type of FU issued system.cpu.iq.rate 2.592749 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11837270 # FU busy when requested +system.cpu.iq.fu_busy_cnt 11837271 # FU busy when requested system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634505765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 634505774 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234812476 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 234812479 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241576218 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 241576222 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -473,11 +473,11 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4916501 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 4916500 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130314 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 130318 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions @@ -489,17 +489,17 @@ system.cpu.iew.predictedNotTakenIncorrect 408580 # N system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3567783 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 3567786 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 24803859 # number of nop insts executed system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed system.cpu.iew.exec_branches 46575028 # Number of branches executed system.cpu.iew.exec_stores 78467483 # Number of stores executed system.cpu.iew.exec_rate 2.569736 # Inst execution rate -system.cpu.iew.wb_sent 396861812 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396231790 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193564450 # num instructions producing a value -system.cpu.iew.wb_consumers 271143007 # num instructions consuming a value +system.cpu.iew.wb_sent 396861814 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396231793 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193564452 # num instructions producing a value +system.cpu.iew.wb_consumers 271143010 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back @@ -507,13 +507,13 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 149822651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55444792 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22572343 15.07% 52.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13039784 8.70% 60.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55444795 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22572345 15.07% 52.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13039783 8.70% 60.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle @@ -523,7 +523,7 @@ system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149822651 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,10 +536,10 @@ system.cpu.commit.int_insts 316365839 # Nu system.cpu.commit.function_calls 8007752 # Number of function calls committed. system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557859409 # The number of ROB reads +system.cpu.rob.rob_reads 557859413 # The number of ROB reads system.cpu.rob.rob_writes 871404727 # The number of ROB writes system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293616 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 293613 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated @@ -548,7 +548,7 @@ system.cpu.cpi_total 0.412788 # CP system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 398219851 # number of integer regfile reads -system.cpu.int_regfile_writes 170183529 # number of integer regfile writes +system.cpu.int_regfile_writes 170183531 # number of integer regfile writes system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads @@ -575,31 +575,31 @@ system.cpu.toL2Bus.respLayer1.occupancy 6675000 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2141 # number of replacements system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50291613 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 50291612 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12359.698452 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12359.698206 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50291613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50291613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50291613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50291613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50291613 # number of overall hits -system.cpu.icache.overall_hits::total 50291613 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5620 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5620 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5620 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5620 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5620 # number of overall misses -system.cpu.icache.overall_misses::total 5620 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 330576500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 330576500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 330576500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 330576500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 330576500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 330576500 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50291612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50291612 # number of overall hits +system.cpu.icache.overall_hits::total 50291612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses +system.cpu.icache.overall_misses::total 5621 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 330634250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 330634250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 330634250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 330634250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 330634250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 330634250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses @@ -612,12 +612,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.441281 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58821.441281 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58821.441281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.250667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58821.250667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58821.250667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58821.250667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -626,36 +626,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1551 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1551 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1551 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1551 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1551 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1551 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1552 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1552 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1552 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1552 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1552 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1552 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249127500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249127500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249127500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249127500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249127500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249127500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249126500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249126500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.731138 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.731138 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.485377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4006.698259 # Cycle average of tags in use @@ -694,17 +694,17 @@ system.cpu.l2cache.demand_misses::total 7447 # nu system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses system.cpu.l2cache.overall_misses::total 7447 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238916500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238915500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 66414500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 305331000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 305330000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 225828500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 225828500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 238916500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238915500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 292243000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 531159500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 238916500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 531158500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238915500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 292243000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 531159500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 531158500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4069 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) @@ -729,17 +729,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902557 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849349 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.954328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.902557 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.931713 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.642361 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77136.469222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.588603 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.356961 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72149.680511 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72149.680511 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71325.298778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71325.164496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71325.298778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71325.164496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index dd0636ebe..8cc45b24c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 93aa60ef6..356503ef7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068515 # Number of seconds simulated -sim_ticks 68515366500 # Number of ticks simulated -final_tick 68515366500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068510 # Number of seconds simulated +sim_ticks 68509635500 # Number of ticks simulated +final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128186 # Simulator instruction rate (inst/s) -host_op_rate 163879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32166693 # Simulator tick rate (ticks/s) -host_mem_usage 283052 # Number of bytes of host memory used -host_seconds 2130.01 # Real time elapsed on the host +host_inst_rate 105106 # Simulator instruction rate (inst/s) +host_op_rate 134373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26372946 # Simulator tick rate (ticks/s) +host_mem_usage 303620 # Number of bytes of host memory used +host_seconds 2597.72 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory -system.physmem.bytes_read::total 466432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194304 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2835919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3971781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6807699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2835919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2835919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2835919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3971781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6807699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7289 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory +system.physmem.bytes_read::total 466944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7296 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7289 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466496 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466496 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -43,13 +43,13 @@ system.physmem.perBankRdBursts::0 607 # Pe system.physmem.perBankRdBursts::1 801 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 443 # Per bank write bursts -system.physmem.perBankRdBursts::5 353 # Per bank write bursts -system.physmem.perBankRdBursts::6 161 # Per bank write bursts -system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::4 444 # Per bank write bursts +system.physmem.perBankRdBursts::5 356 # Per bank write bursts +system.physmem.perBankRdBursts::6 162 # Per bank write bursts +system.physmem.perBankRdBursts::7 220 # Per bank write bursts system.physmem.perBankRdBursts::8 207 # Per bank write bursts system.physmem.perBankRdBursts::9 294 # Per bank write bursts -system.physmem.perBankRdBursts::10 325 # Per bank write bursts +system.physmem.perBankRdBursts::10 324 # Per bank write bursts system.physmem.perBankRdBursts::11 416 # Per bank write bursts system.physmem.perBankRdBursts::12 529 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts @@ -73,14 +73,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68515346000 # Total gap between requests +system.physmem.totGap 68509447000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7289 # Read request sizes (log2) +system.physmem.readPktSize::6 7296 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -88,9 +88,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -152,80 +152,80 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 365.973249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.155512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 760.469459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 520 40.91% 40.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 218 17.15% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 133 10.46% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 73 5.74% 74.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 41 3.23% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 37 2.91% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 29 2.28% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 36 2.83% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 1.18% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 25 1.97% 88.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 5 0.39% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 14 1.10% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 0.31% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 0.63% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.39% 91.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 8 0.63% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 8 0.63% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 6 0.47% 93.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 7 0.55% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.16% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 0.39% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 5 0.39% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.16% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.24% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.24% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.24% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 4 0.31% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.24% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.16% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.24% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1271 # Bytes accessed per row activation -system.physmem.totQLat 60705750 # Total ticks spent queuing -system.physmem.totMemAccLat 196384500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36445000 # Total ticks spent in databus transfers -system.physmem.totBankLat 99233750 # Total ticks spent accessing banks -system.physmem.avgQLat 8328.41 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13614.18 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation +system.physmem.totQLat 61296000 # Total ticks spent queuing +system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers +system.physmem.totBankLat 99426250 # Total ticks spent accessing banks +system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26942.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -235,37 +235,37 @@ system.physmem.avgRdQLen 0.00 # Av system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 6018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9399827.96 # Average gap between requests -system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.15 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6807699 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4464 # Transaction distribution -system.membus.trans_dist::ReadResp 4463 # Transaction distribution +system.physmem.avgGap 9390000.96 # Average gap between requests +system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6815742 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4471 # Transaction distribution +system.membus.trans_dist::ReadResp 4471 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 2825 # Transaction distribution system.membus.trans_dist::ReadExResp 2825 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14581 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466432 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466944 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8930000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67824498 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35429100 # Number of BP lookups -system.cpu.branchPred.condPredicted 21225812 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1661684 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19625450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16825398 # Number of BTB hits +system.cpu.branchPred.lookups 35425567 # Number of BP lookups +system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.732546 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6780528 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8438 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -309,100 +309,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137030734 # number of cpu cycles simulated +system.cpu.numCycles 137019272 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39012994 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 318080298 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35429100 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23605926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70957862 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6891670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21493708 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1614 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37614130 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 516506 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136684696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983709 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66359879 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6789497 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5708838 4.18% 57.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6107274 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4922167 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4085695 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3186230 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4137086 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35388030 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136684696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258549 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.321233 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45532866 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16645865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66825856 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2530463 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5149646 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7344267 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69062 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401846627 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 213953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5149646 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51082336 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1907734 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332489 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63745566 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14466925 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394259426 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1660076 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10182958 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1156 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432806895 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2333828888 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575589736 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200458039 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48240702 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36507596 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103616420 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91395607 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4296163 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5310753 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384620101 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374263749 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1212133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34826495 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 87778881 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136684696 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024883 # Number of insts issued each cycle +system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25139035 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19926957 14.58% 32.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20565636 15.05% 48.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18170176 13.29% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24039516 17.59% 78.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15735356 11.51% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814568 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3374876 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 918576 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136684696 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8700 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4687 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -421,22 +421,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46352 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7624 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 437 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190912 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4399 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241386 1.36% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9273710 52.31% 55.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7950548 44.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126477598 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175809 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued @@ -455,93 +455,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6782032 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8476848 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430270 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595622 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20869694 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7174273 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130259 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101673859 27.17% 76.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88302195 23.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374263749 # Type of FU issued -system.cpu.iq.rate 2.731239 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17728757 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047370 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654715892 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289089659 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250133425 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249437192 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130393861 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118075733 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263363212 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128629294 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11082647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued +system.cpu.iq.rate 2.731303 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8967672 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108753 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14263 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9020024 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 174668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1902 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5149646 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 272927 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384644450 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871710 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103616420 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91395607 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 342 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14263 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1301323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1672094 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370296137 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100380791 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3967612 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1561 # number of nop insts executed -system.cpu.iew.exec_refs 187597519 # number of memory reference insts executed -system.cpu.iew.exec_branches 32011770 # Number of branches executed -system.cpu.iew.exec_stores 87216728 # Number of stores executed -system.cpu.iew.exec_rate 2.702285 # Inst execution rate -system.cpu.iew.wb_sent 368879898 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368209158 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183085663 # num instructions producing a value -system.cpu.iew.wb_consumers 363859128 # num instructions consuming a value +system.cpu.iew.exec_nop 1558 # number of nop insts executed +system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed +system.cpu.iew.exec_branches 32011507 # Number of branches executed +system.cpu.iew.exec_stores 87214232 # Number of stores executed +system.cpu.iew.exec_rate 2.702398 # Inst execution rate +system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183086265 # num instructions producing a value +system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687055 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503177 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35579507 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1592984 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131535050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.653780 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659242 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34731076 26.40% 26.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28455457 21.63% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13342482 10.14% 58.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11433888 8.69% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13770355 10.47% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7412668 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3873056 2.94% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3888664 2.96% 88.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14627404 11.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131535050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -552,220 +552,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14627404 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501549691 # The number of ROB reads -system.cpu.rob.rob_writes 774443009 # The number of ROB writes -system.cpu.timesIdled 6642 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 346038 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501522594 # The number of ROB reads +system.cpu.rob.rob_writes 774405807 # The number of ROB writes +system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501877 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501877 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1770065591 # number of integer regfile reads -system.cpu.int_regfile_writes 233053939 # number of integer regfile writes -system.cpu.fp_regfile_reads 188169392 # number of floating regfile reads -system.cpu.fp_regfile_writes 132536105 # number of floating regfile writes -system.cpu.misc_regfile_reads 566956802 # number of misc regfile reads +system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads +system.cpu.int_regfile_writes 233047297 # number of integer regfile writes +system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads +system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes +system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20102702 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution +system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 42006 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1015808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1377088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1377088 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11799000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24347988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7401462 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13986 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.638823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37596770 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15875 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2368.300472 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13968 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.638823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902656 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902656 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37596770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37596770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37596770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37596770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37596770 # number of overall hits -system.cpu.icache.overall_hits::total 37596770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17358 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17358 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17358 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17358 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17358 # number of overall misses -system.cpu.icache.overall_misses::total 17358 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 450239984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 450239984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 450239984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 450239984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 450239984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 450239984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37614128 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37614128 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37614128 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37614128 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37614128 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37614128 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits +system.cpu.icache.overall_hits::total 37591948 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses +system.cpu.icache.overall_misses::total 17349 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25938.471252 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25938.471252 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25938.471252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25938.471252 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2006 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 87.217391 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 87.043478 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1481 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1481 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1481 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1481 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1481 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1481 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15877 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15877 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15877 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15877 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15877 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15877 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359424009 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359424009 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359424009 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359424009 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359424009 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359424009 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15859 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15859 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15859 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15859 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15859 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15859 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359132259 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359132259 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359132259 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359132259 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359132259 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359132259 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22638.030421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22638.030421 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22645.328142 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22645.328142 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3939.771440 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13217 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5387 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.453499 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3941.799565 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13198 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.446793 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 378.229398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.621740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 774.920301 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085041 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023649 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120232 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12824 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13123 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1037 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1037 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 379.005926 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.464306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 776.329333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011566 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.120294 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12803 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13104 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1036 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1036 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12824 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13140 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12824 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits -system.cpu.l2cache.overall_hits::total 13140 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3049 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1467 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4516 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 12803 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 318 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13121 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12803 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits +system.cpu.l2cache.overall_hits::total 13121 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3052 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4523 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2825 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2825 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3049 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4292 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7341 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3049 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses -system.cpu.l2cache.overall_misses::total 7341 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215269250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 108631000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 323900250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 199625500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 199625500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 215269250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 308256500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 523525750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 215269250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 308256500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 523525750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15873 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1766 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17639 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 3052 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4296 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7348 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3052 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4296 # number of overall misses +system.cpu.l2cache.overall_misses::total 7348 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215204250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109433000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 324637250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 200213000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 200213000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 215204250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 309646000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 524850250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 215204250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 309646000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 524850250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15855 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1772 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17627 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1036 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2842 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2842 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15873 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20481 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15873 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20481 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192087 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830691 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.256024 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15855 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4614 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20469 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4614 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20469 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192494 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830135 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.256595 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994018 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994018 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192087 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.358430 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192087 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.358430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70603.230567 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74049.761418 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71722.818866 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70663.893805 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70663.893805 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71315.318077 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71315.318077 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192494 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931079 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.358982 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192494 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931079 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.358982 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70512.532765 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74393.609789 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71774.762326 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70871.858407 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70871.858407 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71427.633370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71427.633370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -783,112 +783,112 @@ system.cpu.l2cache.demand_mshr_hits::total 52 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3037 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3040 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1431 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4471 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2825 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2825 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3037 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4252 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3037 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4252 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7289 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176465000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88132000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264597000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4256 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4256 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7296 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88886000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265256000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 429242000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176465000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252777000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 429242000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808041 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253076 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176370000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254119500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 430489500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176370000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254119500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 430489500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807562 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253645 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.355891 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.355891 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58105.037866 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61760.336370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59273.521505 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356441 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356441 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58016.447368 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62114.605171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59328.114516 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.415929 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.415929 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1414 # number of replacements -system.cpu.dcache.tags.tagsinuse 3101.535581 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170993874 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37108.045573 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1417 # number of replacements +system.cpu.dcache.tags.tagsinuse 3102.941006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170982340 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4614 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37057.290854 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3101.535581 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757211 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757211 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88940583 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88940583 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11003 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11003 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170971964 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170971964 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170971964 # number of overall hits -system.cpu.dcache.overall_hits::total 170971964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3947 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3947 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits +system.cpu.dcache.overall_hits::total 170960424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses -system.cpu.dcache.overall_misses::total 25231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 233964205 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 233964205 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1259611139 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses +system.cpu.dcache.overall_misses::total 25240 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1493575344 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1493575344 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1493575344 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1493575344 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88944530 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88944530 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11005 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11005 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170997195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170997195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170997195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170997195 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses @@ -899,52 +899,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59276.464403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59276.464403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59181.128500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59181.128500 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59196.042329 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59196.042329 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28298 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 410 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.019512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks -system.cpu.dcache.writebacks::total 1037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2179 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2179 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks +system.cpu.dcache.writebacks::total 1036 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20621 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20621 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20621 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20621 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1768 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4610 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4610 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4610 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4610 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 113556540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 113556540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 202620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 202620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316177538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 316177538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316177538 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 316177538 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -953,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64228.812217 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64228.812217 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71295.213934 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71295.213934 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 507dc65a9..3613fc19c 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 23516d587..2a6478fe5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.631518 # Nu sim_ticks 631518097500 # Number of ticks simulated final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141288 # Simulator instruction rate (inst/s) -host_op_rate 141288 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48943367 # Simulator tick rate (ticks/s) -host_mem_usage 266484 # Number of bytes of host memory used -host_seconds 12903.04 # Real time elapsed on the host +host_inst_rate 116160 # Simulator instruction rate (inst/s) +host_op_rate 116160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40238771 # Simulator tick rate (ticks/s) +host_mem_usage 286040 # Number of bytes of host memory used +host_seconds 15694.27 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory @@ -273,8 +273,8 @@ system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # By system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation -system.physmem.totQLat 2888041500 # Total ticks spent queuing -system.physmem.totMemAccLat 14116019000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2888040000 # Total ticks spent queuing +system.physmem.totMemAccLat 14116017500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst @@ -310,9 +310,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34753664 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1230653000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1230652000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4488013000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4488013500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.branchPred.lookups 388926557 # Number of BP lookups system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted @@ -339,10 +339,10 @@ system.cpu.dtb.data_hits 805300436 # DT system.cpu.dtb.data_misses 641311 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 805941747 # DTB accesses -system.cpu.itb.fetch_hits 394923337 # ITB hits +system.cpu.itb.fetch_hits 394923336 # ITB hits system.cpu.itb.fetch_misses 673 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394924010 # ITB accesses +system.cpu.itb.fetch_accesses 394924009 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -359,62 +359,62 @@ system.cpu.workload.num_syscalls 39 # Nu system.cpu.numCycles 1263036196 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410109211 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3275361916 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 410109214 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3275361918 # Number of instructions fetch has processed system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157942219 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 157942220 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394923337 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11250821 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 394923336 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11250823 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1248398019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 618119320 49.51% 49.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 618119324 49.51% 49.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41223037 3.30% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41223036 3.30% 80.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233409830 18.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233409831 18.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1248398019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438388188 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62722157 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 438388192 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62722156 # Number of cycles decode is blocked system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131631452 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 131631453 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131631452 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467678490 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27888697 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 131631453 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467678494 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27888696 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3095577928 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 3095577926 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2054701915 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3579840201 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3494452831 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 2054701913 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3579840200 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3494452830 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669732845 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 669732843 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer @@ -422,30 +422,30 @@ system.cpu.memDep0.insertedLoads 743928173 # Nu system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2623617017 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2623617019 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160251370 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2160251371 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 800506396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 800506398 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1248398015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1248398019 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 451794383 36.19% 36.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196881070 15.77% 51.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 451794387 36.19% 36.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196881068 15.77% 51.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120660417 9.67% 81.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104720930 8.39% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79314006 6.35% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120660419 9.67% 81.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104720933 8.39% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79314003 6.35% 96.50% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1248398015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1248398019 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available @@ -481,7 +481,7 @@ system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234386708 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234386709 57.14% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued @@ -514,17 +514,17 @@ system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Ty system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160251370 # Type of FU issued +system.cpu.iq.FU_type_0::total 2160251371 # Type of FU issued system.cpu.iq.rate 1.710364 # Inst issue rate system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5472576315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3336085104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990052080 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 5472576321 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3336085108 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990052081 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2119632114 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2119632115 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -537,11 +537,11 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131631452 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 131631453 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987064962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 734569 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 2987064964 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 734565 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions @@ -553,31 +553,31 @@ system.cpu.iew.predictedNotTakenIncorrect 30372 # N system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94121182 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 94121183 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 363447857 # number of nop insts executed system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed system.cpu.iew.exec_branches 277625839 # Number of branches executed system.cpu.iew.exec_stores 283075035 # Number of stores executed system.cpu.iew.exec_rate 1.635844 # Inst execution rate -system.cpu.iew.wb_sent 2066015512 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063661876 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180966909 # num instructions producing a value -system.cpu.iew.wb_consumers 1753315236 # num instructions consuming a value +system.cpu.iew.wb_sent 2066015513 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2063661877 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180966911 # num instructions producing a value +system.cpu.iew.wb_consumers 1753315239 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961121272 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 961121274 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1116766563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1116766566 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 497624739 44.56% 44.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228755329 20.48% 65.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119853189 10.73% 75.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 497624741 44.56% 44.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228755331 20.48% 65.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119853188 10.73% 75.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle @@ -587,7 +587,7 @@ system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1116766563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1116766566 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,10 +600,10 @@ system.cpu.commit.int_insts 1778941351 # Nu system.cpu.commit.function_calls 39955347 # Number of function calls committed. system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3980018807 # The number of ROB reads -system.cpu.rob.rob_writes 6071851296 # The number of ROB writes +system.cpu.rob.rob_reads 3980018812 # The number of ROB reads +system.cpu.rob.rob_writes 6071851301 # The number of ROB writes system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14638181 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14638177 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated @@ -612,7 +612,7 @@ system.cpu.cpi_total 0.692817 # CP system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads -system.cpu.int_regfile_writes 1496658984 # number of integer regfile writes +system.cpu.int_regfile_writes 1496658985 # number of integer regfile writes system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads @@ -639,54 +639,54 @@ system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # La system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu.icache.tags.replacements 8311 # number of replacements system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394910394 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 394910393 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39396.487829 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 39396.487729 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 394910394 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394910394 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394910394 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394910394 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394910394 # number of overall hits -system.cpu.icache.overall_hits::total 394910394 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 394910393 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394910393 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394910393 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394910393 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394910393 # number of overall hits +system.cpu.icache.overall_hits::total 394910393 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses system.cpu.icache.overall_misses::total 12943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 383675499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 383675499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 383675499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 383675499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 383675499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 383675499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394923337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394923337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394923337 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394923337 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394923337 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394923337 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 383664999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 383664999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 383664999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 383664999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 383664999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 383664999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394923336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394923336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394923336 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394923336 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394923336 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394923336 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29643.475160 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29643.475160 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29643.475160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29643.475160 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29642.663911 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29642.663911 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29642.663911 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29642.663911 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 707 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.307692 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.384615 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -702,24 +702,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10025 system.cpu.icache.demand_mshr_misses::total 10025 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10025 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10025 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281680749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281680749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281680749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281680749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281680749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281680749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281678249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281678249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281678249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281678249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281678249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281678249 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.830324 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.830324 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.580948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.580948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 443340 # number of replacements system.cpu.l2cache.tags.tagsinuse 32689.012035 # Cycle average of tags in use @@ -758,17 +758,17 @@ system.cpu.l2cache.demand_misses::total 476119 # nu system.cpu.l2cache.overall_misses::cpu.inst 2752 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 473367 # number of overall misses system.cpu.l2cache.overall_misses::total 476119 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198914750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198912250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29323124000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29522038750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29522036250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5227072250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5227072250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 198914750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198912250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 34550196250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34749111000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 198914750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34749108500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198912250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 34550196250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34749111000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34749108500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10025 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460252 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1470277 # number of ReadReq accesses(hits+misses) @@ -793,17 +793,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.308784 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274514 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.309008 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.308784 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72280.069041 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72279.160610 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72133.122106 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.110212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.104103 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78187.549549 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78187.549549 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72984.088012 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72984.082761 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72984.088012 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72984.082761 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -825,17 +825,17 @@ system.cpu.l2cache.demand_mshr_misses::total 476119 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 473367 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 476119 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164199250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164196250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24183867000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24348066250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24348063250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4422430250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4422430250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164199250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164196250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28606297250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28770496500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164199250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28770493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164196250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28606297250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28770496500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28770493500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278386 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278360 # mshr miss rate for ReadReq accesses @@ -847,17 +847,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.308784 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.308784 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59665.425145 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59664.335029 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.032688 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.025358 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1527796 # number of replacements system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use @@ -888,10 +888,10 @@ system.cpu.dcache.demand_misses::cpu.data 2987711 # n system.cpu.dcache.demand_misses::total 2987711 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2987711 # number of overall misses system.cpu.dcache.overall_misses::total 2987711 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391156750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77391156750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191877602 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 46191877602 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391157750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77391157750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191876602 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 46191876602 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles @@ -918,10 +918,10 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004453 system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.415618 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.415618 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.019744 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.019744 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.416137 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.416137 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.018802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.018802 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index be78ce1bf..cbb921be0 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2fb0bf01c..6310afb8f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.633885 # Number of seconds simulated -sim_ticks 633884897500 # Number of ticks simulated -final_tick 633884897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629535 # Number of seconds simulated +sim_ticks 629535413500 # Number of ticks simulated +final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87779 # Simulator instruction rate (inst/s) -host_op_rate 119542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40192628 # Simulator tick rate (ticks/s) -host_mem_usage 283676 # Number of bytes of host memory used -host_seconds 15771.17 # Real time elapsed on the host +host_inst_rate 71307 # Simulator instruction rate (inst/s) +host_op_rate 97111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32426577 # Simulator tick rate (ticks/s) +host_mem_usage 303200 # Number of bytes of host memory used +host_seconds 19414.18 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242944 # Number of bytes read from this memory -system.physmem.bytes_read::total 30398080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory +system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472546 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472539 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474963 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 244738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47710466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47955205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 244738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 244738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6673565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6673565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6673565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 244738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47710466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54628770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474970 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 246429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48039388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48285817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6719673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6719673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6719673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48039388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55005490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474963 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474970 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 474963 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30392000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.physmem.bytesWritten 4230080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30398080 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30390400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30397632 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4324 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29875 # Per bank write bursts -system.physmem.perBankRdBursts::1 29673 # Per bank write bursts -system.physmem.perBankRdBursts::2 29745 # Per bank write bursts -system.physmem.perBankRdBursts::3 29707 # Per bank write bursts -system.physmem.perBankRdBursts::4 29817 # Per bank write bursts -system.physmem.perBankRdBursts::5 29835 # Per bank write bursts -system.physmem.perBankRdBursts::6 29655 # Per bank write bursts -system.physmem.perBankRdBursts::7 29450 # Per bank write bursts -system.physmem.perBankRdBursts::8 29485 # Per bank write bursts -system.physmem.perBankRdBursts::9 29492 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4262 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29871 # Per bank write bursts +system.physmem.perBankRdBursts::1 29675 # Per bank write bursts +system.physmem.perBankRdBursts::2 29749 # Per bank write bursts +system.physmem.perBankRdBursts::3 29712 # Per bank write bursts +system.physmem.perBankRdBursts::4 29816 # Per bank write bursts +system.physmem.perBankRdBursts::5 29834 # Per bank write bursts +system.physmem.perBankRdBursts::6 29642 # Per bank write bursts +system.physmem.perBankRdBursts::7 29444 # Per bank write bursts +system.physmem.perBankRdBursts::8 29480 # Per bank write bursts +system.physmem.perBankRdBursts::9 29489 # Per bank write bursts system.physmem.perBankRdBursts::10 29547 # Per bank write bursts -system.physmem.perBankRdBursts::11 29655 # Per bank write bursts -system.physmem.perBankRdBursts::12 29700 # Per bank write bursts -system.physmem.perBankRdBursts::13 29805 # Per bank write bursts +system.physmem.perBankRdBursts::11 29649 # Per bank write bursts +system.physmem.perBankRdBursts::12 29701 # Per bank write bursts +system.physmem.perBankRdBursts::13 29813 # Per bank write bursts system.physmem.perBankRdBursts::14 29629 # Per bank write bursts -system.physmem.perBankRdBursts::15 29805 # Per bank write bursts +system.physmem.perBankRdBursts::15 29799 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4138 # Per bank write bursts system.physmem.perBankWrBursts::3 4148 # Per bank write bursts system.physmem.perBankWrBursts::4 4226 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4094 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4093 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 633884833500 # Total gap between requests +system.physmem.totGap 629535350500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474970 # Read request sizes (log2) +system.physmem.readPktSize::6 474963 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,13 +95,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -130,9 +130,9 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see @@ -144,11 +144,11 @@ system.physmem.wrQLenPdf::13 3004 # Wh system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -159,161 +159,161 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 190556 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.682403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 122.345891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 377.529861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 76623 40.21% 40.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 50018 26.25% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 37571 19.72% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 19599 10.29% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 202 0.11% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 233 0.12% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 93 0.05% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 219 0.11% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 79 0.04% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 190822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.419082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 122.160667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 377.205430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 76972 40.34% 40.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 49989 26.20% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 37639 19.72% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 19482 10.21% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 187 0.10% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 252 0.13% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 85 0.04% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 218 0.11% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 85 0.04% 96.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 59 0.03% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 225 0.12% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 74 0.04% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 178 0.09% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 61 0.03% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 176 0.09% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 47 0.02% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 188 0.10% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 71 0.04% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 186 0.10% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 71 0.04% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 3176 1.67% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 17 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 14 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 12 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 11 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 7 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 10 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 16 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 14 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 52 0.03% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 225 0.12% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 65 0.03% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 188 0.10% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 60 0.03% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 181 0.09% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 44 0.02% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 201 0.11% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 67 0.04% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 181 0.09% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 66 0.03% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 3167 1.66% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 20 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 13 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 12 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 12 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 13 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 17 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 15 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 15 0.01% 99.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 23 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 18 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 9 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 10 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 18 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 13 0.01% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 13 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 10 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 12 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 24 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 8 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 18 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 22 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 22 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 14 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 14 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 14 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 15 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 21 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 12 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 17 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 16 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 16 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 13 0.01% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 11 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 10 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 8 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 14 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 4 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 19 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 19 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 21 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 17 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 18 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 12 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 19 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 10 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 12 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 10 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 12 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 16 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 16 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 16 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 31 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 17 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 10 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 9 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 6 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 17 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 12 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 14 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 9 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 19 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 10 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 20 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 10 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 16 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 12 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 21 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 13 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 16 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 15 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 18 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 7 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 15 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 17 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 14 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 12 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 28 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 16 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 14 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 7 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 17 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 11 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 14 0.01% 99.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 16 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 14 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 19 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 17 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 16 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 3 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 13 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 6 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 7 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 7 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 10 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 14 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 20 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 16 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 19 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 10 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 13 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 9 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 17 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 8 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 17 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 7 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 9 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 9 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 13 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 11 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 14 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 12 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 12 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 34 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 69 0.04% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 58 0.03% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 15 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 31 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 73 0.04% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 59 0.03% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 4 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 6 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 59 0.03% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 190556 # Bytes accessed per row activation -system.physmem.totQLat 3723849000 # Total ticks spent queuing -system.physmem.totMemAccLat 15162897750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2374375000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9064673750 # Total ticks spent accessing banks -system.physmem.avgQLat 7841.75 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 19088.55 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation +system.physmem.totQLat 3804882250 # Total ticks spent queuing +system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks +system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31930.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.41 # Average write queue length when enqueuing -system.physmem.readRowHits 301072 # Number of row buffer hits during reads -system.physmem.writeRowHits 49342 # Number of row buffer hits during writes -system.physmem.readRowHitRate 63.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.65 # Row buffer hit rate for writes -system.physmem.avgGap 1171543.75 # Average gap between requests -system.physmem.pageHitRate 64.77 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 24.91 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54628770 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408895 # Transaction distribution -system.membus.trans_dist::ReadResp 408895 # Transaction distribution +system.physmem.avgWrQLen 6.84 # Average write queue length when enqueuing +system.physmem.readRowHits 300749 # Number of row buffer hits during reads +system.physmem.writeRowHits 49371 # Number of row buffer hits during writes +system.physmem.readRowHitRate 63.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.69 # Row buffer hit rate for writes +system.physmem.avgGap 1163520.10 # Average gap between requests +system.physmem.pageHitRate 64.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 24.30 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55005389 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408886 # Transaction distribution +system.membus.trans_dist::ReadResp 408885 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4324 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4324 # Transaction distribution -system.membus.trans_dist::ReadExReq 66075 # Transaction distribution -system.membus.trans_dist::ReadExResp 66075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024686 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024686 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628352 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34628352 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34628352 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 4262 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4262 # Transaction distribution +system.membus.trans_dist::ReadExReq 66077 # Transaction distribution +system.membus.trans_dist::ReadExResp 66077 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024547 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34627840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1216897000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4442648676 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 445875274 # Number of BP lookups -system.cpu.branchPred.condPredicted 355714891 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 31013117 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262160312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 234316871 # Number of BTB hits +system.cpu.branchPred.lookups 438247561 # Number of BP lookups +system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.379231 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52540791 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2805997 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -357,239 +357,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1267769796 # number of cpu cycles simulated +system.cpu.numCycles 1259070828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 359604051 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2297734506 # Number of instructions fetch has processed -system.cpu.fetch.Branches 445875274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 286857662 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 606667357 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 159378109 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 130943287 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11360 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 340050056 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11891209 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1225539818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.573745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.170795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 618917347 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42971146 3.51% 54.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 97897325 7.99% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 56071890 4.58% 66.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 75061628 6.12% 72.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45063261 3.68% 76.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31435951 2.57% 78.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31903606 2.60% 81.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226217664 18.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1225539818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351701 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.812423 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 410024939 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 104223819 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 567090713 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15899066 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 128301281 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 47087821 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11947 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3044373258 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 26488 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 128301281 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 445072814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37752394 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 469546 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 545867989 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 68075794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2962731385 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4402501 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 53439360 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 9 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2946792223 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14100168268 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12232464769 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 87261724 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 953652133 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20387 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17854 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 175792199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 972804227 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 491413736 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36509550 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 42116928 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2808310459 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27673 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2443543142 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13552705 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 910455744 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2345608138 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6289 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1225539818 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.993850 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.871016 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 386142313 31.51% 31.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183212489 14.95% 46.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204921233 16.72% 63.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171581285 14.00% 77.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 134431508 10.97% 88.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92278264 7.53% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37194117 3.03% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12766594 1.04% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3012015 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1225539818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 692354 0.79% 0.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24381 0.03% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55108221 62.64% 63.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32145057 36.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1110380096 45.44% 45.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223911 0.46% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502670 0.23% 46.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23408416 0.96% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 840781219 34.41% 81.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 443995061 18.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2443543142 # Type of FU issued -system.cpu.iq.rate 1.927434 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87970013 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6090822143 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3633185531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2257760958 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123326677 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 85675338 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56498576 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2467787139 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63726016 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 85165626 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued +system.cpu.iq.rate 1.934087 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341417046 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38150 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1428012 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 214418439 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 322 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 128301281 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16032166 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1560767 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2808350603 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 961806 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 972804227 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 491413736 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 17687 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1557116 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1428012 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32911757 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1861954 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34773711 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2367002070 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 794874980 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 76541072 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12471 # number of nop insts executed -system.cpu.iew.exec_refs 1219940656 # number of memory reference insts executed -system.cpu.iew.exec_branches 321608336 # Number of branches executed -system.cpu.iew.exec_stores 425065676 # Number of stores executed -system.cpu.iew.exec_rate 1.867060 # Inst execution rate -system.cpu.iew.wb_sent 2340031230 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2314259534 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1351078205 # num instructions producing a value -system.cpu.iew.wb_consumers 2527156960 # num instructions consuming a value +system.cpu.iew.exec_nop 12446 # number of nop insts executed +system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed +system.cpu.iew.exec_branches 319532182 # Number of branches executed +system.cpu.iew.exec_stores 423276586 # Number of stores executed +system.cpu.iew.exec_rate 1.874346 # Inst execution rate +system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1349155886 # num instructions producing a value +system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.825457 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534624 # average fanout of values written-back +system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 923014366 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 31001379 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1097238537 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.718256 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.389874 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 455331878 41.50% 41.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 289999556 26.43% 67.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95581485 8.71% 76.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70096070 6.39% 83.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46571745 4.24% 87.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22195585 2.02% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15856765 1.45% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11363497 1.04% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90241956 8.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1097238537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,222 +600,222 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90241956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3815328960 # The number of ROB reads -system.cpu.rob.rob_writes 5745013824 # The number of ROB writes -system.cpu.timesIdled 352945 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42229978 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3791959297 # The number of ROB reads +system.cpu.rob.rob_writes 5711929091 # The number of ROB writes +system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.915773 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.915773 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091973 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091973 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11799440532 # number of integer regfile reads -system.cpu.int_regfile_writes 2227507770 # number of integer regfile writes -system.cpu.fp_regfile_reads 68853045 # number of floating regfile reads -system.cpu.fp_regfile_writes 49554235 # number of floating regfile writes -system.cpu.misc_regfile_reads 1367872939 # number of misc regfile reads +system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads +system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads +system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes +system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads +system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes +system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 167773046 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1492868 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1492867 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4328 # Transaction distribution +system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52441 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3231415 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1539648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104532224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106071872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106071872 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 276928 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929329999 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 42995247 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2368559798 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 22373 # number of replacements -system.cpu.icache.tags.tagsinuse 1644.727747 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340012575 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24056 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14134.210800 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23332 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1644.727747 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.803090 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.803090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 340019150 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340019150 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340019150 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340019150 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340019150 # number of overall hits -system.cpu.icache.overall_hits::total 340019150 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30904 # number of overall misses -system.cpu.icache.overall_misses::total 30904 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 530577244 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 530577244 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 530577244 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 530577244 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 530577244 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 530577244 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 340050054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 340050054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 340050054 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 340050054 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 340050054 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 340050054 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17168.562128 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17168.562128 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17168.562128 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17168.562128 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1738 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 334702534 # number of overall hits +system.cpu.icache.overall_hits::total 334702534 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 32107 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 32107 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses +system.cpu.icache.overall_misses::total 32107 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 545585992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.064516 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2520 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2520 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2520 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2520 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2520 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2520 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28384 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28384 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28384 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28384 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28384 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28384 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424232750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 424232750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424232750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 424232750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424232750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 424232750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14946.193278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14946.193278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2825 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2825 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2825 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2825 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2825 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29282 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 29282 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 29282 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 29282 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 29282 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 29282 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435718750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 435718750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435718750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 435718750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435718750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 435718750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442189 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32678.484609 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1109448 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474936 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.335995 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 442179 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32678.084712 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1110777 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1308.214481 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.900676 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31321.369452 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039924 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001492 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.955852 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997268 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1057987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1079618 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96315 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96315 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6443 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6443 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1064430 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1086061 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1064430 # number of overall hits -system.cpu.l2cache.overall_hits::total 1086061 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001578 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.955470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997256 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 22592 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1058063 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1080655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96313 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96313 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22592 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1064504 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1087096 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22592 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1064504 # number of overall hits +system.cpu.l2cache.overall_hits::total 1087096 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408923 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4324 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4324 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 408912 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4262 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4262 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66077 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66077 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 472563 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 474989 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses -system.cpu.l2cache.overall_misses::total 474998 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175176750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30663807500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30838984250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756616500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4756616500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 175176750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35420424000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35595600750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 175176750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35420424000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35595600750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 24057 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1464484 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1488541 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4328 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4328 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 472563 # number of overall misses +system.cpu.l2cache.overall_misses::total 474989 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4757394750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1464549 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 96313 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 96313 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4265 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4265 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72518 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72518 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 24057 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1537002 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1561059 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24057 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1537002 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1561059 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277570 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.274714 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999076 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999076 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911153 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911153 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100844 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307463 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.304279 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100844 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307463 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.304279 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72208.058533 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75434.277498 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75415.137446 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71988.142263 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71988.142263 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74938.422372 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74938.422372 # average overall miss latency +system.cpu.l2cache.demand_accesses::cpu.inst 25018 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1537067 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1562085 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25018 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1537067 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1562085 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.096970 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.274517 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999297 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999297 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911181 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911181 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096970 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307445 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.304074 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -827,120 +827,120 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406471 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408895 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4324 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4324 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408886 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4262 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4262 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 472546 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474970 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472539 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474963 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 472546 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474970 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144597750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25603608250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25748206000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43244324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43244324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924227000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924227000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144597750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29527835250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29672433000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144597750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29527835250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29672433000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277552 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274695 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999076 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999076 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911153 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911153 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304261 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304261 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59652.537129 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62989.999902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62970.214847 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911181 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911181 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304057 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.495649 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.495649 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532905 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.387385 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 971436889 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1537001 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 632.033999 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 400661250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.387385 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999606 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999606 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 695310256 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 695310256 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276092959 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276092959 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1532970 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 971403215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 971403215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 971403215 # number of overall hits -system.cpu.dcache.overall_hits::total 971403215 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1954136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1954136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 842719 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 842719 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits +system.cpu.dcache.overall_hits::total 971375738 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 842629 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2796855 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2796855 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2796855 # number of overall misses -system.cpu.dcache.overall_misses::total 2796855 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80332980069 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80332980069 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58617620770 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58617620770 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 138950600839 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 138950600839 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 138950600839 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 138950600839 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 697264392 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 697264392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2796744 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses +system.cpu.dcache.overall_misses::total 2796744 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 974200070 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 974200070 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 974200070 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 974200070 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses @@ -951,68 +951,68 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41109.206355 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41109.206355 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69557.730121 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69557.730121 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49681.017013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49681.017013 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2430 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 892 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 86 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.392857 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.372093 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96315 # number of writebacks -system.cpu.dcache.writebacks::total 96315 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489650 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489650 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765875 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765875 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks +system.cpu.dcache.writebacks::total 96313 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1255525 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1255525 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1255525 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1255525 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464486 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464486 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76844 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76844 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541330 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541330 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541330 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541330 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42708562776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42708562776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4994223926 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4994223926 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47702786702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47702786702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47702786702 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47702786702 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002100 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29162.834452 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29162.834452 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64991.722529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64991.722529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index dd99e1fcc..d10bd65d5 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 4f4f69eed..fc01eaffa 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.043690 # Nu sim_ticks 43690025000 # Number of ticks simulated final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111109 # Simulator instruction rate (inst/s) -host_op_rate 111109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54950396 # Simulator tick rate (ticks/s) -host_mem_usage 264576 # Number of bytes of host memory used -host_seconds 795.08 # Real time elapsed on the host +host_inst_rate 91247 # Simulator instruction rate (inst/s) +host_op_rate 91247 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45127446 # Simulator tick rate (ticks/s) +host_mem_usage 283120 # Number of bytes of host memory used +host_seconds 968.15 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -327,9 +327,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218630500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218631000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1521664000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) system.cpu.branchPred.lookups 18742723 # Number of BP lookups system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted @@ -395,7 +395,7 @@ system.cpu.execution_unit.executions 44777932 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77196543 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77196544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed @@ -577,14 +577,14 @@ system.cpu.l2cache.overall_misses::total 165515 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 550125750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2043322000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2593447750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13452980750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13452980250 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 550125750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15496302750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16046428500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15496302250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16046428000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 550125750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15496302750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16046428500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15496302250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16046428000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses) @@ -612,14 +612,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.569244 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.814042 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.810222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.810222 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96948.485032 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96948.482011 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96948.485032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,14 +700,14 @@ system.cpu.dcache.demand_misses::cpu.data 1135132 # n system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses system.cpu.dcache.overall_misses::total 1135132 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5098666734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765880 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85921765880 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91020432614 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91020432614 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91020432614 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91020432614 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666234 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5098666234 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765380 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85921765380 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91020431614 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91020431614 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91020431614 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91020431614 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -724,14 +724,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.377950 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.377950 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634839 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634839 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80184.888290 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80184.887409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80184.887409 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked @@ -760,12 +760,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 204346 system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723509265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723509265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161452281 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16161452281 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161452281 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16161452281 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723508765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723508765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161451781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16161451781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161451781 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16161451781 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -776,12 +776,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.925373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.925373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 684c8c0e1..08705e6b8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 5daeaeb73..63551bce4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024874 # Number of seconds simulated -sim_ticks 24873813500 # Number of ticks simulated -final_tick 24873813500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024877 # Number of seconds simulated +sim_ticks 24876941500 # Number of ticks simulated +final_tick 24876941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165069 # Simulator instruction rate (inst/s) -host_op_rate 165069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51586823 # Simulator tick rate (ticks/s) -host_mem_usage 265596 # Number of bytes of host memory used -host_seconds 482.17 # Real time elapsed on the host +host_inst_rate 131928 # Simulator instruction rate (inst/s) +host_op_rate 131928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41235030 # Simulator tick rate (ticks/s) +host_mem_usage 285168 # Number of bytes of host memory used +host_seconds 603.30 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166299 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19683351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408201822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 427885173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19683351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19683351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 293364264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 293364264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 293364264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19683351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408201822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 721249438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166299 # Number of read requests accepted -system.physmem.writeReqs 114017 # Number of write requests accepted -system.physmem.readBursts 166299 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10643008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7296896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10643136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 490624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory +system.physmem.bytes_read::total 10645376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297216 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166334 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114019 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114019 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19722039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408199376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 427921415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19722039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19722039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 293332522 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 293332522 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 293332522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19722039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408199376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 721253937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166334 # Number of read requests accepted +system.physmem.writeReqs 114019 # Number of write requests accepted +system.physmem.readBursts 166334 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114019 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10645312 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297024 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10645376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297216 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10432 # Per bank write bursts -system.physmem.perBankRdBursts::1 10453 # Per bank write bursts +system.physmem.perBankRdBursts::0 10436 # Per bank write bursts +system.physmem.perBankRdBursts::1 10466 # Per bank write bursts system.physmem.perBankRdBursts::2 10310 # Per bank write bursts -system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::3 10058 # Per bank write bursts system.physmem.perBankRdBursts::4 10431 # Per bank write bursts -system.physmem.perBankRdBursts::5 10400 # Per bank write bursts +system.physmem.perBankRdBursts::5 10410 # Per bank write bursts system.physmem.perBankRdBursts::6 9846 # Per bank write bursts -system.physmem.perBankRdBursts::7 10320 # Per bank write bursts -system.physmem.perBankRdBursts::8 10615 # Per bank write bursts -system.physmem.perBankRdBursts::9 10642 # Per bank write bursts -system.physmem.perBankRdBursts::10 10549 # Per bank write bursts -system.physmem.perBankRdBursts::11 10234 # Per bank write bursts -system.physmem.perBankRdBursts::12 10280 # Per bank write bursts -system.physmem.perBankRdBursts::13 10614 # Per bank write bursts +system.physmem.perBankRdBursts::7 10323 # Per bank write bursts +system.physmem.perBankRdBursts::8 10612 # Per bank write bursts +system.physmem.perBankRdBursts::9 10641 # Per bank write bursts +system.physmem.perBankRdBursts::10 10552 # Per bank write bursts +system.physmem.perBankRdBursts::11 10231 # Per bank write bursts +system.physmem.perBankRdBursts::12 10282 # Per bank write bursts +system.physmem.perBankRdBursts::13 10619 # Per bank write bursts system.physmem.perBankRdBursts::14 10489 # Per bank write bursts -system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankRdBursts::15 10627 # Per bank write bursts system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7257 # Per bank write bursts -system.physmem.perBankWrBursts::2 7256 # Per bank write bursts -system.physmem.perBankWrBursts::3 6997 # Per bank write bursts +system.physmem.perBankWrBursts::1 7258 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts system.physmem.perBankWrBursts::5 7177 # Per bank write bursts -system.physmem.perBankWrBursts::6 6772 # Per bank write bursts -system.physmem.perBankWrBursts::7 7093 # Per bank write bursts -system.physmem.perBankWrBursts::8 7227 # Per bank write bursts +system.physmem.perBankWrBursts::6 6771 # Per bank write bursts +system.physmem.perBankWrBursts::7 7092 # Per bank write bursts +system.physmem.perBankWrBursts::8 7228 # Per bank write bursts system.physmem.perBankWrBursts::9 6941 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts -system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::10 7087 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts system.physmem.perBankWrBursts::12 6966 # Per bank write bursts system.physmem.perBankWrBursts::13 7287 # Per bank write bursts system.physmem.perBankWrBursts::14 7286 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24873779500 # Total gap between requests +system.physmem.totGap 24876907500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166299 # Read request sizes (log2) +system.physmem.readPktSize::6 166334 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114017 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 71536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114019 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,233 +127,232 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4811 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.243169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.634788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 670.449971 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 22509 43.19% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7813 14.99% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4251 8.16% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3108 5.96% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2227 4.27% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1678 3.22% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1376 2.64% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1167 2.24% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 816 1.57% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 658 1.26% 87.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 508 0.97% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 506 0.97% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 390 0.75% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 297 0.57% 90.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 306 0.59% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 440 0.84% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 200 0.38% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 185 0.36% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 164 0.31% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 351 0.67% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 222 0.43% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 266 0.51% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 128 0.25% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 805 1.54% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 220 0.42% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 67 0.13% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 43 0.08% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 225 0.43% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 103 0.20% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 52 0.10% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.289837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.462354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 671.053187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 22533 43.24% 43.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7819 15.00% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4221 8.10% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3179 6.10% 72.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2215 4.25% 76.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1656 3.18% 79.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1349 2.59% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1165 2.24% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 821 1.58% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 640 1.23% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 526 1.01% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 503 0.97% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 384 0.74% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 279 0.54% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 312 0.60% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 436 0.84% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 202 0.39% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 182 0.35% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 166 0.32% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 352 0.68% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 220 0.42% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 250 0.48% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 131 0.25% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 818 1.57% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 224 0.43% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 79 0.15% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 35 0.07% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 217 0.42% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 119 0.23% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 48 0.09% 98.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 84 0.16% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 57 0.11% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 36 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 83 0.16% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 65 0.12% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 27 0.05% 98.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 55 0.11% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 59 0.11% 98.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 21 0.04% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 12 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 17 0.03% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 18 0.03% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 24 0.05% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 13 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 9 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 11 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 6 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 11 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 9 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 13 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 6 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 10 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 6 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 8 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 7 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 22 0.04% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 18 0.03% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 16 0.03% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 20 0.04% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 13 0.02% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 16 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 32 0.06% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 16 0.03% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 10 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 12 0.02% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 13 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 13 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 14 0.03% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 9 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 11 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 10 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 9 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 11 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 6 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 4 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 9 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.01% 99.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 8 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 10 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 4 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation -system.physmem.totQLat 6321612000 # Total ticks spent queuing -system.physmem.totMemAccLat 8667027000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831485000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1513930000 # Total ticks spent accessing banks -system.physmem.avgQLat 38013.99 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9103.77 # Average bank access latency per DRAM burst +system.physmem.totQLat 6294270000 # Total ticks spent queuing +system.physmem.totMemAccLat 8641432500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831665000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1515497500 # Total ticks spent accessing banks +system.physmem.avgQLat 37841.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9111.23 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52117.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 427.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 293.36 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 427.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 293.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51952.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 427.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 293.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 427.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 293.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 5.63 # Data bus utilization in percentage system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.68 # Average write queue length when enqueuing -system.physmem.readRowHits 152202 # Number of row buffer hits during reads -system.physmem.writeRowHits 75997 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing +system.physmem.readRowHits 152220 # Number of row buffer hits during reads +system.physmem.writeRowHits 76017 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.65 # Row buffer hit rate for writes -system.physmem.avgGap 88734.78 # Average gap between requests +system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes +system.physmem.avgGap 88734.23 # Average gap between requests system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 12.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 721249438 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35493 # Transaction distribution -system.membus.trans_dist::ReadResp 35493 # Transaction distribution -system.membus.trans_dist::Writeback 114017 # Transaction distribution -system.membus.trans_dist::ReadExReq 130806 # Transaction distribution -system.membus.trans_dist::ReadExResp 130806 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446615 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17940224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940224 # Total data (bytes) +system.physmem.prechargeAllPercent 11.97 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 721253937 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35533 # Transaction distribution +system.membus.trans_dist::ReadResp 35533 # Transaction distribution +system.membus.trans_dist::Writeback 114019 # Transaction distribution +system.membus.trans_dist::ReadExReq 130801 # Transaction distribution +system.membus.trans_dist::ReadExResp 130801 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446687 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17942592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17942592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17942592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1242127000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242193000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1539178500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1539567000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) -system.cpu.branchPred.lookups 16532535 # Number of BP lookups -system.cpu.branchPred.condPredicted 10677865 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 412540 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11187771 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7331268 # Number of BTB hits +system.cpu.branchPred.lookups 16535475 # Number of BP lookups +system.cpu.branchPred.condPredicted 10680150 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 413128 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11281450 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7332394 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.529300 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1986493 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41581 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.995138 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986702 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41528 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22399036 # DTB read hits -system.cpu.dtb.read_misses 220951 # DTB read misses -system.cpu.dtb.read_acv 40 # DTB read access violations -system.cpu.dtb.read_accesses 22619987 # DTB read accesses -system.cpu.dtb.write_hits 15703469 # DTB write hits -system.cpu.dtb.write_misses 40937 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 15744406 # DTB write accesses -system.cpu.dtb.data_hits 38102505 # DTB hits -system.cpu.dtb.data_misses 261888 # DTB misses -system.cpu.dtb.data_acv 45 # DTB access violations -system.cpu.dtb.data_accesses 38364393 # DTB accesses -system.cpu.itb.fetch_hits 13899355 # ITB hits -system.cpu.itb.fetch_misses 34906 # ITB misses +system.cpu.dtb.read_hits 22396974 # DTB read hits +system.cpu.dtb.read_misses 220986 # DTB read misses +system.cpu.dtb.read_acv 45 # DTB read access violations +system.cpu.dtb.read_accesses 22617960 # DTB read accesses +system.cpu.dtb.write_hits 15703419 # DTB write hits +system.cpu.dtb.write_misses 41132 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15744551 # DTB write accesses +system.cpu.dtb.data_hits 38100393 # DTB hits +system.cpu.dtb.data_misses 262118 # DTB misses +system.cpu.dtb.data_acv 49 # DTB access violations +system.cpu.dtb.data_accesses 38362511 # DTB accesses +system.cpu.itb.fetch_hits 13901400 # ITB hits +system.cpu.itb.fetch_misses 35038 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13934261 # ITB accesses +system.cpu.itb.fetch_accesses 13936438 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -367,139 +366,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49747630 # number of cpu cycles simulated +system.cpu.numCycles 49753887 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15785028 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105317585 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16532535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9317761 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19533050 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1994568 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7608263 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7898 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 310217 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15785706 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105319377 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16535475 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9319096 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19535939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995771 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7614067 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 310803 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13899355 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 208294 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44693564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.356437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13901400 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208167 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44703895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.355933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120018 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25160514 56.30% 56.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1525973 3.41% 59.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1366086 3.06% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510374 3.38% 66.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4139884 9.26% 75.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1847459 4.13% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671184 1.50% 81.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1072337 2.40% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7399753 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25167956 56.30% 56.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1528006 3.42% 59.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1366750 3.06% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1512499 3.38% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4138976 9.26% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846420 4.13% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671442 1.50% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1071050 2.40% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7400796 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44693564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.332328 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.117037 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16872770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7137515 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18556178 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 782832 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344269 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743968 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 106931 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103592319 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 303311 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344269 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17342531 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4850765 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84983 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18829662 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2241354 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102344042 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 512 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2574 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2122740 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61629886 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123330813 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123015128 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 315684 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44703895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.332345 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.116807 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16874554 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7142634 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18558802 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 783225 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344680 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743647 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107085 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103596223 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302671 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344680 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17346175 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4853031 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85455 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18830704 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2243850 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102345999 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 509 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2584 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2124299 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61632193 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123331325 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123012632 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 318692 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9083005 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5522 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4827061 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23228738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16269123 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1186061 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452179 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90719899 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5267 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88414674 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10680066 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4660295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 684 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44693564 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.978242 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.110252 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9085312 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5523 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5521 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4830878 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23230757 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16269125 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1199559 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452349 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90724395 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5268 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88415459 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10689316 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4663748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 685 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44703895 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.977802 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109542 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16504766 36.93% 36.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6842289 15.31% 52.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5576642 12.48% 64.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4760179 10.65% 75.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4735432 10.60% 85.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2623142 5.87% 91.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1921443 4.30% 96.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1284900 2.87% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 444771 1.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16507369 36.93% 36.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6840922 15.30% 52.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5582133 12.49% 64.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4775843 10.68% 75.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4724672 10.57% 85.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2622986 5.87% 91.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1924028 4.30% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1282580 2.87% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443362 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44693564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44703895 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126888 6.81% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 786366 42.17% 48.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 951332 51.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126532 6.78% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 788261 42.26% 49.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 950494 50.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49347874 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43826 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49348241 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.86% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 120827 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120926 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38966 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121319 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121135 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38977 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -521,84 +520,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22848043 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15894065 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22847876 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15893880 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88414674 # Type of FU issued -system.cpu.iq.rate 1.777264 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1864586 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021089 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222880329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101013312 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86537625 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 602080 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 409925 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89978136 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301124 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1470512 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88415459 # Type of FU issued +system.cpu.iq.rate 1.777056 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1865287 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021097 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222890546 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101022608 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86533727 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603725 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414375 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294393 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89978801 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301945 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1469946 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2952100 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4699 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655746 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2954119 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4771 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18244 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655748 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2987 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 95590 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3011 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 95424 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344269 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3728175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74875 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100203568 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23228738 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16269123 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5267 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49826 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 191969 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160202 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 352171 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87579420 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22623199 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 835254 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344680 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3730457 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74850 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100207935 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 218697 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23230757 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16269125 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49823 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6563 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18244 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192844 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 159688 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 352532 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87575579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22621211 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 839880 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9478402 # number of nop insts executed -system.cpu.iew.exec_refs 38367932 # number of memory reference insts executed -system.cpu.iew.exec_branches 15082234 # Number of branches executed -system.cpu.iew.exec_stores 15744733 # Number of stores executed -system.cpu.iew.exec_rate 1.760474 # Inst execution rate -system.cpu.iew.wb_sent 87221630 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86831789 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33348400 # num instructions producing a value -system.cpu.iew.wb_consumers 43473071 # num instructions consuming a value +system.cpu.iew.exec_nop 9478272 # number of nop insts executed +system.cpu.iew.exec_refs 38366084 # number of memory reference insts executed +system.cpu.iew.exec_branches 15081989 # Number of branches executed +system.cpu.iew.exec_stores 15744873 # Number of stores executed +system.cpu.iew.exec_rate 1.760176 # Inst execution rate +system.cpu.iew.wb_sent 87218892 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86828120 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33348545 # num instructions producing a value +system.cpu.iew.wb_consumers 43472168 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.745446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767105 # average fanout of values written-back +system.cpu.iew.wb_rate 1.745152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767124 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8866636 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8870802 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 307777 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43349295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.037880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791190 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 308267 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43359215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.037414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791048 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20524240 47.35% 47.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7032147 16.22% 63.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3350548 7.73% 71.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2057076 4.75% 76.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2049777 4.73% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1169910 2.70% 83.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1109421 2.56% 86.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718391 1.66% 87.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5337785 12.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20533772 47.36% 47.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7032064 16.22% 63.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3351851 7.73% 71.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2056930 4.74% 76.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048633 4.72% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1170984 2.70% 83.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1108500 2.56% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718184 1.66% 87.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5338297 12.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43349295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43359215 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -609,212 +608,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5337785 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5338297 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133901476 # The number of ROB reads -system.cpu.rob.rob_writes 195761663 # The number of ROB writes -system.cpu.timesIdled 83653 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5054066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133915050 # The number of ROB reads +system.cpu.rob.rob_writes 195770285 # The number of ROB writes +system.cpu.timesIdled 83590 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5049992 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625035 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625035 # CPI: Total CPI of All Threads -system.cpu.ipc 1.599911 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599911 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115904116 # number of integer regfile reads -system.cpu.int_regfile_writes 57506232 # number of integer regfile writes -system.cpu.fp_regfile_reads 249599 # number of floating regfile reads -system.cpu.fp_regfile_writes 239957 # number of floating regfile writes -system.cpu.misc_regfile_reads 38110 # number of misc regfile reads +system.cpu.cpi 0.625114 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625114 # CPI: Total CPI of All Threads +system.cpu.ipc 1.599709 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599709 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115901393 # number of integer regfile reads +system.cpu.int_regfile_writes 57502981 # number of integer regfile writes +system.cpu.fp_regfile_reads 249622 # number of floating regfile reads +system.cpu.fp_regfile_writes 240154 # number of floating regfile writes +system.cpu.misc_regfile_reads 38048 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204474416 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168935 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143420 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187275 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 767312 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5992768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29959872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29959872 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204366702 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143411 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580010 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 767351 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5994880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23966080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29960960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29960960 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402997000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 403000500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141831227 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141888472 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326236500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326227248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91589 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.117780 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13792950 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93637 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.302348 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20015752250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.117780 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940487 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940487 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13792950 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13792950 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13792950 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13792950 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13792950 # number of overall hits -system.cpu.icache.overall_hits::total 13792950 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses -system.cpu.icache.overall_misses::total 106403 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2026702474 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2026702474 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2026702474 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2026702474 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2026702474 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2026702474 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13899353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13899353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13899353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13899353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13899353 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13899353 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007655 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007655 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007655 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007655 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007655 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007655 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19047.418531 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19047.418531 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19047.418531 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19047.418531 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 673 # number of cycles access was blocked +system.cpu.icache.tags.replacements 91622 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.124790 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13794941 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93670 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.271709 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20019697250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.124790 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940491 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13794941 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13794941 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13794941 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13794941 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13794941 # number of overall hits +system.cpu.icache.overall_hits::total 13794941 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106457 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106457 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106457 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106457 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106457 # number of overall misses +system.cpu.icache.overall_misses::total 106457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2019960968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2019960968 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2019960968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2019960968 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2019960968 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2019960968 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13901398 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13901398 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13901398 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13901398 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13901398 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13901398 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007658 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007658 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007658 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007658 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007658 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007658 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18974.430690 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18974.430690 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18974.430690 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18974.430690 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.866667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.187500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12765 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12765 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12765 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12765 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12765 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12765 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93638 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93638 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93638 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93638 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93638 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1554482273 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1554482273 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1554482273 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1554482273 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1554482273 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1554482273 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006737 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006737 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006737 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16600.976879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16600.976879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12786 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12786 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12786 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12786 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12786 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12786 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93671 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93671 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93671 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93671 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93671 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93671 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551735028 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1551735028 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551735028 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1551735028 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551735028 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1551735028 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006738 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006738 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006738 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16565.799746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16565.799746 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132395 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30693.596872 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159984 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164457 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.972801 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132428 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30694.665852 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159970 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164497 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.972480 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26343.566994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2104.284685 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2245.745192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803942 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064218 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.068535 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.936694 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34288 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168935 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168935 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12614 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12614 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85987 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46902 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132889 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85987 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46902 # number of overall hits -system.cpu.l2cache.overall_hits::total 132889 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7651 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27843 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35494 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130806 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130806 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7651 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158649 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166300 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7651 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158649 # number of overall misses -system.cpu.l2cache.overall_misses::total 166300 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 600341000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2116503000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2716844000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13805964000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13805964000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 600341000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15922467000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16522808000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 600341000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15922467000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16522808000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 93638 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62131 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 155769 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168935 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168935 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 93638 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 299189 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 93638 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 299189 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081708 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448134 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.227863 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912049 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912049 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081708 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771823 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.555836 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081708 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771823 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.555836 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78465.690759 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76015.623316 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76543.753874 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105545.341957 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105545.341957 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78465.690759 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100362.857629 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 99355.429946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78465.690759 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100362.857629 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 99355.429946 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 26341.005950 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2105.517354 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2248.142548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.803864 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.068608 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.936727 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 86004 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34262 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 120266 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168930 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168930 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12610 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12610 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86004 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46872 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132876 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86004 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46872 # number of overall hits +system.cpu.l2cache.overall_hits::total 132876 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7667 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27867 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35534 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130801 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130801 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7667 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158668 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166335 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7667 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158668 # number of overall misses +system.cpu.l2cache.overall_misses::total 166335 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 597389250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2119099250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2716488500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13782092500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13782092500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 597389250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15901191750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16498581000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 597389250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15901191750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16498581000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93671 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62129 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155800 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168930 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168930 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143411 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143411 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93671 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205540 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 299211 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93671 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205540 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 299211 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081850 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448535 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.228074 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912071 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912071 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081850 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771957 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555912 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081850 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771957 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555912 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77916.949263 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76043.321850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76447.585411 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105366.874106 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105366.874106 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 99188.871855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99188.871855 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -823,164 +822,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114017 # number of writebacks -system.cpu.l2cache.writebacks::total 114017 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7651 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27843 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35494 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130806 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130806 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7651 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158649 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166300 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7651 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158649 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166300 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503573000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1760000500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2263573500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12201880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12201880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503573000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13961880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14465453500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503573000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13961880500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14465453500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.227863 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912049 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912049 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555836 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555836 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65817.932296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63211.597170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63773.412408 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93282.265340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93282.265340 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114019 # number of writebacks +system.cpu.l2cache.writebacks::total 114019 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7667 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27867 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7667 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7667 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166335 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 500389250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1762290750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2262680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12178041500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12178041500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 500389250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13940332250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14440721500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 500389250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13940332250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14440721500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448535 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912071 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912071 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555912 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555912 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65265.325421 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63239.342233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63676.478865 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93103.581012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93103.581012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201455 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.008979 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34185233 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205551 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.310225 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 201444 # number of replacements +system.cpu.dcache.tags.tagsinuse 4074.011744 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34183901 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205540 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.312645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 220306250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.008979 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994631 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994631 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20611135 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20611135 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574043 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574043 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 55 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34185178 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34185178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34185178 # number of overall hits -system.cpu.dcache.overall_hits::total 34185178 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267491 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267491 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039334 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039334 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306825 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306825 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306825 # number of overall misses -system.cpu.dcache.overall_misses::total 1306825 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16297490000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16297490000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89003554001 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89003554001 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105301044001 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105301044001 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105301044001 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105301044001 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20878626 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20878626 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 4074.011744 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20609776 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20609776 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574069 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574069 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34183845 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34183845 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34183845 # number of overall hits +system.cpu.dcache.overall_hits::total 34183845 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267478 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267478 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039308 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039308 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306786 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306786 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306786 # number of overall misses +system.cpu.dcache.overall_misses::total 1306786 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16319754498 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16319754498 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88798095012 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88798095012 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105117849510 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105117849510 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105117849510 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105117849510 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20877254 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20877254 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 55 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35492003 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35492003 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35492003 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35492003 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35490631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35490631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35490631 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35490631 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036820 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036820 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036820 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036820 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60927.246150 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60927.246150 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85635.179837 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85635.179837 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80577.769786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80577.769786 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5154697 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036821 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036821 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036821 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036821 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61013.445958 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61013.445958 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85439.633883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85439.633883 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80439.987504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80439.987504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5138864 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.949822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.808684 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168935 # number of writebacks -system.cpu.dcache.writebacks::total 168935 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205357 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205357 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895917 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895917 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101274 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101274 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101274 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101274 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62134 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62134 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205551 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205551 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205551 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205551 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523454750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523454750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14076498244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14076498244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16599952994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16599952994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16599952994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168930 # number of writebacks +system.cpu.dcache.writebacks::total 168930 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205345 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205345 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101246 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101246 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101246 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101246 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62133 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62133 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143407 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143407 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205540 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205540 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205540 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205540 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2525887252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2525887252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14052510994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14052510994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16578398246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16578398246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16578398246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16578398246 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40613.106351 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40613.106351 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98150.834587 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98150.834587 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.909919 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.909919 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97990.411863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97990.411863 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index a8a1f643c..9b769867b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 1084e1661..df6074257 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026816 # Number of seconds simulated -sim_ticks 26816405500 # Number of ticks simulated -final_tick 26816405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026810 # Number of seconds simulated +sim_ticks 26810051000 # Number of ticks simulated +final_tick 26810051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109329 # Simulator instruction rate (inst/s) -host_op_rate 155152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41346943 # Simulator tick rate (ticks/s) -host_mem_usage 283460 # Number of bytes of host memory used -host_seconds 648.57 # Real time elapsed on the host +host_inst_rate 86453 # Simulator instruction rate (inst/s) +host_op_rate 122688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32687774 # Simulator tick rate (ticks/s) +host_mem_usage 303000 # Number of bytes of host memory used +host_seconds 820.19 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942848 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372096 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124107 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128770 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83939 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83939 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11128710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296193612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307322322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11128710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11128710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200328713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200328713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200328713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11128710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296193612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 507651035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128770 # Number of read requests accepted -system.physmem.writeReqs 83939 # Number of write requests accepted -system.physmem.readBursts 128770 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83939 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8241152 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 299136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory +system.physmem.bytes_read::total 8242368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 299136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 299136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4674 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128787 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11157607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296278138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307435745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11157607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11157607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200395292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200395292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200395292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11157607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296278138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 507831037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128788 # Number of read requests accepted +system.physmem.writeReqs 83947 # Number of write requests accepted +system.physmem.readBursts 128788 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83947 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8242304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8241280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372096 # Total written bytes from the system interface side +system.physmem.bytesWritten 5371392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8242432 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372608 # Total written bytes from the system interface side system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 318 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8144 # Per bank write bursts -system.physmem.perBankRdBursts::1 8386 # Per bank write bursts -system.physmem.perBankRdBursts::2 8247 # Per bank write bursts -system.physmem.perBankRdBursts::3 8164 # Per bank write bursts -system.physmem.perBankRdBursts::4 8296 # Per bank write bursts -system.physmem.perBankRdBursts::5 8451 # Per bank write bursts -system.physmem.perBankRdBursts::6 8094 # Per bank write bursts -system.physmem.perBankRdBursts::7 7961 # Per bank write bursts -system.physmem.perBankRdBursts::8 8061 # Per bank write bursts -system.physmem.perBankRdBursts::9 7610 # Per bank write bursts -system.physmem.perBankRdBursts::10 7787 # Per bank write bursts -system.physmem.perBankRdBursts::11 7813 # Per bank write bursts -system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7886 # Per bank write bursts -system.physmem.perBankRdBursts::14 7979 # Per bank write bursts -system.physmem.perBankRdBursts::15 8007 # Per bank write bursts -system.physmem.perBankWrBursts::0 5180 # Per bank write bursts -system.physmem.perBankWrBursts::1 5376 # Per bank write bursts -system.physmem.perBankWrBursts::2 5287 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8141 # Per bank write bursts +system.physmem.perBankRdBursts::1 8391 # Per bank write bursts +system.physmem.perBankRdBursts::2 8249 # Per bank write bursts +system.physmem.perBankRdBursts::3 8162 # Per bank write bursts +system.physmem.perBankRdBursts::4 8307 # Per bank write bursts +system.physmem.perBankRdBursts::5 8450 # Per bank write bursts +system.physmem.perBankRdBursts::6 8088 # Per bank write bursts +system.physmem.perBankRdBursts::7 7966 # Per bank write bursts +system.physmem.perBankRdBursts::8 8060 # Per bank write bursts +system.physmem.perBankRdBursts::9 7616 # Per bank write bursts +system.physmem.perBankRdBursts::10 7784 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7887 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 8012 # Per bank write bursts +system.physmem.perBankWrBursts::0 5178 # Per bank write bursts +system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.perBankWrBursts::2 5292 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::4 5267 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5205 # Per bank write bursts -system.physmem.perBankWrBursts::7 5049 # Per bank write bursts -system.physmem.perBankWrBursts::8 5030 # Per bank write bursts +system.physmem.perBankWrBursts::6 5206 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::8 5028 # Per bank write bursts system.physmem.perBankWrBursts::9 5090 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5144 # Per bank write bursts +system.physmem.perBankWrBursts::10 5248 # Per bank write bursts +system.physmem.perBankWrBursts::11 5142 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5223 # Per bank write bursts +system.physmem.perBankWrBursts::15 5222 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26816294000 # Total gap between requests +system.physmem.totGap 26810034000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128770 # Read request sizes (log2) +system.physmem.readPktSize::6 128788 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83939 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 72833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83947 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 72914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,31 +127,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3685 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -159,189 +159,189 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.431816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.292002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 695.442994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15095 39.87% 39.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5646 14.91% 54.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3407 9.00% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2352 6.21% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1734 4.58% 74.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1565 4.13% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1073 2.83% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 929 2.45% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 665 1.76% 85.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 565 1.49% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 384 1.01% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 558 1.47% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 286 0.76% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 361 0.95% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 176 0.46% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 218 0.58% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 133 0.35% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 117 0.31% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 270 0.71% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 104 0.27% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 418 1.10% 95.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 100 0.26% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 243 0.64% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 38 0.10% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 144 0.38% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 38 0.10% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 86 0.23% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 54 0.14% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 16 0.04% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 43 0.11% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 22 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 358.604352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.758574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 692.410978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15190 40.02% 40.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5700 15.02% 55.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3416 9.00% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2313 6.09% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1704 4.49% 74.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1539 4.05% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1108 2.92% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 903 2.38% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 681 1.79% 85.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 548 1.44% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 355 0.94% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 578 1.52% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 299 0.79% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 386 1.02% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 183 0.48% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 223 0.59% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 117 0.31% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 252 0.66% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 118 0.31% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 257 0.68% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 108 0.28% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 421 1.11% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 88 0.23% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 246 0.65% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 122 0.32% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 43 0.11% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 88 0.23% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 65 0.17% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 27 0.07% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 45 0.12% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 16 0.04% 98.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.04% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 32 0.08% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 11 0.03% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 29 0.08% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 17 0.04% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 31 0.08% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 15 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 11 0.03% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.03% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 9 0.02% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 8 0.02% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 21 0.06% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.03% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.06% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 15 0.04% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 29 0.08% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 15 0.04% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 34 0.09% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 13 0.03% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 17 0.04% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 7 0.02% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 19 0.05% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 17 0.04% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 10 0.03% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 27 0.07% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 7 0.02% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 14 0.04% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.03% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 15 0.04% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 6 0.02% 98.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 6 0.02% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.03% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 10 0.03% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 7 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 17 0.04% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 5 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 7 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 6 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 6 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 13 0.03% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.03% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 8 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 10 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 7 0.02% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.02% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.02% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 11 0.03% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 10 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 13 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 8 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 13 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 9 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 8 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 7 0.02% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 6 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 7 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 7 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 3 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 5 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 36 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37861 # Bytes accessed per row activation -system.physmem.totQLat 3024623000 # Total ticks spent queuing -system.physmem.totMemAccLat 4968016750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643840000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1299553750 # Total ticks spent accessing banks -system.physmem.avgQLat 23488.93 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10092.21 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 35 0.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37958 # Bytes accessed per row activation +system.physmem.totQLat 3020745250 # Total ticks spent queuing +system.physmem.totMemAccLat 4967419000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643930000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1302743750 # Total ticks spent accessing banks +system.physmem.avgQLat 23455.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10115.57 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38581.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.31 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38571.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.56 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.76 # Average write queue length when enqueuing -system.physmem.readRowHits 117866 # Number of row buffer hits during reads -system.physmem.writeRowHits 56971 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.73 # Average write queue length when enqueuing +system.physmem.readRowHits 117878 # Number of row buffer hits during reads +system.physmem.writeRowHits 56878 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.87 # Row buffer hit rate for writes -system.physmem.avgGap 126070.33 # Average gap between requests -system.physmem.pageHitRate 82.20 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.88 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 507651035 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26514 # Transaction distribution -system.membus.trans_dist::ReadResp 26514 # Transaction distribution -system.membus.trans_dist::Writeback 83939 # Transaction distribution -system.membus.trans_dist::UpgradeReq 318 # Transaction distribution -system.membus.trans_dist::UpgradeResp 318 # Transaction distribution -system.membus.trans_dist::ReadExReq 102256 # Transaction distribution -system.membus.trans_dist::ReadExResp 102256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342115 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13613376 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13613376 # Total data (bytes) +system.physmem.writeRowHitRate 67.75 # Row buffer hit rate for writes +system.physmem.avgGap 126025.50 # Average gap between requests +system.physmem.pageHitRate 82.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 507831037 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26531 # Transaction distribution +system.membus.trans_dist::ReadResp 26530 # Transaction distribution +system.membus.trans_dist::Writeback 83947 # Transaction distribution +system.membus.trans_dist::UpgradeReq 308 # Transaction distribution +system.membus.trans_dist::UpgradeResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 102257 # Transaction distribution +system.membus.trans_dist::ReadExResp 102257 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342138 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13614976 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13614976 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934803500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934752500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203423433 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203686693 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16622919 # Number of BP lookups -system.cpu.branchPred.condPredicted 12749857 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 605504 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10570940 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7775711 # Number of BTB hits +system.cpu.branchPred.lookups 16646392 # Number of BP lookups +system.cpu.branchPred.condPredicted 12773976 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 607235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10818826 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7781096 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.557423 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1829148 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113993 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.921815 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825486 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113411 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -385,239 +385,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53632812 # number of cpu cycles simulated +system.cpu.numCycles 53620103 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12575227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85200235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16622919 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9604859 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21200799 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2368859 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10684050 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 493 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11692200 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 184239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46197272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12555863 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85327612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16646392 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9606582 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21220606 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2386309 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10655499 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 479 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11697004 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 183631 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46184612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.586702 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333983 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25016575 54.15% 54.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138831 4.63% 58.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1968354 4.26% 63.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2045405 4.43% 67.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466932 3.18% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1376276 2.98% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 961294 2.08% 75.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1190217 2.58% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10033388 21.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24984951 54.10% 54.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138585 4.63% 58.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1966197 4.26% 62.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2046003 4.43% 67.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1469884 3.18% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1382868 2.99% 73.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958032 2.07% 75.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1189943 2.58% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10048149 21.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46197272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309939 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.588584 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14661485 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9032065 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19500717 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1369785 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1633220 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334387 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105402 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116870755 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 365005 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1633220 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16370455 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2587455 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1031873 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19111398 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5462871 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114984523 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 46184612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310451 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.591336 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14642918 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9005955 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19517473 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1369283 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1648983 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334820 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105179 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116999070 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363013 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1648983 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16350179 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2575616 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1030832 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19130431 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5448571 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115098604 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15960 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4602334 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 241 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115277175 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529754178 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476504412 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2548 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 17023 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4589680 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115425064 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 530260724 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476967295 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2691 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16144503 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20627 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20613 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12986013 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29603679 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22442541 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3905979 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4383979 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111534291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36144 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107247539 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 279427 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10792871 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25872402 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2358 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46197272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.321512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.989577 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16292392 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12970121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29626660 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22464166 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3855353 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4357218 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111639066 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36000 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107318490 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 273494 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10897204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26020912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46184612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.323685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.992080 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10946962 23.70% 23.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8090791 17.51% 41.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7422192 16.07% 57.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7125519 15.42% 72.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5414632 11.72% 84.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3916527 8.48% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842332 3.99% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 865884 1.87% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 572433 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10954733 23.72% 23.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8081116 17.50% 41.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7387326 16.00% 57.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7126917 15.43% 72.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408207 11.71% 84.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3931545 8.51% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1847862 4.00% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 871002 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 575904 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46197272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46184612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 111334 4.52% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1349070 54.73% 59.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1004381 40.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112087 4.51% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 3 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1355242 54.58% 59.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1015813 40.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56643981 52.82% 52.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91446 0.09% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 176 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28888115 26.94% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21623814 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56685703 52.82% 52.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91410 0.09% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 203 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28899327 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21641840 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107247539 # Type of FU issued -system.cpu.iq.rate 1.999663 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464786 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022982 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263436010 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122391385 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105557389 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 553 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 926 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109712054 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 271 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2181647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107318490 # Type of FU issued +system.cpu.iq.rate 2.001460 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2483145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023138 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263577666 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122600736 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105627540 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 565 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109801353 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2296571 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6409 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29938 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1886803 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2319552 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6675 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30486 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1908428 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 694 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1633220 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1092915 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45139 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111580294 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29603679 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22442541 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20224 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6335 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5295 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29938 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 394730 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181332 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 576062 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106214921 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28587238 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1032618 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1648983 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1092293 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45577 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111684840 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 295051 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29626660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22464166 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20080 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6356 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5380 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30486 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 395595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182079 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 577674 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106281813 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28597262 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1036677 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9859 # number of nop insts executed -system.cpu.iew.exec_refs 49925863 # number of memory reference insts executed -system.cpu.iew.exec_branches 14600722 # Number of branches executed -system.cpu.iew.exec_stores 21338625 # Number of stores executed -system.cpu.iew.exec_rate 1.980409 # Inst execution rate -system.cpu.iew.wb_sent 105779922 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105557547 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53302648 # num instructions producing a value -system.cpu.iew.wb_consumers 103946447 # num instructions consuming a value +system.cpu.iew.exec_nop 9774 # number of nop insts executed +system.cpu.iew.exec_refs 49953963 # number of memory reference insts executed +system.cpu.iew.exec_branches 14606559 # Number of branches executed +system.cpu.iew.exec_stores 21356701 # Number of stores executed +system.cpu.iew.exec_rate 1.982126 # Inst execution rate +system.cpu.iew.wb_sent 105847179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105627710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53336530 # num instructions producing a value +system.cpu.iew.wb_consumers 104015656 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.968152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512790 # average fanout of values written-back +system.cpu.iew.wb_rate 1.969927 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512774 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10948789 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11053294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 502113 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44564052 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.258153 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763889 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 504169 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44535629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.259594 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.766011 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15506218 34.80% 34.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11644493 26.13% 60.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3446423 7.73% 68.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2869378 6.44% 75.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1870309 4.20% 79.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1959985 4.40% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685768 1.54% 85.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 560638 1.26% 86.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6020840 13.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15484235 34.77% 34.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11649742 26.16% 60.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3457573 7.76% 68.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2865921 6.44% 75.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1843682 4.14% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1946516 4.37% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 688008 1.54% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565195 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6034757 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44564052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44535629 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,226 +628,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6020840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6034757 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150099130 # The number of ROB reads -system.cpu.rob.rob_writes 224804524 # The number of ROB writes -system.cpu.timesIdled 76985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7435540 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150161295 # The number of ROB reads +system.cpu.rob.rob_writes 225029668 # The number of ROB writes +system.cpu.timesIdled 76463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7435491 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.756376 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.756376 # CPI: Total CPI of All Threads -system.cpu.ipc 1.322094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.322094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511539854 # number of integer regfile reads -system.cpu.int_regfile_writes 103334614 # number of integer regfile writes -system.cpu.fp_regfile_reads 734 # number of floating regfile reads -system.cpu.fp_regfile_writes 630 # number of floating regfile writes -system.cpu.misc_regfile_reads 49164319 # number of misc regfile reads +system.cpu.cpi 0.756197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.756197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.322408 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.322408 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511842322 # number of integer regfile reads +system.cpu.int_regfile_writes 103400028 # number of integer regfile writes +system.cpu.fp_regfile_reads 836 # number of floating regfile reads +system.cpu.fp_regfile_writes 732 # number of floating regfile writes +system.cpu.misc_regfile_reads 49193821 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 775188755 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 88572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 88572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107050 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65806 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454775 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 520581 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2089088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18665280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20754368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20754368 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33408 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 291762996 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 770392865 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 86565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 86563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107049 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 516494 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20623232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20623232 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 31040 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290637496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 50495227 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47495730 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260303004 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260347495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 30799 # number of replacements -system.cpu.icache.tags.tagsinuse 1804.677341 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11655246 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 32836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 354.953283 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 28815 # number of replacements +system.cpu.icache.tags.tagsinuse 1808.840382 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11662045 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 30854 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377.975141 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1804.677341 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.881190 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.881190 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11655255 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11655255 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11655255 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11655255 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11655255 # number of overall hits -system.cpu.icache.overall_hits::total 11655255 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36945 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36945 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36945 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36945 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36945 # number of overall misses -system.cpu.icache.overall_misses::total 36945 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 836533724 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 836533724 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 836533724 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 836533724 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 836533724 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 836533724 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11692200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11692200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11692200 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11692200 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11692200 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11692200 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003160 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003160 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003160 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003160 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003160 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003160 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22642.677602 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22642.677602 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22642.677602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22642.677602 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 965 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1808.840382 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883223 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11662047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11662047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11662047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11662047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11662047 # number of overall hits +system.cpu.icache.overall_hits::total 11662047 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34957 # number of overall misses +system.cpu.icache.overall_misses::total 34957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 813284976 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 813284976 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 813284976 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 813284976 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 813284976 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 813284976 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11697004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11697004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11697004 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11697004 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11697004 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11697004 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002989 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002989 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002989 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002989 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002989 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002989 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23265.296679 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23265.296679 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23265.296679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23265.296679 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2987 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 129.869565 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3781 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3781 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3781 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3781 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3781 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3781 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33164 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33164 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33164 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33164 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33164 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33164 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 680570772 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 680570772 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 680570772 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 680570772 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 680570772 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 680570772 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002836 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002836 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002836 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20521.371728 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20521.371728 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3787 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3787 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3787 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3787 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3787 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3787 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31170 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31170 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31170 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31170 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31170 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31170 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 659799769 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 659799769 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 659799769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 659799769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 659799769 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 659799769 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002665 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002665 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002665 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21167.782130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21167.782130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21167.782130 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21167.782130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21167.782130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21167.782130 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95639 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29886.699201 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 90376 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126754 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.713003 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95665 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29888.812560 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 88308 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126769 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.696606 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26679.268686 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1365.813290 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1841.617225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814187 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.056202 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912070 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27962 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33496 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 61458 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129187 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129187 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 18 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 18 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4794 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4794 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27962 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38290 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 66252 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27962 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38290 # number of overall hits -system.cpu.l2cache.overall_hits::total 66252 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21912 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26592 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 318 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 318 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124168 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128848 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124168 # number of overall misses -system.cpu.l2cache.overall_misses::total 128848 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 367025250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1881179499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2248204749 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8506522000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8506522000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 367025250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10387701499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10754726749 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 367025250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10387701499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10754726749 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 32642 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 88050 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 129187 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 129187 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 336 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 336 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107050 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107050 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 32642 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162458 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 195100 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 32642 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162458 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 195100 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.143374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.302010 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.946429 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.946429 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955217 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955217 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143374 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.764308 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.660420 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143374 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.764308 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.660420 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78424.198718 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85851.565307 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84544.402414 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.896226 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.896226 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83188.487717 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83188.487717 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83468.325073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83468.325073 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 26671.340857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1372.959347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1844.512356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.813945 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041899 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.056290 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.912134 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25996 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 59472 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129111 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129111 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 13 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4792 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4792 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 25996 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 38268 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 64264 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25996 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 38268 # number of overall hits +system.cpu.l2cache.overall_hits::total 64264 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21919 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26608 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124176 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128865 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4689 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124176 # number of overall misses +system.cpu.l2cache.overall_misses::total 128865 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 367952250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1871129000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2239081250 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8515215250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8515215250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 367952250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10386344250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10754296500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 367952250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10386344250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10754296500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 30685 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 86080 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 129111 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 129111 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 321 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 321 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107049 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107049 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 30685 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162444 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 193129 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 30685 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162444 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 193129 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.152811 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395686 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.309108 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.959502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.959502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955235 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955235 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.152811 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764423 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.667248 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.152811 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.764423 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.667248 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78471.369162 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85365.618869 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84150.678367 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 74.672078 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 74.672078 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83272.687933 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83272.687933 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78471.369162 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83642.122874 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83453.975090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78471.369162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83642.122874 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83453.975090 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -856,195 +856,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83939 # number of writebacks -system.cpu.l2cache.writebacks::total 83939 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4663 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21851 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26514 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 318 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 318 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4663 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124107 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128770 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4663 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124107 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128770 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307037750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1604664499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1911702249 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3189317 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3189317 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7230852500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7230852500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307037750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8835516999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9142554749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307037750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8835516999 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9142554749 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.301124 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.946429 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.946429 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955217 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955217 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.660021 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.660021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65845.539352 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73436.661892 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72101.616090 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.298742 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.298742 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70713.234431 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70713.234431 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks +system.cpu.l2cache.writebacks::total 83947 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4674 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26531 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4674 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124114 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128788 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4674 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124114 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128788 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 308414000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1593918750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1902332750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3088307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3088307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7239546250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7239546250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 308414000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8833465000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9141879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 308414000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8833465000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9141879000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.959502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.959502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.666850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.666850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65985.023534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72924.863888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71702.263390 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.970779 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.970779 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70797.561536 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70797.561536 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.865935 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44347537 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 272.978474 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 158347 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.859504 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44362534 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162443 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.096003 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.865935 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993375 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993375 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26048299 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048299 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266707 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.859504 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26063246 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26063246 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266759 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266759 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15989 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15989 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44315006 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44315006 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44315006 # number of overall hits -system.cpu.dcache.overall_hits::total 44315006 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125034 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125034 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583194 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583194 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708228 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708228 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708228 # number of overall misses -system.cpu.dcache.overall_misses::total 1708228 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5241649212 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5241649212 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126812367989 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126812367989 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 914750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 914750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 132054017201 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 132054017201 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 132054017201 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 132054017201 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44330005 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44330005 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44330005 # number of overall hits +system.cpu.dcache.overall_hits::total 44330005 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583142 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583142 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707681 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707681 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707681 # number of overall misses +system.cpu.dcache.overall_misses::total 1707681 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5216348715 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5216348715 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126998846491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126998846491 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 132215195206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132215195206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132215195206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132215195206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26187785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26187785 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16032 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16032 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023234 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023234 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004777 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004777 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079758 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079758 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037117 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037117 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037117 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037117 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41921.790969 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41921.790969 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80099.070606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80099.070606 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22310.975610 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22310.975610 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77304.679001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77304.679001 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4730 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.028777 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 87.428571 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46037686 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46037686 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46037686 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46037686 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004756 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079756 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079756 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002682 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002682 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037093 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037093 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037093 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037093 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41885.262568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41885.262568 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80219.491676 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80219.491676 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24104.651163 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24104.651163 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77423.825179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77423.825179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3791 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1217 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 149 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.442953 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 93.615385 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129187 # number of writebacks -system.cpu.dcache.writebacks::total 129187 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69592 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69592 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475842 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475842 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55442 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55442 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107352 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107352 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162794 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162794 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162794 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162794 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2274282063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2274282063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8672803924 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8672803924 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947085987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10947085987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947085987 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10947085987 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003537 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003537 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41020.923902 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41020.923902 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80788.470862 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80788.470862 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129111 # number of writebacks +system.cpu.dcache.writebacks::total 129111 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69110 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69110 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475806 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475806 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55429 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55429 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107336 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107336 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162765 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162765 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162765 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162765 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263965562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263965562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8681187684 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8681187684 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945153246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10945153246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40844.423713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40844.423713 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80878.621190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80878.621190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 49239c031..cd7da392b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index e22bfa1d8..864d4a591 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.009838 # Nu sim_ticks 1009838214500 # Number of ticks simulated final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108402 # Simulator instruction rate (inst/s) -host_op_rate 108402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60154913 # Simulator tick rate (ticks/s) -host_mem_usage 256492 # Number of bytes of host memory used -host_seconds 16787.29 # Real time elapsed on the host +host_inst_rate 87394 # Simulator instruction rate (inst/s) +host_op_rate 87394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48496748 # Simulator tick rate (ticks/s) +host_mem_usage 275936 # Number of bytes of host memory used +host_seconds 20822.81 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -95,10 +95,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1662262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1662258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -128,27 +128,27 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45699 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45671 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45986 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47567 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47073 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see @@ -159,19 +159,19 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1862401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 102.289945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.389421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 186.671108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1500565 80.57% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201454 10.82% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59784 3.21% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29274 1.57% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16603 0.89% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10401 0.56% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7224 0.39% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6892 0.37% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4048 0.22% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1862398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 102.290110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.389553 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 186.671437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1500560 80.57% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201450 10.82% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59792 3.21% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29273 1.57% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16605 0.89% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10399 0.56% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7221 0.39% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6896 0.37% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4046 0.22% 98.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation @@ -180,10 +180,10 @@ system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # By system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1308 0.07% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 968 0.05% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1341 0.07% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 595 0.03% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1307 0.07% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 969 0.05% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1340 0.07% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 596 0.03% 99.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation @@ -283,15 +283,15 @@ system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1862401 # Bytes accessed per row activation -system.physmem.totQLat 23049370500 # Total ticks spent queuing -system.physmem.totMemAccLat 84969994250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 1862398 # Bytes accessed per row activation +system.physmem.totQLat 23048924250 # Total ticks spent queuing +system.physmem.totMemAccLat 84969451750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers -system.physmem.totBankLat 52124943750 # Total ticks spent accessing banks -system.physmem.avgQLat 11765.07 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26606.09 # Average bank access latency per DRAM burst +system.physmem.totBankLat 52124847500 # Total ticks spent accessing banks +system.physmem.avgQLat 11764.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26606.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43371.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43370.88 # Average memory access latency per DRAM burst system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s @@ -302,8 +302,8 @@ system.physmem.busUtilRead 0.97 # Da system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing -system.physmem.readRowHits 771404 # Number of row buffer hits during reads -system.physmem.writeRowHits 343365 # Number of row buffer hits during writes +system.physmem.readRowHits 771409 # Number of row buffer hits during reads +system.physmem.writeRowHits 343363 # Number of row buffer hits during writes system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes system.physmem.avgGap 339128.71 # Average gap between requests @@ -321,39 +321,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1 system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190575552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11787413500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11785228500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18365913000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326538195 # Number of BP lookups -system.cpu.branchPred.condPredicted 252572806 # Number of conditional branches predicted +system.cpu.branchPred.lookups 326538257 # Number of BP lookups +system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220428693 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135446272 # Number of BTB hits +system.cpu.branchPred.BTBLookups 220428800 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135446379 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.446752 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.446771 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444831815 # DTB read hits +system.cpu.dtb.read_hits 444831817 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449728893 # DTB read accesses +system.cpu.dtb.read_accesses 449728895 # DTB read accesses system.cpu.dtb.write_hits 160846718 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 162548022 # DTB write accesses -system.cpu.dtb.data_hits 605678533 # DTB hits +system.cpu.dtb.data_hits 605678535 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612276915 # DTB accesses -system.cpu.itb.fetch_hits 231928866 # ITB hits +system.cpu.dtb.data_accesses 612276917 # DTB accesses +system.cpu.itb.fetch_hits 231928870 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231928888 # ITB accesses +system.cpu.itb.fetch_accesses 231928892 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -370,8 +370,8 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 2019676430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172263192 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154275003 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 172263299 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154274958 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File @@ -389,12 +389,12 @@ system.cpu.execution_unit.executions 1139356886 # Nu system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742059065 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742060649 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7515569 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 447943127 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571733303 # Number of cycles cpu stages are processed. -system.cpu.activity 77.821045 # Percentage of cycles cpu is active +system.cpu.timesIdled 7515544 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 447943086 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571733344 # Number of cycles cpu stages are processed. +system.cpu.activity 77.821047 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -412,66 +412,66 @@ system.cpu.cpi_total 1.109846 # CP system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 833031471 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186644959 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.754211 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1085876245 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933800185 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.235138 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1047285366 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972391064 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.idleCycles 833031386 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186645044 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.754216 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1085876271 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933800159 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.235137 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1047285367 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972391063 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1610051905 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624525 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.idleCycles 1610051904 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409624526 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 998329603 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021346827 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.idleCycles 998329594 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021346836 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231927727 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 231927731 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269997.353900 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 269997.358556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231927727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231927727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231927727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231927727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231927727 # number of overall hits -system.cpu.icache.overall_hits::total 231927727 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231927731 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231927731 # number of overall hits +system.cpu.icache.overall_hits::total 231927731 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82717000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82717000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82717000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82717000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82717000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82717000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231928866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231928866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231928866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231928866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231928866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231928866 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82716500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82716500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82716500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82716500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82716500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82716500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231928870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231928870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231928870 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231928870 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231928870 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231928870 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.475856 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72622.475856 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72622.475856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72622.475856 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.036874 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72622.036874 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72622.036874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72622.036874 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -492,24 +492,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65136750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65136750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65136750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65136250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65136250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65136250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75828.579744 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75828.579744 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75827.997672 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75827.997672 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution @@ -529,17 +529,17 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # La system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13991720500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13991718500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.l2cache.tags.replacements 1926957 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30919.698652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30919.698369 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.578348 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 67892812750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14931.952178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 14931.951876 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.659960 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086514 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086532 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy @@ -565,17 +565,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98167461500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98231735250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71142206750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71142206750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 64273750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169309668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 169373942000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64273750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169309668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 169373942000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98166669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98230942250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71141350250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 71141350250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 64273250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 169308019250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 169372292500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 64273250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 169308019250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 169372292500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221824 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222683 # number of ReadReq accesses(hits+misses) @@ -600,17 +600,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215060 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.923166 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83367.057654 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.830055 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91056.663224 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91056.663224 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86429.034622 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86429.034622 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.341094 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83366.384636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.157104 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91055.566968 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91055.566968 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86428.192906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86428.192906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,17 +632,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53492750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83392423000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445915750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355655750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355655750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53492750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144748078750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 144801571500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53492750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144748078750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 144801571500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53491750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83391618000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445109750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355946750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355946750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144747564750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 144801056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53491750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144747564750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 144801056500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses @@ -654,21 +654,21 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62273.282887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70819.605905 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70813.375982 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.615477 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.615477 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62272.118743 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70818.922272 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70812.691999 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.987935 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.987935 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 9107351 # number of replacements system.cpu.dcache.tags.tagsinuse 4082.357931 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 593283203 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 593283202 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111447 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.114049 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 12709353000 # Cycle when the warmup percentage was hit. @@ -677,28 +677,28 @@ system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156014426 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156014426 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593283203 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593283203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593283203 # number of overall hits -system.cpu.dcache.overall_hits::total 593283203 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156014425 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593283202 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593283202 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593283202 # number of overall hits +system.cpu.dcache.overall_hits::total 593283202 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4714076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4714076 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12040962 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12040962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12040962 # number of overall misses -system.cpu.dcache.overall_misses::total 12040962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066802000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183066802000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 258282974250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 258282974250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 441349776250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 441349776250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 441349776250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 441349776250 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4714077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4714077 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12040963 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12040963 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12040963 # number of overall misses +system.cpu.dcache.overall_misses::total 12040963 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066004000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183066004000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 258278135000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 258278135000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 441344139000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 441344139000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 441344139000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 441344139000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -715,19 +715,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.019892 system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.621723 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.621723 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54789.734881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54789.734881 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36654.029491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36654.029491 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12098438 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.512809 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.512809 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54788.696706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54788.696706 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36653.558274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36653.558274 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12098433 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 422645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 422647 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625532 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625385 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -735,12 +735,12 @@ system.cpu.dcache.writebacks::writebacks 3693280 # nu system.cpu.dcache.writebacks::total 3693280 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824895 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2824895 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2929515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2929515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2929515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2929515 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824896 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2824896 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2929516 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2929516 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2929516 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2929516 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses @@ -749,14 +749,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111447 system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165960748500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 165960748500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84277565500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84277565500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250238314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 250238314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250238314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 250238314000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165959957500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 165959957500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84276720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84276720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250236677500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250236677500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250236677500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 250236677500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -765,14 +765,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22979.041273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22979.041273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.635773 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.635773 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22978.931751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22978.931751 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.188224 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.188224 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 898bd1404..3e178e75c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index fbdbcc030..29e4de429 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.685488 # Number of seconds simulated -sim_ticks 685488076000 # Number of ticks simulated -final_tick 685488076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.685387 # Number of seconds simulated +sim_ticks 685386545000 # Number of ticks simulated +final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134484 # Simulator instruction rate (inst/s) -host_op_rate 134484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53101916 # Simulator tick rate (ticks/s) -host_mem_usage 257516 # Number of bytes of host memory used -host_seconds 12908.91 # Real time elapsed on the host +host_inst_rate 111182 # Simulator instruction rate (inst/s) +host_op_rate 111182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43894428 # Simulator tick rate (ticks/s) +host_mem_usage 276060 # Number of bytes of host memory used +host_seconds 15614.43 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125793664 # Number of bytes read from this memory -system.physmem.bytes_read::total 125855616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265536 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966494 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019774 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019774 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 183509631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 183600008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95210316 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95210316 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95210316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 183509631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278810323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966494 # Number of read requests accepted -system.physmem.writeReqs 1019774 # Number of write requests accepted -system.physmem.readBursts 1966494 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019774 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125820608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35008 # Total number of bytes read from write queue -system.physmem.bytesWritten 65264256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125855616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65265536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 547 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory +system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263104 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965501 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019736 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019736 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 183534481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 183624591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95220871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95220871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95220871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 183534481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278845462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966466 # Number of read requests accepted +system.physmem.writeReqs 1019736 # Number of write requests accepted +system.physmem.readBursts 1966466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019736 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125817344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36480 # Total number of bytes read from write queue +system.physmem.bytesWritten 65263104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125853824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65263104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 570 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119024 # Per bank write bursts -system.physmem.perBankRdBursts::1 114431 # Per bank write bursts -system.physmem.perBankRdBursts::2 116551 # Per bank write bursts -system.physmem.perBankRdBursts::3 118044 # Per bank write bursts -system.physmem.perBankRdBursts::4 118169 # Per bank write bursts -system.physmem.perBankRdBursts::5 117821 # Per bank write bursts -system.physmem.perBankRdBursts::6 120193 # Per bank write bursts -system.physmem.perBankRdBursts::7 124929 # Per bank write bursts -system.physmem.perBankRdBursts::8 127563 # Per bank write bursts -system.physmem.perBankRdBursts::9 130460 # Per bank write bursts -system.physmem.perBankRdBursts::10 129120 # Per bank write bursts -system.physmem.perBankRdBursts::11 130791 # Per bank write bursts -system.physmem.perBankRdBursts::12 126621 # Per bank write bursts -system.physmem.perBankRdBursts::13 125625 # Per bank write bursts -system.physmem.perBankRdBursts::14 122955 # Per bank write bursts -system.physmem.perBankRdBursts::15 123650 # Per bank write bursts -system.physmem.perBankWrBursts::0 61294 # Per bank write bursts -system.physmem.perBankWrBursts::1 61576 # Per bank write bursts -system.physmem.perBankWrBursts::2 60653 # Per bank write bursts -system.physmem.perBankWrBursts::3 61320 # Per bank write bursts -system.physmem.perBankWrBursts::4 61767 # Per bank write bursts -system.physmem.perBankWrBursts::5 63184 # Per bank write bursts -system.physmem.perBankWrBursts::6 64210 # Per bank write bursts -system.physmem.perBankWrBursts::7 65704 # Per bank write bursts -system.physmem.perBankWrBursts::8 65475 # Per bank write bursts -system.physmem.perBankWrBursts::9 65876 # Per bank write bursts -system.physmem.perBankWrBursts::10 65422 # Per bank write bursts -system.physmem.perBankWrBursts::11 65733 # Per bank write bursts -system.physmem.perBankWrBursts::12 64307 # Per bank write bursts -system.physmem.perBankWrBursts::13 64297 # Per bank write bursts -system.physmem.perBankWrBursts::14 64633 # Per bank write bursts -system.physmem.perBankWrBursts::15 64303 # Per bank write bursts +system.physmem.perBankRdBursts::0 119017 # Per bank write bursts +system.physmem.perBankRdBursts::1 114428 # Per bank write bursts +system.physmem.perBankRdBursts::2 116569 # Per bank write bursts +system.physmem.perBankRdBursts::3 118023 # Per bank write bursts +system.physmem.perBankRdBursts::4 118127 # Per bank write bursts +system.physmem.perBankRdBursts::5 117816 # Per bank write bursts +system.physmem.perBankRdBursts::6 120202 # Per bank write bursts +system.physmem.perBankRdBursts::7 124913 # Per bank write bursts +system.physmem.perBankRdBursts::8 127544 # Per bank write bursts +system.physmem.perBankRdBursts::9 130446 # Per bank write bursts +system.physmem.perBankRdBursts::10 129104 # Per bank write bursts +system.physmem.perBankRdBursts::11 130773 # Per bank write bursts +system.physmem.perBankRdBursts::12 126663 # Per bank write bursts +system.physmem.perBankRdBursts::13 125636 # Per bank write bursts +system.physmem.perBankRdBursts::14 122981 # Per bank write bursts +system.physmem.perBankRdBursts::15 123654 # Per bank write bursts +system.physmem.perBankWrBursts::0 61274 # Per bank write bursts +system.physmem.perBankWrBursts::1 61571 # Per bank write bursts +system.physmem.perBankWrBursts::2 60654 # Per bank write bursts +system.physmem.perBankWrBursts::3 61312 # Per bank write bursts +system.physmem.perBankWrBursts::4 61747 # Per bank write bursts +system.physmem.perBankWrBursts::5 63190 # Per bank write bursts +system.physmem.perBankWrBursts::6 64213 # Per bank write bursts +system.physmem.perBankWrBursts::7 65700 # Per bank write bursts +system.physmem.perBankWrBursts::8 65483 # Per bank write bursts +system.physmem.perBankWrBursts::9 65878 # Per bank write bursts +system.physmem.perBankWrBursts::10 65419 # Per bank write bursts +system.physmem.perBankWrBursts::11 65720 # Per bank write bursts +system.physmem.perBankWrBursts::12 64327 # Per bank write bursts +system.physmem.perBankWrBursts::13 64305 # Per bank write bursts +system.physmem.perBankWrBursts::14 64649 # Per bank write bursts +system.physmem.perBankWrBursts::15 64294 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 685487953500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 685386422500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966494 # Read request sizes (log2) +system.physmem.readPktSize::6 1966466 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019774 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1645141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 231582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019736 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1645035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 231982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -127,235 +127,234 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 49534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 46127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 49473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 48655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1822247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.837037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.099826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.854977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1460763 80.16% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 186024 10.21% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 72307 3.97% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32393 1.78% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16822 0.92% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10551 0.58% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6953 0.38% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6800 0.37% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3880 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3184 0.17% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2717 0.15% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2015 0.11% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1651 0.09% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1492 0.08% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1271 0.07% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1102 0.06% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 982 0.05% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1041 0.06% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 864 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 817 0.04% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 719 0.04% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2906 0.16% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 391 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 753 0.04% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 249 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 220 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 185 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 207 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 171 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 149 0.01% 99.85% # Bytes accessed per row activation +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1821867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.857955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.098310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.882118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1460616 80.17% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 186071 10.21% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 71892 3.95% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32365 1.78% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16766 0.92% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10653 0.58% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7007 0.38% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6870 0.38% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3886 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3166 0.17% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2723 0.15% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1980 0.11% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1594 0.09% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1502 0.08% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1242 0.07% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1240 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1003 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1017 0.06% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 831 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 807 0.04% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 751 0.04% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2873 0.16% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 389 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 742 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 289 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 237 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 196 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 198 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 161 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 171 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 381 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 117 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 95 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 87 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 78 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 78 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 61 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 165 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 370 0.02% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 134 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 101 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 73 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 67 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 51 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 41 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 29 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 49 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 40 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 35 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 42 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 34 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 27 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 24 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 26 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 27 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 27 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 22 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 17 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 11 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 23 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 21 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 12 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 85 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 29 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 19 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 35 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 9 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 10 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 11 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 16 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 15 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 26 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 22 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 89 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 28 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 125 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1822247 # Bytes accessed per row activation -system.physmem.totQLat 24360796250 # Total ticks spent queuing -system.physmem.totMemAccLat 84735751250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9829735000 # Total ticks spent in databus transfers -system.physmem.totBankLat 50545220000 # Total ticks spent accessing banks -system.physmem.avgQLat 12391.38 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 25710.37 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7936-7937 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 123 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1821867 # Bytes accessed per row activation +system.physmem.totQLat 24443368500 # Total ticks spent queuing +system.physmem.totMemAccLat 84807426000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9829480000 # Total ticks spent in databus transfers +system.physmem.totBankLat 50534577500 # Total ticks spent accessing banks +system.physmem.avgQLat 12433.70 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25705.62 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43101.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 183.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 183.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.21 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43139.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 183.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 183.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.18 # Data bus utilization in percentage system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.63 # Average write queue length when enqueuing -system.physmem.readRowHits 818889 # Number of row buffer hits during reads -system.physmem.writeRowHits 344565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.79 # Row buffer hit rate for writes -system.physmem.avgGap 229546.70 # Average gap between requests -system.physmem.pageHitRate 38.97 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 7.09 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 278810323 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191305 # Transaction distribution -system.membus.trans_dist::ReadResp 1191305 # Transaction distribution -system.membus.trans_dist::Writeback 1019774 # Transaction distribution -system.membus.trans_dist::ReadExReq 775189 # Transaction distribution -system.membus.trans_dist::ReadExResp 775189 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952762 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191121152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191121152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191121152 # Total data (bytes) +system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing +system.physmem.readRowHits 819101 # Number of row buffer hits during reads +system.physmem.writeRowHits 344664 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes +system.physmem.avgGap 229517.77 # Average gap between requests +system.physmem.pageHitRate 38.98 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 278845462 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191273 # Transaction distribution +system.membus.trans_dist::ReadResp 1191273 # Transaction distribution +system.membus.trans_dist::Writeback 1019736 # Transaction distribution +system.membus.trans_dist::ReadExReq 775193 # Transaction distribution +system.membus.trans_dist::ReadExResp 775193 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952668 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191116928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191116928 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191116928 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11874044250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11873404000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18494220250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381678235 # Number of BP lookups -system.cpu.branchPred.condPredicted 296637110 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16088915 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262749250 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259783318 # Number of BTB hits +system.cpu.branchPred.lookups 381642976 # Number of BP lookups +system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262443817 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259723367 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.871193 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24705471 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3030 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.963416 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24699577 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3003 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613987676 # DTB read hits -system.cpu.dtb.read_misses 11260420 # DTB read misses +system.cpu.dtb.read_hits 613972689 # DTB read hits +system.cpu.dtb.read_misses 11257711 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625248096 # DTB read accesses -system.cpu.dtb.write_hits 212348403 # DTB write hits -system.cpu.dtb.write_misses 7134109 # DTB write misses +system.cpu.dtb.read_accesses 625230400 # DTB read accesses +system.cpu.dtb.write_hits 212364531 # DTB write hits +system.cpu.dtb.write_misses 7123508 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219482512 # DTB write accesses -system.cpu.dtb.data_hits 826336079 # DTB hits -system.cpu.dtb.data_misses 18394529 # DTB misses +system.cpu.dtb.write_accesses 219488039 # DTB write accesses +system.cpu.dtb.data_hits 826337220 # DTB hits +system.cpu.dtb.data_misses 18381219 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844730608 # DTB accesses -system.cpu.itb.fetch_hits 391118478 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844718439 # DTB accesses +system.cpu.itb.fetch_hits 391054896 # ITB hits +system.cpu.itb.fetch_misses 42 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391118522 # ITB accesses +system.cpu.itb.fetch_accesses 391054938 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,138 +368,137 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1370976153 # number of cpu cycles simulated +system.cpu.numCycles 1370773091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402585457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3161328538 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381678235 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284488789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574592396 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140681937 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 190961804 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1466 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391118478 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8069239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1284965558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.460244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.144346 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402523002 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161115412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381642976 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284422944 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574525052 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140645567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 190952168 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1444 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 391054896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8064214 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1284797805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.460399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.144459 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 710373162 55.28% 55.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42677954 3.32% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21796461 1.70% 60.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39706509 3.09% 63.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129357441 10.07% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61547596 4.79% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38577258 3.00% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28126573 2.19% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212802604 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 710272753 55.28% 55.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42667609 3.32% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21782496 1.70% 60.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39699327 3.09% 63.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129330544 10.07% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61540269 4.79% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38580495 3.00% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28116157 2.19% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212808155 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1284965558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.278399 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.305896 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434593706 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172173126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542518914 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18856302 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116823510 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58351123 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 876 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3088655283 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2048 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116823510 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457554918 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116845929 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535622730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58111705 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3006575354 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610156 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1852925 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51779132 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247748999 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3899198212 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899055356 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 142855 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1284797805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.278414 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.306082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434521910 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 172167391 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542471492 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18841651 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116795361 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58349498 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 879 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088463521 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116795361 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457475867 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116907635 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7798 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535572514 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58038630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006337354 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 608843 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1808950 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51752219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247576032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898866654 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898722180 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 144473 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 871546036 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 162 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 160 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123661161 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679705832 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255482967 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67737746 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37011786 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724988246 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509612209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3204133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979747229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416253397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1284965558 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953058 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971218 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871373069 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 157 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 156 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123546719 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679659315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255464076 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67507479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36716823 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724801247 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509489521 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3207288 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979575578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416138423 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1284797805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953217 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971436 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442955350 34.47% 34.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203613373 15.85% 50.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185757734 14.46% 64.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153374382 11.94% 76.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133013671 10.35% 87.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80752885 6.28% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65067569 5.06% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15309053 1.19% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5121541 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442944970 34.48% 34.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203642722 15.85% 50.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185470521 14.44% 64.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153370563 11.94% 76.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133097213 10.36% 87.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80758631 6.29% 93.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65098641 5.07% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15296137 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5118407 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1284965558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1284797805 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2189478 11.81% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923612 64.31% 76.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4426862 23.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2193136 11.83% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923525 64.32% 76.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4420966 23.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643894908 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 110 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643778581 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 256 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 160 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued @@ -523,84 +521,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641620248 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224096461 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641602507 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224107818 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509612209 # Type of FU issued -system.cpu.iq.rate 1.830529 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18539952 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007388 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6324036158 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3703625637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413191204 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897903 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1215976 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850771 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527214134 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938027 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62593572 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509489521 # Type of FU issued +system.cpu.iq.rate 1.830711 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18537627 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007387 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6323623582 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703265011 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413078875 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1898180 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217876 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527088869 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938279 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62595515 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235110169 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263246 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94754465 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235063652 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 262733 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107683 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94735574 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 95 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1543010 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 113 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1541249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116823510 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 56431673 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1297935 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867161807 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8942583 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679705832 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255482967 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282108 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18553 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10367292 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8554999 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18922291 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462270338 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625248683 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47341871 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116795361 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 56591518 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1298088 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2866959659 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8943399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679659315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255464076 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282702 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18018 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107683 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10360004 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8558145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18918149 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462143246 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625230973 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47346275 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142173439 # number of nop insts executed -system.cpu.iew.exec_refs 844731223 # number of memory reference insts executed -system.cpu.iew.exec_branches 300901770 # Number of branches executed -system.cpu.iew.exec_stores 219482540 # Number of stores executed -system.cpu.iew.exec_rate 1.795998 # Inst execution rate -system.cpu.iew.wb_sent 2441991151 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2414041975 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388322535 # num instructions producing a value -system.cpu.iew.wb_consumers 1764247998 # num instructions consuming a value +system.cpu.iew.exec_nop 142158292 # number of nop insts executed +system.cpu.iew.exec_refs 844719037 # number of memory reference insts executed +system.cpu.iew.exec_branches 300873221 # Number of branches executed +system.cpu.iew.exec_stores 219488064 # Number of stores executed +system.cpu.iew.exec_rate 1.796171 # Inst execution rate +system.cpu.iew.wb_sent 2441862108 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413929769 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388272639 # num instructions producing a value +system.cpu.iew.wb_consumers 1764258225 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.760820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786920 # average fanout of values written-back +system.cpu.iew.wb_rate 1.760999 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786887 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826708029 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826504574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16088134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1168142048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.499033 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16081360 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1168002444 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.558028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.499439 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654070645 55.99% 55.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174984637 14.98% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86150926 7.38% 78.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53558629 4.58% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34734385 2.97% 85.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26071538 2.23% 88.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21585678 1.85% 89.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22876428 1.96% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94109182 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 654033697 56.00% 56.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174911016 14.98% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86140681 7.38% 78.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53576194 4.59% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34697975 2.97% 85.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25994339 2.23% 88.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21604457 1.85% 89.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22883851 1.96% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94160234 8.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1168142048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1168002444 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,95 +609,95 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94109182 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94160234 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3634741821 # The number of ROB reads -system.cpu.rob.rob_writes 5409898345 # The number of ROB writes -system.cpu.timesIdled 948322 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 86010595 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3634347710 # The number of ROB reads +system.cpu.rob.rob_writes 5409463480 # The number of ROB writes +system.cpu.timesIdled 947782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 85975286 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.789713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.789713 # CPI: Total CPI of All Threads -system.cpu.ipc 1.266283 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.266283 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318184796 # number of integer regfile reads -system.cpu.int_regfile_writes 1932088897 # number of integer regfile writes -system.cpu.fp_regfile_reads 30223 # number of floating regfile reads -system.cpu.fp_regfile_writes 511 # number of floating regfile writes +system.cpu.cpi 0.789596 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.789596 # CPI: Total CPI of All Threads +system.cpu.ipc 1.266471 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.266471 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318031256 # number of integer regfile reads +system.cpu.int_regfile_writes 1931984794 # number of integer regfile writes +system.cpu.fp_regfile_reads 30556 # number of floating regfile reads +system.cpu.fp_regfile_writes 536 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204982897 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085568 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825939456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826001408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826001408 # Total data (bytes) +system.cpu.toL2Bus.throughput 1205179048 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883628 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085762 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825951744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 826013504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 826013504 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178244432 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178550909 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1610000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14084473000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14084464250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 776.507603 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391116973 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 404046.459711 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.100738 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391053395 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 405236.678756 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 776.507603 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.379154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.379154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391116973 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391116973 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391116973 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391116973 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391116973 # number of overall hits -system.cpu.icache.overall_hits::total 391116973 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses -system.cpu.icache.overall_misses::total 1504 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108221250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108221250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108221250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108221250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108221250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108221250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391118477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391118477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391118477 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391118477 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391118477 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391118477 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391053395 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391053395 # number of overall hits +system.cpu.icache.overall_hits::total 391053395 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1501 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1501 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1501 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1501 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1501 # number of overall misses +system.cpu.icache.overall_misses::total 1501 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108152500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108152500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108152500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108152500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108152500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108152500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391054896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391054896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391054896 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391054896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391054896 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391054896 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71955.618351 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71955.618351 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71955.618351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71955.618351 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 344 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72053.630913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72053.630913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72053.630913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72053.630913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 156 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 114.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -709,111 +707,111 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 536 system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75754750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75754750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75754750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75754750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75754750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75754750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75095000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75095000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75095000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75095000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75095000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75095000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78259.039256 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78259.039256 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77818.652850 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77818.652850 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933792 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31423.528987 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058568 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963567 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613323 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1933762 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31423.393947 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058762 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963540 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613485 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 28354220250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14586.952110 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.526107 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.050770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.445158 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14586.517425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.834239 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.042284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958970 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6106321 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106321 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725040 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108417 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108417 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214738 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214738 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214738 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214738 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190337 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191305 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775189 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775189 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 968 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965526 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966494 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 968 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965526 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966494 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74779750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102580412000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 102655191750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67293864000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 67293864000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74779750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169874276000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 169949055750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74779750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169874276000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 169949055750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297626 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883606 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883606 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180264 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181232 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180264 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181232 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_percent::total 0.958966 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6106330 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106330 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3725230 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3725230 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108435 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108435 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214765 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214765 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214765 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214765 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191273 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775193 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775193 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965501 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966466 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965501 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966466 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74125000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102633894750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 102708019750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67309627250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 67309627250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 74125000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 169943522000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 170017647000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 74125000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 169943522000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 170017647000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296638 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297603 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3725230 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3725230 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181231 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181231 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163135 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163246 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411545 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411545 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163131 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163242 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411543 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411543 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214186 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214101 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214183 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214186 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77251.807851 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86177.621968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 86170.369259 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86809.621912 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86809.621912 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77251.807851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86426.878098 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86422.361701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77251.807851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86426.878098 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86422.361701 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214101 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214183 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76813.471503 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86224.653409 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86217.029808 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86829.508587 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86829.508587 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76813.471503 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86458.472712 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76813.471503 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86458.472712 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,180 +820,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019774 # number of writebacks -system.cpu.l2cache.writebacks::total 1019774 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190337 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775189 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775189 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965526 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966494 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965526 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966494 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62594250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 87638263500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 87700857750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57538532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57538532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62594250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145176795500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 145239389750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62594250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145176795500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 145239389750 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019736 # number of writebacks +system.cpu.l2cache.writebacks::total 1019736 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190308 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775193 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775193 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965501 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966466 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965501 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966466 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61971000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 87692417750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 87754388750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57554177250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57554177250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61971000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145246595000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145308566000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61971000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145246595000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145308566000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163135 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163246 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411545 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411545 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163242 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411543 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214103 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214186 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214183 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214103 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214186 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64663.481405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73624.749546 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73617.468029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74225.165734 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74225.165734 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64663.481405 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64663.481405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214183 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64218.652850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73672.039296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73664.381506 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74244.965125 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74244.965125 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176168 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.562922 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694279443 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180264 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.627394 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9176170 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.561673 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694256138 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180266 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.624839 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.562922 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538739511 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538739511 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155539929 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155539929 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694279440 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694279440 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694279440 # number of overall hits -system.cpu.dcache.overall_hits::total 694279440 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11387381 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11387381 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5188573 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5188573 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155539725 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694256136 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694256136 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694256136 # number of overall hits +system.cpu.dcache.overall_hits::total 694256136 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11395033 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11395033 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5188777 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5188777 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16575954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16575954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16575954 # number of overall misses -system.cpu.dcache.overall_misses::total 16575954 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 342766302500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 342766302500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296010973410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296010973410 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 274500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 274500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 638777275910 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 638777275910 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 638777275910 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 638777275910 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550126892 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550126892 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16583810 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16583810 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16583810 # number of overall misses +system.cpu.dcache.overall_misses::total 16583810 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 343354515500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 343354515500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296317441834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296317441834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 639671957334 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 639671957334 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 639671957334 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 639671957334 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550111444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550111444 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710855394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710855394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710855394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710855394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020700 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020700 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032282 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032282 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023318 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023318 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023318 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023318 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30100.538702 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30100.538702 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57050.555791 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57050.555791 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 274500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 274500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38536.380827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38536.380827 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12380978 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8648655 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745505 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.607505 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.782495 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710839946 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710839946 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710839946 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710839946 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032283 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023330 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023330 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30131.945691 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30131.945691 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57107.376523 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57107.376523 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38572.074652 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38572.074652 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12375504 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8646342 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745563 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.598871 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.744945 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725040 # number of writebacks -system.cpu.dcache.writebacks::total 3725040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4090717 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4090717 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304974 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3304974 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7395691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7395691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7395691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7395691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296664 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296664 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883599 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883599 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725230 # number of writebacks +system.cpu.dcache.writebacks::total 3725230 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4098384 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4098384 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305161 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3305161 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7403545 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7403545 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7403545 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7403545 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296649 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296649 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883616 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883616 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180263 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180263 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180263 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180263 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171778792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171778792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80694684874 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80694684874 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 272500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 272500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252473477374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 252473477374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252473477374 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 252473477374 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180265 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180265 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180265 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180265 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171833895250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171833895250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80710616128 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80710616128 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252544511378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 252544511378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252544511378 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 252544511378 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23542.099855 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23542.099855 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42840.692140 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42840.692140 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 272500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 272500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23549.700040 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23549.700040 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42848.763298 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42848.763298 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 30ce01df4..d4b45072d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 7989e6703..19d70b574 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533691 # Number of seconds simulated -sim_ticks 533690503000 # Number of ticks simulated -final_tick 533690503000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533797 # Number of seconds simulated +sim_ticks 533797009000 # Number of ticks simulated +final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128085 # Simulator instruction rate (inst/s) -host_op_rate 142888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44256929 # Simulator tick rate (ticks/s) -host_mem_usage 275676 # Number of bytes of host memory used -host_seconds 12058.91 # Real time elapsed on the host +host_inst_rate 102910 # Simulator instruction rate (inst/s) +host_op_rate 114803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35565366 # Simulator tick rate (ticks/s) +host_mem_usage 295220 # Number of bytes of host memory used +host_seconds 15008.90 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143713600 # Number of bytes read from this memory -system.physmem.bytes_read::total 143761344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70434112 # Number of bytes written to this memory -system.physmem.bytes_written::total 70434112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245525 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246271 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269282663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269372123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131975577 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131975577 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131975577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269282663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401347700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246271 # Number of read requests accepted -system.physmem.writeReqs 1100533 # Number of write requests accepted -system.physmem.readBursts 2246271 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100533 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143722048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 39296 # Total number of bytes read from write queue -system.physmem.bytesWritten 70432960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143761344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70434112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 614 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory +system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory +system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246734 # Number of read requests accepted +system.physmem.writeReqs 1100498 # Number of write requests accepted +system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue +system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139609 # Per bank write bursts -system.physmem.perBankRdBursts::1 136206 # Per bank write bursts -system.physmem.perBankRdBursts::2 133832 # Per bank write bursts -system.physmem.perBankRdBursts::3 136344 # Per bank write bursts -system.physmem.perBankRdBursts::4 135019 # Per bank write bursts -system.physmem.perBankRdBursts::5 135288 # Per bank write bursts -system.physmem.perBankRdBursts::6 136231 # Per bank write bursts -system.physmem.perBankRdBursts::7 136121 # Per bank write bursts -system.physmem.perBankRdBursts::8 143692 # Per bank write bursts -system.physmem.perBankRdBursts::9 146373 # Per bank write bursts -system.physmem.perBankRdBursts::10 144432 # Per bank write bursts -system.physmem.perBankRdBursts::11 146294 # Per bank write bursts -system.physmem.perBankRdBursts::12 145666 # Per bank write bursts -system.physmem.perBankRdBursts::13 146070 # Per bank write bursts -system.physmem.perBankRdBursts::14 142065 # Per bank write bursts -system.physmem.perBankRdBursts::15 142415 # Per bank write bursts -system.physmem.perBankWrBursts::0 69121 # Per bank write bursts -system.physmem.perBankWrBursts::1 67439 # Per bank write bursts -system.physmem.perBankWrBursts::2 65729 # Per bank write bursts -system.physmem.perBankWrBursts::3 66294 # Per bank write bursts -system.physmem.perBankWrBursts::4 66241 # Per bank write bursts -system.physmem.perBankWrBursts::5 66403 # Per bank write bursts -system.physmem.perBankWrBursts::6 67965 # Per bank write bursts -system.physmem.perBankWrBursts::7 68773 # Per bank write bursts -system.physmem.perBankWrBursts::8 70328 # Per bank write bursts -system.physmem.perBankWrBursts::9 70962 # Per bank write bursts -system.physmem.perBankWrBursts::10 70540 # Per bank write bursts -system.physmem.perBankWrBursts::11 70927 # Per bank write bursts -system.physmem.perBankWrBursts::12 70302 # Per bank write bursts -system.physmem.perBankWrBursts::13 70806 # Per bank write bursts -system.physmem.perBankWrBursts::14 69598 # Per bank write bursts -system.physmem.perBankWrBursts::15 69087 # Per bank write bursts +system.physmem.perBankRdBursts::0 139750 # Per bank write bursts +system.physmem.perBankRdBursts::1 136273 # Per bank write bursts +system.physmem.perBankRdBursts::2 133708 # Per bank write bursts +system.physmem.perBankRdBursts::3 136246 # Per bank write bursts +system.physmem.perBankRdBursts::4 134906 # Per bank write bursts +system.physmem.perBankRdBursts::5 135253 # Per bank write bursts +system.physmem.perBankRdBursts::6 136175 # Per bank write bursts +system.physmem.perBankRdBursts::7 136295 # Per bank write bursts +system.physmem.perBankRdBursts::8 143732 # Per bank write bursts +system.physmem.perBankRdBursts::9 146555 # Per bank write bursts +system.physmem.perBankRdBursts::10 144302 # Per bank write bursts +system.physmem.perBankRdBursts::11 146237 # Per bank write bursts +system.physmem.perBankRdBursts::12 145788 # Per bank write bursts +system.physmem.perBankRdBursts::13 146277 # Per bank write bursts +system.physmem.perBankRdBursts::14 142119 # Per bank write bursts +system.physmem.perBankRdBursts::15 142542 # Per bank write bursts +system.physmem.perBankWrBursts::0 69128 # Per bank write bursts +system.physmem.perBankWrBursts::1 67452 # Per bank write bursts +system.physmem.perBankWrBursts::2 65650 # Per bank write bursts +system.physmem.perBankWrBursts::3 66298 # Per bank write bursts +system.physmem.perBankWrBursts::4 66182 # Per bank write bursts +system.physmem.perBankWrBursts::5 66379 # Per bank write bursts +system.physmem.perBankWrBursts::6 67939 # Per bank write bursts +system.physmem.perBankWrBursts::7 68869 # Per bank write bursts +system.physmem.perBankWrBursts::8 70353 # Per bank write bursts +system.physmem.perBankWrBursts::9 70986 # Per bank write bursts +system.physmem.perBankWrBursts::10 70505 # Per bank write bursts +system.physmem.perBankWrBursts::11 70955 # Per bank write bursts +system.physmem.perBankWrBursts::12 70250 # Per bank write bursts +system.physmem.perBankWrBursts::13 70819 # Per bank write bursts +system.physmem.perBankWrBursts::14 69624 # Per bank write bursts +system.physmem.perBankWrBursts::15 69092 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 533690432500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 533796944500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246271 # Read request sizes (log2) +system.physmem.readPktSize::6 2246734 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100533 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1620463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100498 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,217 +127,215 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 51901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2077885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.053834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.951836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.653120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1660855 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 226890 10.92% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 69105 3.33% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37676 1.81% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 25011 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12112 0.58% 97.77% # Bytes accessed per row activation +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8103 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4494 0.22% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3425 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2747 0.13% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2032 0.10% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1669 0.08% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1441 0.07% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1240 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1051 0.05% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 987 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 902 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 711 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 909 0.04% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 717 0.03% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 694 0.03% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3096 0.15% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 406 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 291 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 190 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 185 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 205 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 473 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 131 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 122 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 122 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 103 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 129 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 90 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 83 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 94 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 68 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 57 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 64 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 70 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 60 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 55 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 48 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 43 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 58 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 55 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 43 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 33 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 32 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 24 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 19 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 34 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 14 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 21 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 20 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 289 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 203 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 186 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 219 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 499 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 143 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 125 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 127 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 94 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 128 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 92 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 97 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 82 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 82 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 62 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 59 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 52 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 72 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 47 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 62 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 51 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 51 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 39 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 48 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 40 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 42 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 28 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 34 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 44 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 23 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 29 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 27 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 28 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 28 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 34 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 27 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 36 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 187 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 23 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 20 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 15 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 185 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 17 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 34 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 26 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 83 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2077885 # Bytes accessed per row activation -system.physmem.totQLat 32824703500 # Total ticks spent queuing -system.physmem.totMemAccLat 104040704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11228285000 # Total ticks spent in databus transfers -system.physmem.totBankLat 59987716250 # Total ticks spent accessing banks -system.physmem.avgQLat 14616.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26712.77 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation +system.physmem.totQLat 32821468000 # Total ticks spent queuing +system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers +system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks +system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46329.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.98 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.08 # Average write queue length when enqueuing -system.physmem.readRowHits 931610 # Number of row buffer hits during reads -system.physmem.writeRowHits 336677 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes -system.physmem.avgGap 159462.71 # Average gap between requests -system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.89 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401347580 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1419678 # Transaction distribution -system.membus.trans_dist::ReadResp 1419677 # Transaction distribution -system.membus.trans_dist::Writeback 1100533 # Transaction distribution -system.membus.trans_dist::ReadExReq 826593 # Transaction distribution -system.membus.trans_dist::ReadExResp 826593 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593074 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214195392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214195392 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214195392 # Total data (bytes) +system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing +system.physmem.readRowHits 932509 # Number of row buffer hits during reads +system.physmem.writeRowHits 336457 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes +system.physmem.avgGap 159474.14 # Average gap between requests +system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401318817 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420235 # Transaction distribution +system.membus.trans_dist::ReadResp 1420234 # Transaction distribution +system.membus.trans_dist::Writeback 1100498 # Transaction distribution +system.membus.trans_dist::ReadExReq 826499 # Transaction distribution +system.membus.trans_dist::ReadExResp 826499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214222784 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12924294750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21079818750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 303467870 # Number of BP lookups -system.cpu.branchPred.condPredicted 249715061 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15195903 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 175178105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161776963 # Number of BTB hits +system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.cpu.branchPred.lookups 303451211 # Number of BP lookups +system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.349990 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17540871 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 204 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -381,133 +379,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067381007 # number of cpu cycles simulated +system.cpu.numCycles 1067594019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299148062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189533318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303467870 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179317834 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435752088 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88086251 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164106751 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289566494 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5997594 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 968963067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206367 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533211067 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25485631 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39032754 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48282665 4.98% 66.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43767932 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46382840 4.79% 75.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38389210 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18960850 1.96% 81.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175450118 18.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 968963067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284311 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051314 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331377153 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 141962670 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405350137 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20317948 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69955159 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46017147 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369104960 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2426 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69955159 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354884990 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70530339 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17935 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400511119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73063525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306250708 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 150920 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5011927 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60136403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282159345 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649371145 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763416611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 460 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575839415 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 404 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160989021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624749088 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220784728 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85932352 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70842412 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202316968 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 440 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018777354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4015619 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474672323 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127531541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 270 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 968963067 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083441 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906294 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 843 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286087063 29.53% 29.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153648666 15.86% 45.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160841319 16.60% 61.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120316001 12.42% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123517924 12.75% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73816539 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38325528 3.96% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9889728 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2520299 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 968963067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 895423 3.74% 3.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5601 0.02% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18274862 76.27% 80.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4786167 19.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236899038 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924736 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -529,90 +526,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 48 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587872837 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193080663 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018777354 # Type of FU issued -system.cpu.iq.rate 1.891337 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23962053 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011870 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034495136 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677178912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957310102 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 311 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 694 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 129 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042739250 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 157 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64569425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued +system.cpu.iq.rate 1.890996 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138822319 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 268987 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192391 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45937683 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4778132 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69955159 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33483642 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1603224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202317539 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7879544 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624749088 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220784728 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 378 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 478707 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97428 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192391 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8138332 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9600465 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17738797 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988042975 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574015030 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30734379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 131 # number of nop insts executed -system.cpu.iew.exec_refs 764217607 # number of memory reference insts executed -system.cpu.iew.exec_branches 238311346 # Number of branches executed -system.cpu.iew.exec_stores 190202577 # Number of stores executed -system.cpu.iew.exec_rate 1.862543 # Inst execution rate -system.cpu.iew.wb_sent 1965731650 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957310231 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295404026 # num instructions producing a value -system.cpu.iew.wb_consumers 2059270839 # num instructions consuming a value +system.cpu.iew.exec_nop 92 # number of nop insts executed +system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed +system.cpu.iew.exec_branches 238324356 # Number of branches executed +system.cpu.iew.exec_stores 190177930 # Number of stores executed +system.cpu.iew.exec_rate 1.862201 # Inst execution rate +system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295422958 # num instructions producing a value +system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833750 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629060 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479343339 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15195240 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899007908 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916639 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718451 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410513863 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193235979 21.49% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72768373 8.09% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35278706 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18862057 2.10% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30820454 3.43% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19957331 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11398634 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106172511 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899007908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -623,90 +620,90 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106172511 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995251990 # The number of ROB reads -system.cpu.rob.rob_writes 4474939624 # The number of ROB writes -system.cpu.timesIdled 1152982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98417940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995444799 # The number of ROB reads +system.cpu.rob.rob_writes 4475102834 # The number of ROB writes +system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691057 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691057 # CPI: Total CPI of All Threads -system.cpu.ipc 1.447059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.447059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956212388 # number of integer regfile reads -system.cpu.int_regfile_writes 1937181821 # number of integer regfile writes -system.cpu.fp_regfile_reads 130 # number of floating regfile reads -system.cpu.fp_regfile_writes 139 # number of floating regfile writes -system.cpu.misc_regfile_reads 737624314 # number of misc regfile reads +system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads +system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads +system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes +system.cpu.fp_regfile_reads 112 # number of floating regfile reads +system.cpu.fp_regfile_writes 111 # number of floating regfile writes +system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1605146644 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709082 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3782685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893414 # Transaction distribution +system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22987676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856601984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856651520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856651520 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10475431595 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1294249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14768966243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 22 # number of replacements -system.cpu.icache.tags.tagsinuse 628.527972 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289565308 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 20 # number of replacements +system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 374115.385013 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.527972 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306898 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306898 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 289565308 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289565308 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289565308 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289565308 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289565308 # number of overall hits -system.cpu.icache.overall_hits::total 289565308 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1186 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1186 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1186 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1186 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1186 # number of overall misses -system.cpu.icache.overall_misses::total 1186 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82924749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82924749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82924749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82924749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82924749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82924749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289566494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289566494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289566494 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289566494 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289566494 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289566494 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits +system.cpu.icache.overall_hits::total 289570320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses +system.cpu.icache.overall_misses::total 1208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69919.687184 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69919.687184 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69919.687184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69919.687184 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -715,120 +712,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57029751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 57029751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57029751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 57029751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57029751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 57029751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56793251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56793251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56793251 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73681.848837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73681.848837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73376.293282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73376.293282 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2213583 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31532.604049 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9247674 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2243357 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.122248 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2214050 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31533.035321 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9245310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243823 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.120338 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14306.578053 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.421352 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17205.604643 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.436602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.525073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.962299 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6289369 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6289396 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3782685 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3782685 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066821 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066821 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7356190 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7356217 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7356190 # number of overall hits -system.cpu.l2cache.overall_hits::total 7356217 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 747 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1418939 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1419686 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826593 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826593 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 747 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2245532 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2246279 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 747 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2245532 # number of overall misses -system.cpu.l2cache.overall_misses::total 2246279 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55980750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125563538750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 125619519500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76414651500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 76414651500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 55980750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 201978190250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 202034171000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 55980750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 201978190250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 202034171000 # number of overall miss cycles +system.cpu.l2cache.tags.occ_blocks::writebacks 14302.277072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.244042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17210.514207 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.436471 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.525223 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.962312 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6288761 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6288789 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3780837 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3780837 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1066946 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1066946 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7355707 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7355735 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7355707 # number of overall hits +system.cpu.l2cache.overall_hits::total 7355735 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1420243 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826499 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826499 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 746 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2245996 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246742 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 746 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2245996 # number of overall misses +system.cpu.l2cache.overall_misses::total 2246742 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55733750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125730219750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 125785953500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76291008750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 76291008750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55733750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 202021228500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 202076962250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 55733750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 202021228500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 202076962250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7708308 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7709082 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3782685 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3782685 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7708258 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7709032 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3780837 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3780837 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893445 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893445 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9601722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9602496 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9601703 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9602477 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9601722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9602496 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184079 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965116 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965116 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74940.763052 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88491.146378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88484.016536 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92445.316498 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92445.316498 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89941.708488 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89941.708488 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 9601703 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9602477 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963824 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184153 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184231 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436505 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436505 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963824 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233916 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233975 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963824 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233916 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233975 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74710.120643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88573.783354 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88566.501296 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92306.232373 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92306.232373 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89942.219556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89942.219556 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -837,8 +834,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100533 # number of writebacks -system.cpu.l2cache.writebacks::total 1100533 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100498 # number of writebacks +system.cpu.l2cache.writebacks::total 1100498 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits @@ -848,176 +845,176 @@ system.cpu.l2cache.demand_mshr_hits::total 8 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418932 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419678 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826593 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826593 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2245525 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246271 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245525 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246271 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46519250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107766607500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107813126750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66030369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66030369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46519250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173796976500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 173843495750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46519250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173796976500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 173843495750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184078 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62358.243968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75949.099393 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75941.957789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79882.564938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79882.564938 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 745 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419490 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420235 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826499 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826499 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2245989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246734 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245989 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246734 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46285250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107925588000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107971873250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65906925250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65906925250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46285250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173832513250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 173878798500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46285250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173832513250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 173878798500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233974 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233974 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62127.852349 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76031.242207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76023.949030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79742.292792 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9597625 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.040332 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 656028832 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9601721 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.324088 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9597606 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.041920 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 656019476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9601702 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.323249 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.040332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041920 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489072771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489072771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166955934 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166955934 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 66 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 66 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656028705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656028705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656028705 # number of overall hits -system.cpu.dcache.overall_hits::total 656028705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11514039 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11514039 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5630113 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5630113 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656019351 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656019351 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656019351 # number of overall hits +system.cpu.dcache.overall_hits::total 656019351 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11507496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11507496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5629349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5629349 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17144152 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17144152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17144152 # number of overall misses -system.cpu.dcache.overall_misses::total 17144152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 363445631238 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 363445631238 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307798034677 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307798034677 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 671243665915 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 671243665915 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 671243665915 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 671243665915 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500586810 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500586810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17136845 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17136845 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17136845 # number of overall misses +system.cpu.dcache.overall_misses::total 17136845 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 363702842488 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 363702842488 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 671447805394 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 671447805394 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 671447805394 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 671447805394 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500570149 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500570149 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673172857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673172857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673172857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673172857 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032622 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043478 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025468 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025468 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025468 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025468 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31565.433402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31565.433402 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54669.956833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54669.956833 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39152.923161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39152.923161 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24614592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988980 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212230 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.305216 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.243609 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3782685 # number of writebacks -system.cpu.dcache.writebacks::total 3782685 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3805731 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3805731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736699 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3736699 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3780837 # number of writebacks +system.cpu.dcache.writebacks::total 3780837 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3799238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3799238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3735904 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3735904 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7542430 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7542430 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7542430 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7542430 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708308 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708308 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893414 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893414 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601722 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601722 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601722 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601722 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198054864257 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198054864257 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89469568032 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89469568032 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287524432289 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 287524432289 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287524432289 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 287524432289 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7535142 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7535142 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7535142 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7535142 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708258 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708258 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893445 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893445 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601703 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601703 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601703 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601703 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198213123757 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 198213123757 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89346986214 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25693.688454 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25693.688454 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47253.040292 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47253.040292 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index c08f958c6..8a347565f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index d049654a9..5f89f07e5 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.041680 # Nu sim_ticks 41680207000 # Number of ticks simulated final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118687 # Simulator instruction rate (inst/s) -host_op_rate 118687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53827332 # Simulator tick rate (ticks/s) -host_mem_usage 260144 # Number of bytes of host memory used -host_seconds 774.33 # Real time elapsed on the host +host_inst_rate 93645 # Simulator instruction rate (inst/s) +host_op_rate 93645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42470141 # Simulator tick rate (ticks/s) +host_mem_usage 279708 # Number of bytes of host memory used +host_seconds 981.40 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -203,14 +203,14 @@ system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation -system.physmem.totQLat 34068750 # Total ticks spent queuing -system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 34070750 # Total ticks spent queuing +system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers system.physmem.totBankLat 67663750 # Total ticks spent accessing banks -system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -239,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted @@ -310,9 +310,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed. -system.cpu.activity 90.699835 # Percentage of cycles cpu is active +system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed. +system.cpu.activity 90.699836 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -342,9 +342,9 @@ system.cpu.stage2.utilization 59.802183 # Pe system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. @@ -366,12 +366,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses @@ -384,12 +384,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,24 +410,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution @@ -486,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -521,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,14 +554,14 @@ system.cpu.l2cache.overall_mshr_misses::total 4938 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -576,22 +576,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits @@ -610,14 +610,14 @@ system.cpu.dcache.demand_misses::cpu.data 8851 # n system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses system.cpu.dcache.overall_misses::total 8851 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -634,19 +634,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -670,12 +670,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2223 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -686,12 +686,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index b1f130dee..201e62f46 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 1aa820757..445692444 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023462 # Nu sim_ticks 23461709500 # Number of ticks simulated final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165875 # Simulator instruction rate (inst/s) -host_op_rate 165875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46230980 # Simulator tick rate (ticks/s) -host_mem_usage 261164 # Number of bytes of host memory used -host_seconds 507.49 # Real time elapsed on the host +host_inst_rate 127245 # Simulator instruction rate (inst/s) +host_op_rate 127245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35464472 # Simulator tick rate (ticks/s) +host_mem_usage 280732 # Number of bytes of host memory used +host_seconds 661.56 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory @@ -204,14 +204,14 @@ system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation -system.physmem.totQLat 37518250 # Total ticks spent queuing -system.physmem.totMemAccLat 134402000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 37518750 # Total ticks spent queuing +system.physmem.totMemAccLat 134402500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers system.physmem.totBankLat 70743750 # Total ticks spent accessing banks -system.physmem.avgQLat 7176.41 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7176.50 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25708.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25708.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s @@ -240,17 +240,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6831000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49013750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.branchPred.lookups 14847721 # Number of BP lookups system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6957683 # Number of BTB hits +system.cpu.branchPred.BTBHits 6957680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.809492 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 83.809456 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits @@ -289,93 +289,93 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 46923420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15463377 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126961895 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 15463381 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126961894 # Number of instructions fetch has processed system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8425661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22130057 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473004 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5559399 # Number of cycles fetch has spent blocked +system.cpu.fetch.predictedBranches 8425658 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22130056 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473003 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5559398 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324640 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 324644 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46671603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24541545 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24541547 52.58% 52.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755702 5.90% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755701 5.90% 69.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771783 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10936610 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771780 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10936613 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46671603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705726 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17289391 # Number of cycles decode is idle +system.cpu.fetch.rate 2.705725 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17289395 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20524695 # Number of cycles decode is running +system.cpu.decode.RunCycles 20524693 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3504753 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 3504752 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123979131 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 12167 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123979126 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3504753 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18431775 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 3504752 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18431780 # Number of cycles rename is idle system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20455401 # Number of cycles rename is running +system.cpu.rename.RunCycles 20455398 # Number of cycles rename is running system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121154586 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 121154570 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88974234 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157440436 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150394666 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 88974225 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157440425 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150394655 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20546873 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 20546864 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 749 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25363135 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8241350 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 25363133 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8241349 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105438340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 105438334 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96565073 # Number of instructions issued +system.cpu.iq.iqInstsIssued 96565072 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20784584 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15622472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 20784578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15622466 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46671603 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12133901 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9340973 20.01% 46.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12133902 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9340972 20.01% 46.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4921134 10.54% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2853572 6.11% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4921137 10.54% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2853571 6.11% 94.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798698 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 798697 1.71% 99.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46671603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available @@ -411,7 +411,7 @@ system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58732394 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58732393 60.82% 60.82% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued @@ -444,36 +444,36 @@ system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Ty system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96565073 # Type of FU issued +system.cpu.iq.FU_type_0::total 96565072 # Type of FU issued system.cpu.iq.rate 2.057929 # Inst issue rate system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226434514 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117518312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 226434513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117518300 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90145383 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 90145382 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5366937 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 5366935 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740247 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1740246 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3504753 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 3504752 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115674273 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 115674265 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25363135 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8241350 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 25363133 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8241349 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall @@ -483,41 +483,41 @@ system.cpu.iew.predictedNotTakenIncorrect 494157 # N system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1227384 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1227383 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10234972 # number of nop insts executed +system.cpu.iew.exec_nop 10234970 # number of nop insts executed system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed system.cpu.iew.exec_branches 12022158 # Number of branches executed system.cpu.iew.exec_stores 7069522 # Number of stores executed system.cpu.iew.exec_rate 2.031772 # Inst execution rate -system.cpu.iew.wb_sent 94652013 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 94652012 # cumulative count of insts sent to commit system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64474348 # num instructions producing a value -system.cpu.iew.wb_consumers 89850693 # num instructions consuming a value +system.cpu.iew.wb_producers 64474346 # num instructions producing a value +system.cpu.iew.wb_consumers 89850691 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23772324 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23772316 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 43166851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16723467 38.74% 38.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9908467 22.95% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16723468 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9908468 22.95% 61.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818064 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5518957 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818065 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5518956 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43166851 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -528,12 +528,12 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5518957 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5518956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153322231 # The number of ROB reads -system.cpu.rob.rob_writes 234879486 # The number of ROB writes +system.cpu.rob.rob_reads 153322226 # The number of ROB reads +system.cpu.rob.rob_writes 234879469 # The number of ROB writes system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 251818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 251817 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated @@ -542,7 +542,7 @@ system.cpu.cpi_total 0.557420 # CP system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 129048096 # number of integer regfile reads -system.cpu.int_regfile_writes 70519804 # number of integer regfile writes +system.cpu.int_regfile_writes 70519803 # number of integer regfile writes system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes system.cpu.misc_regfile_reads 714547 # number of misc regfile reads @@ -568,32 +568,32 @@ system.cpu.toL2Bus.respLayer0.utilization 0.1 # L system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 9576 # number of replacements -system.cpu.icache.tags.tagsinuse 1596.482982 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14719875 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1596.482984 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14719872 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1278.877063 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1278.876803 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482982 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14719875 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14719875 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14719875 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14719875 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14719875 # number of overall hits -system.cpu.icache.overall_hits::total 14719875 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14285 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14285 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14285 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14285 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14285 # number of overall misses -system.cpu.icache.overall_misses::total 14285 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413142250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413142250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413142250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413142250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413142250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413142250 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14719872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14719872 # number of overall hits +system.cpu.icache.overall_hits::total 14719872 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14288 # number of overall misses +system.cpu.icache.overall_misses::total 14288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413271500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413271500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413271500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413271500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413271500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413271500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses @@ -606,12 +606,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28921.403570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28921.403570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28921.403570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28921.403570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28924.377100 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28924.377100 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28924.377100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28924.377100 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked @@ -620,45 +620,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2775 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2775 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2775 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2775 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2775 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2775 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2778 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2778 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2778 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2778 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2778 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2778 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11510 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11510 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11510 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303669750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 303669750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303669750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 303669750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303669750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 303669750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303668250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 303668250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303668250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 303668250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303668250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 303668250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000781 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000781 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26383.123371 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26383.123371 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26382.993050 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26382.993050 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.583503 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2409.583505 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8517 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.372423 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.678720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447961 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447963 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 381.456822 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy @@ -688,17 +688,17 @@ system.cpu.l2cache.demand_misses::total 5228 # nu system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2166 # number of overall misses system.cpu.l2cache.overall_misses::total 5228 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207669750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34561250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 242231000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124309250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 124309250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207669750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158870500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 366540250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207669750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158870500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 366540250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207668250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34560750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 242229000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124310250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 124310250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207668250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 366539250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207668250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158871000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 366539250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12026 # number of ReadReq accesses(hits+misses) @@ -723,17 +723,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380025 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.603527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74970.173536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68757.025263 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.651026 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.651026 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70110.988906 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70110.988906 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,17 +753,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168835250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168834750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103389750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103389750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168835250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132248000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 301083250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168835250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132248000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 301083250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103390750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103390750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168834750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132249000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 301083750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168834750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132249000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 301083750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses @@ -775,25 +775,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.879817 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56115.100766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.149560 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.149560 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1459.152637 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1459.152638 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152637 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits @@ -816,16 +816,16 @@ system.cpu.dcache.demand_misses::cpu.data 9208 # n system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses system.cpu.dcache.overall_misses::total 9208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58289750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 505815795 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 505815795 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58289250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 505816795 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 505816795 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 564105545 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 564105545 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 564105545 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 564105545 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 564106045 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 564106045 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 564106045 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 564106045 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -846,16 +846,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.739220 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.739220 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.142701 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.142701 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61262.548328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61262.602628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61262.602628 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked @@ -884,16 +884,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2246 system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126440497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126440497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126441497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126441497 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161992997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161992997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161992997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161992997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161993497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161993497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161993497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161993497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses @@ -904,16 +904,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.980583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.980583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73044.770075 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73044.770075 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index d981a43f0..90382fb26 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 4425c72f1..ac21abc99 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074220 # Nu sim_ticks 74219948500 # Number of ticks simulated final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110839 # Simulator instruction rate (inst/s) -host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47744278 # Simulator tick rate (ticks/s) -host_mem_usage 278976 # Number of bytes of host memory used -host_seconds 1554.53 # Real time elapsed on the host +host_inst_rate 84730 # Simulator instruction rate (inst/s) +host_op_rate 92772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36497737 # Simulator tick rate (ticks/s) +host_mem_usage 298520 # Number of bytes of host memory used +host_seconds 2033.55 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory @@ -197,14 +197,14 @@ system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25205500 # Total ticks spent queuing -system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 25203500 # Total ticks spent queuing +system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s @@ -233,18 +233,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94784279 # Number of BP lookups -system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted +system.cpu.branchPred.lookups 94784274 # Number of BP lookups +system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -292,95 +292,95 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 148439898 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched +system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running +system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups +system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available @@ -416,7 +416,7 @@ system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued @@ -449,21 +449,21 @@ system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Ty system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued +system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued system.cpu.iq.rate 1.680523 # Inst issue rate system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed @@ -472,12 +472,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall @@ -488,7 +488,7 @@ system.cpu.iew.predictedNotTakenIncorrect 3760086 # N system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 17196 # number of nop insts executed system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed @@ -497,23 +497,23 @@ system.cpu.iew.exec_stores 13648456 # Nu system.cpu.iew.exec_rate 1.636760 # Inst execution rate system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148474079 # num instructions producing a value -system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value +system.cpu.iew.wb_producers 148474078 # num instructions producing a value +system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle @@ -522,7 +522,7 @@ system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -535,10 +535,10 @@ system.cpu.commit.int_insts 150106217 # Nu system.cpu.commit.function_calls 1848934 # Number of function calls committed. system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448787441 # The number of ROB reads -system.cpu.rob.rob_writes 679451137 # The number of ROB writes +system.cpu.rob.rob_reads 448787434 # The number of ROB reads +system.cpu.rob.rob_writes 679451113 # The number of ROB writes system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated @@ -574,49 +574,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3047739 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2394 # number of replacements system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits -system.cpu.icache.overall_hits::total 36845555 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits +system.cpu.icache.overall_hits::total 36845557 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses system.cpu.icache.overall_misses::total 5337 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -637,33 +637,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4126 system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy @@ -693,17 +693,17 @@ system.cpu.l2cache.demand_misses::total 3809 # nu system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses system.cpu.l2cache.overall_misses::total 3809 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) @@ -728,17 +728,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.637170 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,17 +767,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3794 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses @@ -789,17 +789,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use @@ -832,16 +832,16 @@ system.cpu.dcache.demand_misses::cpu.data 9625 # n system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses system.cpu.dcache.overall_misses::total 9625 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -864,16 +864,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -902,14 +902,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1852 system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -918,14 +918,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 5e4a8f947..210f89c36 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 003c2ae7a..3f8722e89 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.144463 # Nu sim_ticks 144463317000 # Number of ticks simulated final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66822 # Simulator instruction rate (inst/s) -host_op_rate 111999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73091533 # Simulator tick rate (ticks/s) -host_mem_usage 308580 # Number of bytes of host memory used -host_seconds 1976.47 # Real time elapsed on the host +host_inst_rate 55445 # Simulator instruction rate (inst/s) +host_op_rate 92931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60647702 # Simulator tick rate (ticks/s) +host_mem_usage 328672 # Number of bytes of host memory used +host_seconds 2382.01 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory @@ -207,14 +207,14 @@ system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # By system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation -system.physmem.totQLat 28805000 # Total ticks spent queuing -system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 28783000 # Total ticks spent queuing +system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers system.physmem.totBankLat 82293750 # Total ticks spent accessing banks -system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s @@ -247,12 +247,12 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 342656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18648234 # Number of BP lookups -system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18648233 # Number of BP lookups +system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits @@ -264,90 +264,90 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 289221873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running +system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking +system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename +system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued +system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available @@ -383,7 +383,7 @@ system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued @@ -412,26 +412,26 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued -system.cpu.iq.rate 0.900700 # Inst issue rate +system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued +system.cpu.iq.rate 0.900699 # Inst issue rate system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address @@ -439,57 +439,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute +system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed -system.cpu.iew.exec_branches 14265860 # Number of branches executed +system.cpu.iew.exec_branches 14265859 # Number of branches executed system.cpu.iew.exec_stores 22347175 # Number of stores executed system.cpu.iew.exec_rate 0.894581 # Inst execution rate -system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back +system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back system.cpu.iew.wb_producers 205928299 # num instructions producing a value -system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value +system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -500,12 +500,12 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571692691 # The number of ROB reads -system.cpu.rob.rob_writes 659422929 # The number of ROB writes +system.cpu.rob.rob_reads 571692690 # The number of ROB reads +system.cpu.rob.rob_writes 659422914 # The number of ROB writes system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated @@ -513,13 +513,13 @@ system.cpu.cpi 2.189894 # CP system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451224157 # number of integer regfile reads +system.cpu.int_regfile_reads 451224153 # number of integer regfile reads system.cpu.int_regfile_writes 233957254 # number of integer regfile writes system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes -system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads -system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes -system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads +system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads +system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes +system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution @@ -545,49 +545,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3467413 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 4653 # number of replacements system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits -system.cpu.icache.overall_hits::total 22344301 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses -system.cpu.icache.overall_misses::total 8911 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits +system.cpu.icache.overall_hits::total 22344300 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses +system.cpu.icache.overall_misses::total 8910 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked @@ -596,45 +596,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy @@ -666,17 +666,17 @@ system.cpu.l2cache.demand_misses::total 5355 # nu system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses system.cpu.l2cache.overall_misses::total 5355 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses) @@ -705,17 +705,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.620870 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,19 +737,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5355 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses @@ -763,37 +763,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits -system.cpu.dcache.overall_hits::total 66102125 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits +system.cpu.dcache.overall_hits::total 66102126 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses @@ -810,14 +810,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 176670730 system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses |