diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/se | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/se')
13 files changed, 5671 insertions, 5671 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index b7910ff50..df256055e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061594 # Number of seconds simulated -sim_ticks 61594138500 # Number of ticks simulated -final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061296 # Number of seconds simulated +sim_ticks 61295518500 # Number of ticks simulated +final_tick 61295518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265976 # Simulator instruction rate (inst/s) -host_op_rate 267300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180817037 # Simulator tick rate (ticks/s) +host_inst_rate 265745 # Simulator instruction rate (inst/s) +host_op_rate 267069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 179784475 # Simulator tick rate (ticks/s) host_mem_usage 446692 # Number of bytes of host memory used -host_seconds 340.64 # Real time elapsed on the host +host_seconds 340.94 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15453006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16261156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15453006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16261156 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61594044000 # Total gap between requests +system.physmem.totGap 61295424000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 76216750 # Total ticks spent queuing -system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 651.693517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 447.533847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.021267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 238 15.59% 15.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 181 11.85% 27.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 5.50% 32.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.45% 37.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.65% 42.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 87 5.70% 47.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 52 3.41% 51.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 56 3.67% 54.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 690 45.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation +system.physmem.totQLat 75432750 # Total ticks spent queuing +system.physmem.totMemAccLat 367445250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4843.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23593.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14024 # Number of row buffer hits during reads +system.physmem.readRowHits 14042 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3954927.70 # Average gap between requests -system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3935753.44 # Average gap between requests +system.physmem.pageHitRate 90.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.614039 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_0.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2494246185 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34588236750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41159350290 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511167 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57530940500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2046720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1716061500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.506960 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_1.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2575259145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34517172750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41161458375 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.545560 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57412676250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2046720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1834237500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20791997 # Number of BP lookups -system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits +system.cpu.branchPred.lookups 20766617 # Number of BP lookups +system.cpu.branchPred.condPredicted 17069689 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8958723 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8857106 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.865720 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62714 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 123188277 # number of cpu cycles simulated +system.cpu.numCycles 122591037 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2197459 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359651 # CPI: cycles per instruction -system.cpu.ipc 0.735483 # IPC: instructions per cycle -system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 946088 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy +system.cpu.cpi 1.353059 # CPI: cycles per instruction +system.cpu.ipc 0.739066 # IPC: instructions per cycle +system.cpu.tickCycles 109335027 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13256010 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 946108 # number of replacements +system.cpu.dcache.tags.tagsinuse 3616.919530 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267744 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.644321 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20526719250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.919530 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883037 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883037 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463926 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463926 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598657 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660805 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits -system.cpu.dcache.overall_hits::total 26259934 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26259462 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259462 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259970 # number of overall hits +system.cpu.dcache.overall_hits::total 26259970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914937 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914937 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74176 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74176 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses -system.cpu.dcache.overall_misses::total 989096 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 989113 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989113 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989117 # number of overall misses +system.cpu.dcache.overall_misses::total 989117 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11917910744 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11917910744 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566961500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2566961500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14484872244 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14484872244 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14484872244 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14484872244 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513594 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513594 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27248575 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248575 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27249087 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27249087 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015666 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015666 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.036300 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036300 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14644.304790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14644.245569 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks -system.cpu.dcache.writebacks::total 943266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks +system.cpu.dcache.writebacks::total 943289 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11503 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11503 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27409 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27409 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38912 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38912 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38912 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38912 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 950201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412555256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412555256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464079000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464079000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876634256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11876634256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11876789756 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11876789756 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 690.351832 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27857021 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.424253 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27792420 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34734.440150 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34653.890274 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.351832 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.424253 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337121 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337121 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55716448 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55716448 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27857021 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27857021 # number of overall hits -system.cpu.icache.overall_hits::total 27857021 # number of overall hits +system.cpu.icache.tags.tag_accesses 55587246 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55587246 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27792420 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27792420 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27792420 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27792420 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27792420 # number of overall hits +system.cpu.icache.overall_hits::total 27792420 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27857823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27857823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27857823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60382998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60382998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60382998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60382998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60382998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60382998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27793222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27793222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27793222 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27793222 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27793222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27793222 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75290.521197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75290.521197 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,117 +593,117 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58977003 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58977003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58841002 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 58841002 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58841002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 58841002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58841002 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 58841002 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.355364 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.450791 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.428453 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312432 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13877 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15216337 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15216337 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903158 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903183 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 943266 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943266 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 935378 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935403 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 935378 # number of overall hits -system.cpu.l2cache.overall_hits::total 935403 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses +system.cpu.l2cache.tags.tag_accesses 15216684 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15216684 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903175 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903201 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 950184 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 950184 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74440.721649 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82233.778626 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76407.755299 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73813.961084 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73813.961084 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73986.747529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73986.747529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 47928250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17945750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65874000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891746250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891746250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47928250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 909692000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 957620250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47928250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 909692000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 957620250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61922.803618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70100.585938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63955.339806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61313.686056 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61313.686056 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2845301 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1894295 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1894295 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1894295 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1890436500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1372498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428685244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution @@ -814,9 +814,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21690500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82133750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index af9445aa2..c17d6c2b8 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.413669 # Number of seconds simulated -sim_ticks 413668621500 # Number of ticks simulated -final_tick 413668621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.413311 # Number of seconds simulated +sim_ticks 413311471500 # Number of ticks simulated +final_tick 413311471500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330001 # Simulator instruction rate (inst/s) -host_op_rate 330001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 223093103 # Simulator tick rate (ticks/s) -host_mem_usage 297764 # Number of bytes of host memory used -host_seconds 1854.24 # Real time elapsed on the host +host_inst_rate 320750 # Simulator instruction rate (inst/s) +host_op_rate 320750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216651718 # Simulator tick rate (ticks/s) +host_mem_usage 298932 # Number of bytes of host memory used +host_seconds 1907.72 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24149824 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724288 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377341 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380011 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292567 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292567 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 413084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58379637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58792721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 413084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 413084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45263979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45263979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45263979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 413084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58379637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104056701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380011 # Number of read requests accepted -system.physmem.writeReqs 292567 # Number of write requests accepted -system.physmem.readBursts 380011 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292567 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24296448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24256 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 379 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 170944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24150272 # Number of bytes read from this memory +system.physmem.bytes_read::total 24321216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724096 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377348 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380019 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292564 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292564 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 413596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58431168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58844764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 413596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 413596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45302628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45302628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45302628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 413596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58431168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104147392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380019 # Number of read requests accepted +system.physmem.writeReqs 292564 # Number of write requests accepted +system.physmem.readBursts 380019 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292564 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24298816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22400 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24321216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 350 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23738 # Per bank write bursts -system.physmem.perBankRdBursts::1 23215 # Per bank write bursts -system.physmem.perBankRdBursts::2 23512 # Per bank write bursts -system.physmem.perBankRdBursts::3 24525 # Per bank write bursts -system.physmem.perBankRdBursts::4 25461 # Per bank write bursts -system.physmem.perBankRdBursts::5 23591 # Per bank write bursts -system.physmem.perBankRdBursts::6 23667 # Per bank write bursts -system.physmem.perBankRdBursts::7 23972 # Per bank write bursts -system.physmem.perBankRdBursts::8 23176 # Per bank write bursts -system.physmem.perBankRdBursts::9 23948 # Per bank write bursts -system.physmem.perBankRdBursts::10 24672 # Per bank write bursts -system.physmem.perBankRdBursts::11 22745 # Per bank write bursts -system.physmem.perBankRdBursts::12 23724 # Per bank write bursts -system.physmem.perBankRdBursts::13 24415 # Per bank write bursts -system.physmem.perBankRdBursts::14 22805 # Per bank write bursts -system.physmem.perBankRdBursts::15 22466 # Per bank write bursts -system.physmem.perBankWrBursts::0 17754 # Per bank write bursts -system.physmem.perBankWrBursts::1 17430 # Per bank write bursts -system.physmem.perBankWrBursts::2 17902 # Per bank write bursts -system.physmem.perBankWrBursts::3 18771 # Per bank write bursts +system.physmem.perBankRdBursts::0 23743 # Per bank write bursts +system.physmem.perBankRdBursts::1 23222 # Per bank write bursts +system.physmem.perBankRdBursts::2 23516 # Per bank write bursts +system.physmem.perBankRdBursts::3 24520 # Per bank write bursts +system.physmem.perBankRdBursts::4 25462 # Per bank write bursts +system.physmem.perBankRdBursts::5 23584 # Per bank write bursts +system.physmem.perBankRdBursts::6 23675 # Per bank write bursts +system.physmem.perBankRdBursts::7 23980 # Per bank write bursts +system.physmem.perBankRdBursts::8 23177 # Per bank write bursts +system.physmem.perBankRdBursts::9 23949 # Per bank write bursts +system.physmem.perBankRdBursts::10 24669 # Per bank write bursts +system.physmem.perBankRdBursts::11 22747 # Per bank write bursts +system.physmem.perBankRdBursts::12 23729 # Per bank write bursts +system.physmem.perBankRdBursts::13 24425 # Per bank write bursts +system.physmem.perBankRdBursts::14 22797 # Per bank write bursts +system.physmem.perBankRdBursts::15 22474 # Per bank write bursts +system.physmem.perBankWrBursts::0 17756 # Per bank write bursts +system.physmem.perBankWrBursts::1 17433 # Per bank write bursts +system.physmem.perBankWrBursts::2 17901 # Per bank write bursts +system.physmem.perBankWrBursts::3 18770 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts -system.physmem.perBankWrBursts::5 18543 # Per bank write bursts -system.physmem.perBankWrBursts::6 18683 # Per bank write bursts -system.physmem.perBankWrBursts::7 18577 # Per bank write bursts +system.physmem.perBankWrBursts::5 18538 # Per bank write bursts +system.physmem.perBankWrBursts::6 18680 # Per bank write bursts +system.physmem.perBankWrBursts::7 18573 # Per bank write bursts system.physmem.perBankWrBursts::8 18350 # Per bank write bursts -system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19129 # Per bank write bursts +system.physmem.perBankWrBursts::9 18834 # Per bank write bursts +system.physmem.perBankWrBursts::10 19126 # Per bank write bursts system.physmem.perBankWrBursts::11 17963 # Per bank write bursts -system.physmem.perBankWrBursts::12 18222 # Per bank write bursts -system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::12 18227 # Per bank write bursts +system.physmem.perBankWrBursts::13 18693 # Per bank write bursts system.physmem.perBankWrBursts::14 17147 # Per bank write bursts -system.physmem.perBankWrBursts::15 17103 # Per bank write bursts +system.physmem.perBankWrBursts::15 17105 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 413668533000 # Total gap between requests +system.physmem.totGap 413311383000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380011 # Read request sizes (log2) +system.physmem.readPktSize::6 380019 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292567 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292564 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,47 +144,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17386 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -193,128 +193,128 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 301.943638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.238649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.808189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 51183 35.92% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38564 27.07% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13147 9.23% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8365 5.87% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5777 4.05% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3877 2.72% 84.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2993 2.10% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2580 1.81% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15987 11.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142473 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17260 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.993917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.515702 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17249 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142426 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.052266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.083619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.600685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51194 35.94% 35.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38668 27.15% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13205 9.27% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8199 5.76% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5653 3.97% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3753 2.64% 84.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3030 2.13% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2604 1.83% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16120 11.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142426 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17258 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.998378 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.944233 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17248 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 4 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17260 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17260 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.949189 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.879017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.574623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17060 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 147 0.85% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17258 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17258 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.950863 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.879940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.817078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17053 98.81% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 148 0.86% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 32 0.19% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 6 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17260 # Writes before turning the bus around for reads -system.physmem.totQLat 4063422250 # Total ticks spent queuing -system.physmem.totMemAccLat 11181522250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10703.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17258 # Writes before turning the bus around for reads +system.physmem.totQLat 4042656250 # Total ticks spent queuing +system.physmem.totMemAccLat 11161450000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10647.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29453.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29397.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.30 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.80 # Average write queue length when enqueuing -system.physmem.readRowHits 314502 # Number of row buffer hits during reads -system.physmem.writeRowHits 215198 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.56 # Row buffer hit rate for writes -system.physmem.avgGap 615049.16 # Average gap between requests -system.physmem.pageHitRate 78.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 548387280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299219250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1495111800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 953220960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62462923605 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 193408851750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 286186490325 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.826263 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 321201361250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13813280000 # Time in different power states +system.physmem.avgWrQLen 20.55 # Average write queue length when enqueuing +system.physmem.readRowHits 314442 # Number of row buffer hits during reads +system.physmem.writeRowHits 215335 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.60 # Row buffer hit rate for writes +system.physmem.avgGap 614513.57 # Average gap between requests +system.physmem.pageHitRate 78.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 549347400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 299743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1495252200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 953162640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62649847125 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 193029983250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285972717660 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.908567 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320566103500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13801320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78653522500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78943046000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 528708600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288481875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465971000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 942457680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59403829365 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196092272250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 285740496450 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.748106 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 325682433750 # Time in different power states -system.physmem_1.memoryStateTime::REF 13813280000 # Time in different power states +system.physmem_1.actEnergy 527378040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 287755875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1466010000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 942483600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59502215925 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195791063250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285512288610 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.794563 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 325183887500 # Time in different power states +system.physmem_1.memoryStateTime::REF 13801320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74172457500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74324788750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 124268150 # Number of BP lookups -system.cpu.branchPred.condPredicted 87927054 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6406473 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71778224 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67442624 # Number of BTB hits +system.cpu.branchPred.lookups 124207419 # Number of BP lookups +system.cpu.branchPred.condPredicted 87899229 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6403012 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71682632 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67406446 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.959728 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15063408 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126260 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.034558 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15055625 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126618 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149394774 # DTB read hits -system.cpu.dtb.read_misses 568338 # DTB read misses +system.cpu.dtb.read_hits 149439695 # DTB read hits +system.cpu.dtb.read_misses 564071 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149963112 # DTB read accesses -system.cpu.dtb.write_hits 57322660 # DTB write hits -system.cpu.dtb.write_misses 67060 # DTB write misses +system.cpu.dtb.read_accesses 150003766 # DTB read accesses +system.cpu.dtb.write_hits 57327469 # DTB write hits +system.cpu.dtb.write_misses 66798 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57389720 # DTB write accesses -system.cpu.dtb.data_hits 206717434 # DTB hits -system.cpu.dtb.data_misses 635398 # DTB misses +system.cpu.dtb.write_accesses 57394267 # DTB write accesses +system.cpu.dtb.data_hits 206767164 # DTB hits +system.cpu.dtb.data_misses 630869 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207352832 # DTB accesses -system.cpu.itb.fetch_hits 226805869 # ITB hits +system.cpu.dtb.data_accesses 207398033 # DTB accesses +system.cpu.itb.fetch_hits 226566802 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226805917 # ITB accesses +system.cpu.itb.fetch_accesses 226566850 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,82 +328,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 827337243 # number of cpu cycles simulated +system.cpu.numCycles 826622943 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12980749 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13262321 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.352076 # CPI: cycles per instruction -system.cpu.ipc 0.739604 # IPC: instructions per cycle -system.cpu.tickCycles 741744427 # Number of cycles that the object actually ticked -system.cpu.idleCycles 85592816 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535433 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.647440 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202630848 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.790720 # Average number of references to valid blocks. +system.cpu.cpi 1.350908 # CPI: cycles per instruction +system.cpu.ipc 0.740243 # IPC: instructions per cycle +system.cpu.tickCycles 740977624 # Number of cycles that the object actually ticked +system.cpu.idleCycles 85645319 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535493 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.640549 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202664153 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539589 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.801949 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1642835250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647440 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.640549 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414705331 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414705331 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146964653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146964653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666195 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666195 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202630848 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202630848 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202630848 # number of overall hits -system.cpu.dcache.overall_hits::total 202630848 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908214 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908214 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543839 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543839 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452053 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452053 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452053 # number of overall misses -system.cpu.dcache.overall_misses::total 3452053 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37787863500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37787863500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48074024750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48074024750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 85861888250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 85861888250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 85861888250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 85861888250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148872867 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148872867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414772189 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414772189 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146997943 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146997943 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666210 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666210 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202664153 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202664153 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202664153 # number of overall hits +system.cpu.dcache.overall_hits::total 202664153 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908323 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908323 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543824 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543824 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452147 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452147 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452147 # number of overall misses +system.cpu.dcache.overall_misses::total 3452147 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37798959500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37798959500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48016494500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48016494500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85815454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85815454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85815454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85815454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148906266 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148906266 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206082901 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206082901 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206082901 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206082901 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012818 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 206116300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206116300 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206116300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206116300 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012816 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012816 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016751 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016751 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19802.738844 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19802.738844 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31139.273428 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31139.273428 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24872.702780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24872.702780 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016749 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016749 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016749 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016749 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.422276 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.422276 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31102.311209 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31102.311209 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24858.574678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24858.574678 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,103 +412,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340050 # number of writebacks -system.cpu.dcache.writebacks::total 2340050 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143464 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143464 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769060 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769060 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912524 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912524 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912524 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912524 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764750 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764750 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774779 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774779 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539529 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539529 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539529 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539529 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32323432750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32323432750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23036899500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23036899500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55360332250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55360332250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55360332250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55360332250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2340079 # number of writebacks +system.cpu.dcache.writebacks::total 2340079 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143534 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143534 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769024 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769024 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912558 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912558 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912558 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912558 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764789 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764789 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774800 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774800 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539589 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539589 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539589 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539589 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32332751000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32332751000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23008045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23008045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55340796000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55340796000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55340796000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55340796000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011852 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011852 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18316.153988 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18316.153988 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29733.510459 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29733.510459 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012321 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012321 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18321.029313 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18321.029313 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29695.463345 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29695.463345 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3160 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.931154 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226800880 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4989 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45460.188415 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3154 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.871500 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226561819 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4983 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45466.951435 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.931154 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545865 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.871500 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545836 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545836 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1588 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453616727 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453616727 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49564.341551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49564.341551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49564.341551 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49584.487257 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49584.487257 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49584.487257 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49584.487257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49584.487257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49584.487257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47862.933976 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47862.933976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47862.933976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47862.933976 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 347300 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29504.344374 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3711084 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379724 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.773109 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189731783500 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265534 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.536022 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148586 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.149345 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.535177 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148587 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.536022 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148586 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.149345 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78404.119850 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80786.458425 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80749.772183 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78903.956908 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78903.956908 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78404.119850 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79755.630186 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79746.134322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78404.119850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79755.630186 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79746.134322 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78333.021340 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80828.718239 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80790.274630 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78767.432800 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78767.432800 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78333.021340 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79700.033523 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79690.425347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78333.021340 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79700.033523 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79690.425347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,105 +642,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292567 # number of writebacks -system.cpu.l2cache.writebacks::total 292567 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2670 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170715 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173385 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206626 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2670 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 377341 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380011 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2670 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 377341 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380011 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175922000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11655046250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11830968250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13719523500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13719523500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175922000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25374569750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25550491750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175922000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25374569750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25550491750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096921 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098158 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265538 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265538 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for demand accesses +system.cpu.l2cache.writebacks::writebacks 292564 # number of writebacks +system.cpu.l2cache.writebacks::total 292564 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2671 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170726 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 173397 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206622 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206622 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2671 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377348 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2671 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377348 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380019 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175804500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11663055250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11838859750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13690980000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13690980000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175804500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25354035250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25529839750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175804500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25354035250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25529839750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096924 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.149345 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.149345 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65888.389513 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68271.951791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68235.246705 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66397.856514 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66397.856514 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65819.730438 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68314.464405 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68276.035629 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66260.998345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66260.998345 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766378 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766378 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778140 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419108 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429086 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312293056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312612352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766434 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766434 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778138 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9966 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312298752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312617664 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884568 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884651 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884568 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884651 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884568 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782334000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884651 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782404500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8035000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8026500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891583750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891673000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173385 # Transaction distribution -system.membus.trans_dist::ReadResp 173385 # Transaction distribution -system.membus.trans_dist::Writeback 292567 # Transaction distribution -system.membus.trans_dist::ReadExReq 206626 # Transaction distribution -system.membus.trans_dist::ReadExResp 206626 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052589 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052589 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 173397 # Transaction distribution +system.membus.trans_dist::ReadResp 173397 # Transaction distribution +system.membus.trans_dist::Writeback 292564 # Transaction distribution +system.membus.trans_dist::ReadExReq 206622 # Transaction distribution +system.membus.trans_dist::ReadExResp 206622 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052602 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052602 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43045312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43045312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672578 # Request fanout histogram +system.membus.snoop_fanout::samples 672583 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672578 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 672583 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672578 # Request fanout histogram -system.membus.reqLayer0.occupancy 1986204500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 672583 # Request fanout histogram +system.membus.reqLayer0.occupancy 1984973000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2010997250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2011061250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index a54a6c0d4..41f3b60e2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366340 # Number of seconds simulated -sim_ticks 366339500500 # Number of ticks simulated -final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366030 # Number of seconds simulated +sim_ticks 366029674500 # Number of ticks simulated +final_tick 366029674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237525 # Simulator instruction rate (inst/s) -host_op_rate 257271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171768388 # Simulator tick rate (ticks/s) -host_mem_usage 317860 # Number of bytes of host memory used -host_seconds 2132.75 # Real time elapsed on the host +host_inst_rate 241467 # Simulator instruction rate (inst/s) +host_op_rate 261540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174471263 # Simulator tick rate (ticks/s) +host_mem_usage 317880 # Number of bytes of host memory used +host_seconds 2097.94 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 222208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9004736 # Number of bytes read from this memory -system.physmem.bytes_read::total 9226944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6180224 # Number of bytes written to this memory -system.physmem.bytes_written::total 6180224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3472 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140699 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144171 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96566 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96566 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 606563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24580303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25186866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16870209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16870209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16870209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24580303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42057075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144171 # Number of read requests accepted -system.physmem.writeReqs 96566 # Number of write requests accepted -system.physmem.readBursts 144171 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96566 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 6179072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9226944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6180224 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9008192 # Number of bytes read from this memory +system.physmem.bytes_read::total 9229632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6182144 # Number of bytes written to this memory +system.physmem.bytes_written::total 6182144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140753 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144213 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96596 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96596 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 604978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24610551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25215529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 604978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 604978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16889734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16889734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16889734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 604978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24610551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42105264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144213 # Number of read requests accepted +system.physmem.writeReqs 96596 # Number of write requests accepted +system.physmem.readBursts 144213 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96596 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9221696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue +system.physmem.bytesWritten 6180992 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9229632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6182144 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9343 # Per bank write bursts -system.physmem.perBankRdBursts::1 8971 # Per bank write bursts -system.physmem.perBankRdBursts::2 8989 # Per bank write bursts -system.physmem.perBankRdBursts::3 8699 # Per bank write bursts -system.physmem.perBankRdBursts::4 9456 # Per bank write bursts +system.physmem.perBankRdBursts::0 9409 # Per bank write bursts +system.physmem.perBankRdBursts::1 9017 # Per bank write bursts +system.physmem.perBankRdBursts::2 8952 # Per bank write bursts +system.physmem.perBankRdBursts::3 8679 # Per bank write bursts +system.physmem.perBankRdBursts::4 9455 # Per bank write bursts system.physmem.perBankRdBursts::5 9348 # Per bank write bursts -system.physmem.perBankRdBursts::6 8947 # Per bank write bursts -system.physmem.perBankRdBursts::7 8105 # Per bank write bursts -system.physmem.perBankRdBursts::8 8575 # Per bank write bursts -system.physmem.perBankRdBursts::9 8682 # Per bank write bursts -system.physmem.perBankRdBursts::10 8775 # Per bank write bursts -system.physmem.perBankRdBursts::11 9479 # Per bank write bursts -system.physmem.perBankRdBursts::12 9376 # Per bank write bursts -system.physmem.perBankRdBursts::13 9525 # Per bank write bursts -system.physmem.perBankRdBursts::14 8707 # Per bank write bursts -system.physmem.perBankRdBursts::15 9090 # Per bank write bursts -system.physmem.perBankWrBursts::0 6188 # Per bank write bursts -system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6005 # Per bank write bursts -system.physmem.perBankWrBursts::3 5814 # Per bank write bursts -system.physmem.perBankWrBursts::4 6162 # Per bank write bursts -system.physmem.perBankWrBursts::5 6175 # Per bank write bursts -system.physmem.perBankWrBursts::6 6015 # Per bank write bursts +system.physmem.perBankRdBursts::6 8942 # Per bank write bursts +system.physmem.perBankRdBursts::7 8103 # Per bank write bursts +system.physmem.perBankRdBursts::8 8564 # Per bank write bursts +system.physmem.perBankRdBursts::9 8678 # Per bank write bursts +system.physmem.perBankRdBursts::10 8771 # Per bank write bursts +system.physmem.perBankRdBursts::11 9482 # Per bank write bursts +system.physmem.perBankRdBursts::12 9373 # Per bank write bursts +system.physmem.perBankRdBursts::13 9523 # Per bank write bursts +system.physmem.perBankRdBursts::14 8716 # Per bank write bursts +system.physmem.perBankRdBursts::15 9077 # Per bank write bursts +system.physmem.perBankWrBursts::0 6225 # Per bank write bursts +system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankWrBursts::2 6004 # Per bank write bursts +system.physmem.perBankWrBursts::3 5808 # Per bank write bursts +system.physmem.perBankWrBursts::4 6164 # Per bank write bursts +system.physmem.perBankWrBursts::5 6178 # Per bank write bursts +system.physmem.perBankWrBursts::6 6016 # Per bank write bursts system.physmem.perBankWrBursts::7 5497 # Per bank write bursts -system.physmem.perBankWrBursts::8 5730 # Per bank write bursts -system.physmem.perBankWrBursts::9 5822 # Per bank write bursts -system.physmem.perBankWrBursts::10 5962 # Per bank write bursts -system.physmem.perBankWrBursts::11 6449 # Per bank write bursts -system.physmem.perBankWrBursts::12 6307 # Per bank write bursts -system.physmem.perBankWrBursts::13 6278 # Per bank write bursts -system.physmem.perBankWrBursts::14 5993 # Per bank write bursts -system.physmem.perBankWrBursts::15 6057 # Per bank write bursts +system.physmem.perBankWrBursts::8 5725 # Per bank write bursts +system.physmem.perBankWrBursts::9 5821 # Per bank write bursts +system.physmem.perBankWrBursts::10 5961 # Per bank write bursts +system.physmem.perBankWrBursts::11 6450 # Per bank write bursts +system.physmem.perBankWrBursts::12 6306 # Per bank write bursts +system.physmem.perBankWrBursts::13 6280 # Per bank write bursts +system.physmem.perBankWrBursts::14 5998 # Per bank write bursts +system.physmem.perBankWrBursts::15 6047 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366339471500 # Total gap between requests +system.physmem.totGap 366029646000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144171 # Read request sizes (log2) +system.physmem.readPktSize::6 144213 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96566 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96596 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 350 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5657 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,113 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.982530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.409511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.771416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24814 38.03% 38.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18186 27.87% 65.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6968 10.68% 76.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7930 12.15% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2060 3.16% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1157 1.77% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 782 1.20% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 601 0.92% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2757 4.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 65352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.682213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.342104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.346143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24838 38.01% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18259 27.94% 65.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6996 10.71% 76.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7952 12.17% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2091 3.20% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1098 1.68% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 757 1.16% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 602 0.92% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2759 4.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65352 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.846071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.003663 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5571 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.850018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.983730 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5570 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5574 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.321134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.221070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.354740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2655 47.63% 47.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2759 49.50% 97.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 73 1.31% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 16 0.29% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 14 0.25% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 15 0.27% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 8 0.14% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 5 0.09% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 9 0.16% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 2 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 2 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.326516 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.224346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.427330 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2648 47.51% 47.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2778 49.84% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 56 1.00% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 28 0.50% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 12 0.22% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 9 0.16% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 7 0.13% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.02% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::54-55 1 0.02% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-65 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5574 # Writes before turning the bus around for reads -system.physmem.totQLat 1547962750 # Total ticks spent queuing -system.physmem.totMemAccLat 4249219000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10744.74 # Average queueing delay per DRAM burst +system.physmem.totQLat 1545997750 # Total ticks spent queuing +system.physmem.totMemAccLat 4247666500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720445000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10729.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29494.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29479.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.89 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.89 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.02 # Average write queue length when enqueuing -system.physmem.readRowHits 110904 # Number of row buffer hits during reads -system.physmem.writeRowHits 64452 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing +system.physmem.readRowHits 110923 # Number of row buffer hits during reads +system.physmem.writeRowHits 64387 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes -system.physmem.avgGap 1521741.45 # Average gap between requests -system.physmem.pageHitRate 72.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247983120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135308250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560305200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310528080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47721013605 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177940783500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250843161195 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.736086 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295712636000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12232740000 # Time in different power states +system.physmem.writeRowHitRate 66.66 # Row buffer hit rate for writes +system.physmem.avgGap 1519999.86 # Average gap between requests +system.physmem.pageHitRate 72.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248708880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135704250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560640600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310761360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47751629445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 177727049250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250641390825 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.767505 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 295355626000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12222340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58390260500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58446120250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245095200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133732500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563066400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314791920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47027452140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178549170750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250760548350 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.510574 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296727601000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12232740000 # Time in different power states +system.physmem_1.actEnergy 245064960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133716000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562816800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314753040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47056905180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178336456500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250556609520 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.535877 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296372694500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12222340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57375209000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57429294500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132583064 # Number of BP lookups -system.cpu.branchPred.condPredicted 98508784 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6555218 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 69071756 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64847878 # Number of BTB hits +system.cpu.branchPred.lookups 132485545 # Number of BP lookups +system.cpu.branchPred.condPredicted 98435425 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6553959 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68727443 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64816198 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.884797 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10016520 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18156 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.309049 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10006764 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17617 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,98 +417,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 732679001 # number of cpu cycles simulated +system.cpu.numCycles 732059349 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13461102 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13911652 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446318 # CPI: cycles per instruction -system.cpu.ipc 0.691411 # IPC: instructions per cycle -system.cpu.tickCycles 695769824 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36909177 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139845 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.953673 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171282385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143941 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.730087 # Average number of references to valid blocks. +system.cpu.cpi 1.445095 # CPI: cycles per instruction +system.cpu.ipc 0.691996 # IPC: instructions per cycle +system.cpu.tickCycles 695000552 # Number of cycles that the object actually ticked +system.cpu.idleCycles 37058797 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139856 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.933719 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171285318 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143952 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.731211 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.953673 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.933719 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993880 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346819443 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346819443 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114763887 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114763887 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538651 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2765 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2765 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346825504 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346825504 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114766819 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114766819 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538648 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538648 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2769 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2769 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168302538 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168302538 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168305303 # number of overall hits -system.cpu.dcache.overall_hits::total 168305303 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854696 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854696 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700655 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700655 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555366 # number of overall misses -system.cpu.dcache.overall_misses::total 1555366 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025171732 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14025171732 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22048092000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22048092000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36073263732 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36073263732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36073263732 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36073263732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115618583 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115618583 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168305467 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168305467 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168308236 # number of overall hits +system.cpu.dcache.overall_hits::total 168308236 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854784 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854784 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700658 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700658 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555442 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555442 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555458 # number of overall misses +system.cpu.dcache.overall_misses::total 1555458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14034932732 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14034932732 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22036201250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22036201250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36071133982 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36071133982 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36071133982 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36071133982 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115621603 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115621603 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2780 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2780 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2785 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2785 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169857889 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169857889 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169860669 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169860669 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 169860909 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169860909 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169863694 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169863694 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005396 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005396 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005745 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005745 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.544133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.544133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31467.829388 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31467.829388 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23193.005136 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23193.005136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23192.781462 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23192.781462 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16419.274029 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16419.274029 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31450.723820 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31450.723820 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23190.279022 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23190.279022 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23190.040478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23190.040478 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,111 +517,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068547 # number of writebacks -system.cpu.dcache.writebacks::total 1068547 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66929 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66929 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344493 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344493 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411422 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411422 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3472 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140699 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144171 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 232222500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2786510500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3018733000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6677694250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6677694250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 232222500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9464204750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9696427250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 232222500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9464204750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9696427250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050561 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053638 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283044 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283044 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123913 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123913 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66884.360599 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69981.176855 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69732.802033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66193.775339 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66193.775339 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39847 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100906 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100906 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144213 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144213 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229496250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2794594500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3024090750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6671817000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6671817000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229496250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9466411500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9695907750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229496250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9466411500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9695907750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053657 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283115 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283115 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123946 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123946 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66328.395954 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70133.121690 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69829.144249 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66119.130676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66119.130676 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39088 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356429 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141599232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068580 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141602048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142854208 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232097 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2232032 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2232097 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2232097 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184628500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30009996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30040746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744692235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744732235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43290 # Transaction distribution -system.membus.trans_dist::ReadResp 43290 # Transaction distribution -system.membus.trans_dist::Writeback 96566 # Transaction distribution -system.membus.trans_dist::ReadExReq 100881 # Transaction distribution -system.membus.trans_dist::ReadExResp 100881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384908 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15407168 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43307 # Transaction distribution +system.membus.trans_dist::ReadResp 43307 # Transaction distribution +system.membus.trans_dist::Writeback 96596 # Transaction distribution +system.membus.trans_dist::ReadExReq 100906 # Transaction distribution +system.membus.trans_dist::ReadExResp 100906 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 385022 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15411776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15411776 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240737 # Request fanout histogram +system.membus.snoop_fanout::samples 240809 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240737 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240809 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240737 # Request fanout histogram -system.membus.reqLayer0.occupancy 679133000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 240809 # Request fanout histogram +system.membus.reqLayer0.occupancy 679106500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765318250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765494750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index bccf5186d..5e6582f7a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226866 # Number of seconds simulated -sim_ticks 226865901500 # Number of ticks simulated -final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226051 # Number of seconds simulated +sim_ticks 226051212500 # Number of ticks simulated +final_tick 226051212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 324605 # Simulator instruction rate (inst/s) -host_op_rate 324605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 184721178 # Simulator tick rate (ticks/s) -host_mem_usage 301676 # Number of bytes of host memory used -host_seconds 1228.15 # Real time elapsed on the host +host_inst_rate 313509 # Simulator instruction rate (inst/s) +host_op_rate 313509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177766322 # Simulator tick rate (ticks/s) +host_mem_usage 302576 # Number of bytes of host memory used +host_seconds 1271.62 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 249344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory -system.physmem.bytes_read::total 503872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 503936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7873 # Number of read requests accepted +system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1103042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1126258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1103042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1103042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1103042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1126258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7874 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 503936 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side +system.physmem.bytesReadSys 503936 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -49,7 +49,7 @@ system.physmem.perBankRdBursts::4 475 # Pe system.physmem.perBankRdBursts::5 478 # Per bank write bursts system.physmem.perBankRdBursts::6 563 # Per bank write bursts system.physmem.perBankRdBursts::7 560 # Per bank write bursts -system.physmem.perBankRdBursts::8 469 # Per bank write bursts +system.physmem.perBankRdBursts::8 470 # Per bank write bursts system.physmem.perBankRdBursts::9 437 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts system.physmem.perBankRdBursts::11 323 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226865813000 # Total gap between requests +system.physmem.totGap 226051111000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7873 # Read request sizes (log2) +system.physmem.readPktSize::6 7874 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6818 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation -system.physmem.totQLat 54380250 # Total ticks spent queuing -system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.964194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.457187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.645688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 541 34.59% 34.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 22.83% 57.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 194 12.40% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 101 6.46% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 4.16% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 55 3.52% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 2.24% 86.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34 2.17% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 182 11.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1564 # Bytes accessed per row activation +system.physmem.totQLat 54215500 # Total ticks spent queuing +system.physmem.totMemAccLat 201853000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6885.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25635.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6303 # Number of row buffer hits during reads +system.physmem.readRowHits 6308 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28815675.47 # Average gap between requests -system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28708548.51 # Average gap between requests +system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6872040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3749625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682686 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states +system.physmem_0.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5850636750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130498264500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151158364635 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.692398 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217093450250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7548320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1408913500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4951800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2701875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27042600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.490749 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states -system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states +system.physmem_1.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5592917520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130724334000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151116461715 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.507029 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 217471574500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7548320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030789250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46273750 # Number of BP lookups -system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits +system.cpu.branchPred.lookups 46270925 # Number of BP lookups +system.cpu.branchPred.condPredicted 26727379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1017826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21360644 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.374580 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341960 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95585469 # DTB read hits -system.cpu.dtb.read_misses 115 # DTB read misses +system.cpu.dtb.read_hits 95612151 # DTB read hits +system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95585584 # DTB read accesses -system.cpu.dtb.write_hits 73606437 # DTB write hits -system.cpu.dtb.write_misses 857 # DTB write misses +system.cpu.dtb.read_accesses 95612267 # DTB read accesses +system.cpu.dtb.write_hits 73605971 # DTB write hits +system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73607294 # DTB write accesses -system.cpu.dtb.data_hits 169191906 # DTB hits -system.cpu.dtb.data_misses 972 # DTB misses +system.cpu.dtb.write_accesses 73606829 # DTB write accesses +system.cpu.dtb.data_hits 169218122 # DTB hits +system.cpu.dtb.data_misses 974 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169192878 # DTB accesses -system.cpu.itb.fetch_hits 98781212 # ITB hits -system.cpu.itb.fetch_misses 1236 # ITB misses +system.cpu.dtb.data_accesses 169219096 # DTB accesses +system.cpu.itb.fetch_hits 98739643 # ITB hits +system.cpu.itb.fetch_misses 1232 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98782448 # ITB accesses +system.cpu.itb.fetch_accesses 98740875 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 453731803 # number of cpu cycles simulated +system.cpu.numCycles 452102425 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4488157 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.138129 # CPI: cycles per instruction -system.cpu.ipc 0.878635 # IPC: instructions per cycle -system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.134042 # CPI: cycles per instruction +system.cpu.ipc 0.881802 # IPC: instructions per cycle +system.cpu.tickCycles 448265843 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3836582 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.681680 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168032891 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40344.031453 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.681680 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits -system.cpu.dcache.overall_hits::total 168028622 # number of overall hits +system.cpu.dcache.tags.tag_accesses 336084169 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336084169 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94518092 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94518092 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168032891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168032891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168032891 # number of overall hits +system.cpu.dcache.overall_hits::total 168032891 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses -system.cpu.dcache.overall_misses::total 7112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7111 # number of overall misses +system.cpu.dcache.overall_misses::total 7111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88098000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88098000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 432683750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 432683750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 520781750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 520781750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 520781750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 520781750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94519272 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94519272 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168035734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168035734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168040002 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168040002 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168040002 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168040002 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74659.322034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74659.322034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72952.916877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72952.916877 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73236.077907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73236.077907 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2946 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2946 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2946 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2946 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69978250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 69978250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 238524000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 238524000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308502250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 308502250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308502250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 308502250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72216.976264 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72216.976264 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74632.040050 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74632.040050 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3197 # number of replacements +system.cpu.icache.tags.tagsinuse 1918.668517 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98734468 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19079.124251 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668517 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits -system.cpu.icache.overall_hits::total 98776038 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses -system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 320697250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 320697250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 320697250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 320697250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 320697250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 320697250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98781212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98781212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98781212 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 197484461 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197484461 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98734468 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98734468 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98734468 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98734468 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98734468 # number of overall hits +system.cpu.icache.overall_hits::total 98734468 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses +system.cpu.icache.overall_misses::total 5175 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 322926000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 322926000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 322926000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 322926000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 322926000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 322926000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98739643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98739643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98739643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98739643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98739643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98739643 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61982.460379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61982.460379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61982.460379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61982.460379 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62401.159420 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62401.159420 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62401.159420 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62401.159420 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,52 +482,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5174 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5174 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5174 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311289750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 311289750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311289750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 311289750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311289750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 311289750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5175 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5175 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5175 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5175 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5175 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5175 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 313513500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 313513500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 313513500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 313513500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 313513500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 313513500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60164.234635 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60164.234635 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60582.318841 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60582.318841 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60582.318841 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60582.318841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60582.318841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60582.318841 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.526265 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4426.539250 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.283276 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.084024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.466195 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 641.976046 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 373.086855 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.473471 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.978924 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 88415 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 88415 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 88424 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 88424 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits @@ -541,63 +541,63 @@ system.cpu.l2cache.demand_hits::total 1466 # nu system.cpu.l2cache.overall_hits::cpu.inst 1279 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits system.cpu.l2cache.overall_hits::total 1466 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3895 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3896 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 841 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4736 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4737 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3896 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses +system.cpu.l2cache.demand_misses::total 7874 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3896 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses -system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 292685750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 68346250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 361032000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 236421750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 236421750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 292685750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 304768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 597453750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 292685750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 304768000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 597453750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 7874 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 294908500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 67534250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 362442750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234806000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 234806000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 294908500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 302340250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 597248750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 294908500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 302340250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 597248750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5175 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 6142 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5174 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5175 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9339 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5174 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9340 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5175 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9339 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752802 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 9340 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752850 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.771210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.771247 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752850 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.843041 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752850 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75143.966624 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81267.835910 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76231.418919 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75365.556264 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75365.556264 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75886.415598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75886.415598 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.843041 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75695.200205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80302.318668 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76513.141229 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74850.494103 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74850.494103 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75850.742951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75850.742951 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,102 +606,102 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3895 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3896 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4736 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3896 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7874 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3896 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 243926750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 57790750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301717500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 197209250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 197209250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 243926750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 255000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 498926750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 243926750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 255000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 498926750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7874 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 246135500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56978250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 303113750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 195592000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 195592000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246135500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252570250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498705750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246135500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252570250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498705750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771247 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63176.463039 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67750.594530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63988.547604 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62350.015939 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62350.015939 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10350 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19332 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 639552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9993 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9994 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9993 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9994 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9994 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5651000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8587500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7035750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4736 # Transaction distribution -system.membus.trans_dist::ReadResp 4736 # Transaction distribution +system.membus.trans_dist::ReadReq 4737 # Transaction distribution +system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 503936 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7873 # Request fanout histogram +system.membus.snoop_fanout::samples 7874 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7874 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7874 # Request fanout histogram +system.membus.reqLayer0.occupancy 9179500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41811750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 592625271..572510825 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216744 # Number of seconds simulated -sim_ticks 216744260000 # Number of ticks simulated -final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216140 # Number of seconds simulated +sim_ticks 216139917000 # Number of ticks simulated +final_tick 216139917000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172626 # Simulator instruction rate (inst/s) -host_op_rate 207257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137034779 # Simulator tick rate (ticks/s) -host_mem_usage 322768 # Number of bytes of host memory used -host_seconds 1581.67 # Real time elapsed on the host +host_inst_rate 173188 # Simulator instruction rate (inst/s) +host_op_rate 207931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137097336 # Simulator tick rate (ticks/s) +host_mem_usage 323040 # Number of bytes of host memory used +host_seconds 1576.54 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7583 # Number of read requests accepted +system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1013862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1232387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2246249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1013862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1013862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1013862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1232387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2246249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7586 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::1 843 # Pe system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts -system.physmem.perBankRdBursts::5 348 # Per bank write bursts +system.physmem.perBankRdBursts::5 349 # Per bank write bursts system.physmem.perBankRdBursts::6 173 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts @@ -55,8 +55,8 @@ system.physmem.perBankRdBursts::10 342 # Pe system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts -system.physmem.perBankRdBursts::14 637 # Per bank write bursts -system.physmem.perBankRdBursts::15 540 # Per bank write bursts +system.physmem.perBankRdBursts::14 638 # Per bank write bursts +system.physmem.perBankRdBursts::15 541 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216744023500 # Total gap between requests +system.physmem.totGap 216139680500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7583 # Read request sizes (log2) +system.physmem.readPktSize::6 7586 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation -system.physmem.totQLat 54921500 # Total ticks spent queuing -system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.319107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.795582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.243204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 551 36.18% 36.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.72% 58.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 176 11.56% 70.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 81 5.32% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 75 4.92% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.28% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.10% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.84% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation +system.physmem.totQLat 53007250 # Total ticks spent queuing +system.physmem.totMemAccLat 195244750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6987.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25737.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6057 # Number of row buffer hits during reads +system.physmem.readRowHits 6060 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28582885.86 # Average gap between requests +system.physmem.avgGap 28491916.75 # Average gap between requests system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 5004720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2730750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 30022200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.684406 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states +system.physmem_0.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5648540400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124728404250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144531819360 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.699173 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 207494790250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7217340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1426657250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6509160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3551625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29062800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.812768 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states +system.physmem_1.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5781551040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124611728250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144549519915 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.781068 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207298156250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7217340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1623563250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33185861 # Number of BP lookups -system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits +system.cpu.branchPred.lookups 33139216 # Number of BP lookups +system.cpu.branchPred.condPredicted 17107199 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1560655 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17520877 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15610870 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 89.098679 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6611023 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,81 +377,81 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433488520 # number of cpu cycles simulated +system.cpu.numCycles 432279834 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4207498 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.587650 # CPI: cycles per instruction -system.cpu.ipc 0.629862 # IPC: instructions per cycle -system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.583223 # CPI: cycles per instruction +system.cpu.ipc 0.631623 # IPC: instructions per cycle +system.cpu.tickCycles 428628441 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3651393 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.737950 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168771151 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37413.245622 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.737950 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337561379 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337561379 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86638362 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86638362 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047459 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047459 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits -system.cpu.dcache.overall_hits::total 168747655 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168685821 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168685821 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168749361 # number of overall hits +system.cpu.dcache.overall_hits::total 168749361 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5218 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5218 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses -system.cpu.dcache.overall_misses::total 7285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7277 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7277 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7283 # number of overall misses +system.cpu.dcache.overall_misses::total 7283 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136967456 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136967456 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400451000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400451000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537418456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537418456 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537418456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537418456 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86640421 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86640421 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168693098 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168693098 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168756644 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168756644 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73851.649856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73790.808183 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2348 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2348 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2770 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2770 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2770 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2770 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507 system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108888792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 108888792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220256750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220256750 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329145542 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329145542 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329466292 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329466292 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36918 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36928 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.841098 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73108223 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38865 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1881.081256 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.841098 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits -system.cpu.icache.overall_hits::total 73120141 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses -system.cpu.icache.overall_misses::total 38856 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 146333043 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146333043 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73108223 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73108223 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73108223 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73108223 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.175900 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75132.589025 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77410 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75776.329564 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76098.020322 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76098.020322 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75896.657929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75896.657929 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,102 +725,102 @@ system.cpu.l2cache.demand_mshr_hits::total 44 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3424 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4729 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4732 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214398750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85427750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 299826500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181482250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181482250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214398750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266910000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 481308750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214398750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266910000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 481308750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116819 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174885 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174885 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40507 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40506 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77731 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2840704 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44387 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44387 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44387 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23203500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 59023248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7574708 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4729 # Transaction distribution -system.membus.trans_dist::ReadResp 4729 # Transaction distribution +system.membus.trans_dist::ReadReq 4732 # Transaction distribution +system.membus.trans_dist::ReadResp 4732 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7583 # Request fanout histogram +system.membus.snoop_fanout::samples 7586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7583 # Request fanout histogram -system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7586 # Request fanout histogram +system.membus.reqLayer0.occupancy 8848500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40266750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index f83552a37..efccfaef5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.561963 # Number of seconds simulated -sim_ticks 561962991000 # Number of ticks simulated -final_tick 561962991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.561049 # Number of seconds simulated +sim_ticks 561048999000 # Number of ticks simulated +final_tick 561048999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333136 # Simulator instruction rate (inst/s) -host_op_rate 333136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 201563357 # Simulator tick rate (ticks/s) -host_mem_usage 305440 # Number of bytes of host memory used -host_seconds 2788.02 # Real time elapsed on the host +host_inst_rate 327042 # Simulator instruction rate (inst/s) +host_op_rate 327042 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197554566 # Simulator tick rate (ticks/s) +host_mem_usage 305844 # Number of bytes of host memory used +host_seconds 2839.97 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 186944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory -system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18657344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2921 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291521 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 332435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32867645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33200080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 332435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 332435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7594294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7594294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7594294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 332435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32867645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40794373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291519 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 333204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 32921189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33254393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7606665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7606665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7606665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 32921189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40861059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291521 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291521 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18640576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18639104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18657344 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17933 # Per bank write bursts -system.physmem.perBankRdBursts::1 18288 # Per bank write bursts -system.physmem.perBankRdBursts::2 18309 # Per bank write bursts -system.physmem.perBankRdBursts::3 18250 # Per bank write bursts -system.physmem.perBankRdBursts::4 18165 # Per bank write bursts -system.physmem.perBankRdBursts::5 18241 # Per bank write bursts -system.physmem.perBankRdBursts::6 18322 # Per bank write bursts -system.physmem.perBankRdBursts::7 18300 # Per bank write bursts -system.physmem.perBankRdBursts::8 18229 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts -system.physmem.perBankRdBursts::10 18214 # Per bank write bursts -system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::0 17937 # Per bank write bursts +system.physmem.perBankRdBursts::1 18285 # Per bank write bursts +system.physmem.perBankRdBursts::2 18301 # Per bank write bursts +system.physmem.perBankRdBursts::3 18253 # Per bank write bursts +system.physmem.perBankRdBursts::4 18160 # Per bank write bursts +system.physmem.perBankRdBursts::5 18247 # Per bank write bursts +system.physmem.perBankRdBursts::6 18325 # Per bank write bursts +system.physmem.perBankRdBursts::7 18297 # Per bank write bursts +system.physmem.perBankRdBursts::8 18227 # Per bank write bursts +system.physmem.perBankRdBursts::9 18224 # Per bank write bursts +system.physmem.perBankRdBursts::10 18215 # Per bank write bursts +system.physmem.perBankRdBursts::11 18384 # Per bank write bursts system.physmem.perBankRdBursts::12 18260 # Per bank write bursts -system.physmem.perBankRdBursts::13 18047 # Per bank write bursts +system.physmem.perBankRdBursts::13 18042 # Per bank write bursts system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18105 # Per bank write bursts +system.physmem.perBankRdBursts::15 18099 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4189 # Per bank write bursts +system.physmem.perBankWrBursts::9 4188 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 561962908000 # Total gap between requests +system.physmem.totGap 561048916000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291519 # Read request sizes (log2) +system.physmem.readPktSize::6 291521 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290732 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4041 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4041 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,118 +193,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 106018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216.046030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 139.156746 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 265.673827 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41726 39.36% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42732 40.31% 79.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8674 8.18% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 811 0.76% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1515 1.43% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1173 1.11% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 577 0.54% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 518 0.49% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8292 7.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 106018 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.199159 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.197763 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.963064 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 105209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 217.703657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.847395 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 266.018983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39852 37.88% 37.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43676 41.51% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8737 8.30% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 846 0.80% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1608 1.53% 90.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1088 1.03% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 546 0.52% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 586 0.56% 92.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8270 7.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105209 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.193764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.202156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.629260 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4034 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471396 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.862526 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3046 75.36% 75.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 995 24.62% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2975536250 # Total ticks spent queuing -system.physmem.totMemAccLat 8436642500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10216.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4041 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.496907 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.475096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.865198 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3038 75.18% 75.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1001 24.77% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4041 # Writes before turning the bus around for reads +system.physmem.totQLat 2859634000 # Total ticks spent queuing +system.physmem.totMemAccLat 8320309000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9818.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28966.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28568.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing -system.physmem.readRowHits 201381 # Number of row buffer hits during reads -system.physmem.writeRowHits 50515 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes -system.physmem.avgGap 1568843.58 # Average gap between requests -system.physmem.pageHitRate 70.37 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 399311640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 217878375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136904600 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing +system.physmem.readRowHits 202235 # Number of row buffer hits during reads +system.physmem.writeRowHits 50448 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.65 # Row buffer hit rate for writes +system.physmem.avgGap 1566283.22 # Average gap between requests +system.physmem.pageHitRate 70.60 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 396718560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 216463500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1137021600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 110801606310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 239979977250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 389456417535 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.035628 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 398531952000 # Time in different power states -system.physmem_0.memoryStateTime::REF 18764980000 # Time in different power states +system.physmem_0.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 109036341675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240981860250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388629643425 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.687306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 400213963500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18734560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 144660363000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142097780250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 402093720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 219396375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134346200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 111289898520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 239551650750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 389517237165 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.143857 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 397813996000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18764980000 # Time in different power states +system.physmem_1.actEnergy 398601000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 217490625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134307200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 109322809425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240730572750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388664124600 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.748765 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399791677000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18734560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 145378777500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 142520871000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749002 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144241 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157248 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103981751 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513628 # Number of BTB hits +system.cpu.branchPred.lookups 125749073 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144364 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157127 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103970968 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513050 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.315658 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.323432 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691036 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537715 # DTB read hits -system.cpu.dtb.read_misses 198475 # DTB read misses +system.cpu.dtb.read_hits 237538495 # DTB read hits +system.cpu.dtb.read_misses 198467 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736190 # DTB read accesses -system.cpu.dtb.write_hits 98305031 # DTB write hits -system.cpu.dtb.write_misses 7188 # DTB write misses +system.cpu.dtb.read_accesses 237736962 # DTB read accesses +system.cpu.dtb.write_hits 98305062 # DTB write hits +system.cpu.dtb.write_misses 7206 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312219 # DTB write accesses -system.cpu.dtb.data_hits 335842746 # DTB hits -system.cpu.dtb.data_misses 205663 # DTB misses +system.cpu.dtb.write_accesses 98312268 # DTB write accesses +system.cpu.dtb.data_hits 335843557 # DTB hits +system.cpu.dtb.data_misses 205673 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048409 # DTB accesses -system.cpu.itb.fetch_hits 317139351 # ITB hits +system.cpu.dtb.data_accesses 336049230 # DTB accesses +system.cpu.itb.fetch_hits 316986664 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 317139471 # ITB accesses +system.cpu.itb.fetch_accesses 316986784 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,83 +317,83 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1123925982 # number of cpu cycles simulated +system.cpu.numCycles 1122097998 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 27043469 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30863568 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.210098 # CPI: cycles per instruction -system.cpu.ipc 0.826379 # IPC: instructions per cycle -system.cpu.tickCycles 1060172068 # Number of cycles that the object actually ticked -system.cpu.idleCycles 63753914 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.208130 # CPI: cycles per instruction +system.cpu.ipc 0.827726 # IPC: instructions per cycle +system.cpu.tickCycles 1059712720 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62385278 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.699416 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 323503203 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.688853 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322867255 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 414.414040 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 905250250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.699416 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999194 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999194 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 413.599378 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 907886250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.688853 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999192 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999192 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1647 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 649485188 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 649485188 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 225339151 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 225339151 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164052 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164052 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 323503203 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 323503203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 323503203 # number of overall hits -system.cpu.dcache.overall_hits::total 323503203 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648213290 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648213290 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224703202 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224703202 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164053 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164053 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322867255 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322867255 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322867255 # number of overall hits +system.cpu.dcache.overall_hits::total 322867255 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137148 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137148 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849077 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849077 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849077 # number of overall misses -system.cpu.dcache.overall_misses::total 849077 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24941013500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24941013500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10047073750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10047073750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34988087250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34988087250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34988087250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34988087250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 226051080 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 226051080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137147 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849076 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849076 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849076 # number of overall misses +system.cpu.dcache.overall_misses::total 849076 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24858122500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24858122500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10112031250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10112031250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34970153750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34970153750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34970153750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34970153750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225415131 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225415131 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 324352280 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 324352280 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 324352280 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 324352280 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 323716331 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323716331 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323716331 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323716331 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35033.006803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35033.006803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73257.165617 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73257.165617 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41207.201761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41207.201761 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34916.575248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34916.575248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73731.333897 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73731.333897 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41186.129098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41186.129098 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,12 +406,12 @@ system.cpu.dcache.writebacks::writebacks 91489 # nu system.cpu.dcache.writebacks::total 91489 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68137 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68137 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68449 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68136 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68136 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68448 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68448 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68448 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68448 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -421,85 +420,85 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23795842750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23795842750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4974141500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4974141500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28769984250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28769984250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28769984250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28769984250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23712269000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23712269000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5006644750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5006644750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28718913750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28718913750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28718913750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28718913750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33439.115072 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33439.115072 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72077.516628 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72077.516628 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33321.673035 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33321.673035 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72548.503137 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72548.503137 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10603 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.326033 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 317127004 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25686.619472 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10608 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.311703 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316974313 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25665.936275 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.326033 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823890 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823890 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.311703 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1575 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 634291048 # Number of tag accesses -system.cpu.icache.tags.data_accesses 634291048 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 317127004 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 317127004 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 317127004 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 317127004 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 317127004 # number of overall hits -system.cpu.icache.overall_hits::total 317127004 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12347 # number of overall misses -system.cpu.icache.overall_misses::total 12347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 354892250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 354892250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 354892250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 354892250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 354892250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 354892250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 317139351 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 317139351 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 317139351 # 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average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.367629 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76758.384668 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80463.102881 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80414.964625 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73715.406257 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73715.406257 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76758.384668 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78904.889986 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78883.375011 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76758.384668 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78904.889986 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78883.375011 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,103 +634,103 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2920 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2922 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221955 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224877 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2920 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2922 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 288600 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2922 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187160250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15168425250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15355585500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4046889000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4046889000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187160250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19215314250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19402474500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187160250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19215314250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19402474500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 291522 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15084314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15271976000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4079380750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4079380750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187662000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19163694750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19351356750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187662000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19163694750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19351356750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310616 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310617 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367628 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367629 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367628 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64095.976027 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68340.092586 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68284.982768 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60723.069998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60723.069998 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64223.819302 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67961.136266 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67912.574430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61210.604697 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61210.604697 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 723968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723967 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24693 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56605888 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884464 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 884468 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884464 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884468 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884464 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533721000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 884468 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 533723000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19157750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19161500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1221759250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222147750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224874 # Transaction distribution -system.membus.trans_dist::ReadResp 224874 # Transaction distribution +system.membus.trans_dist::ReadReq 224876 # Transaction distribution +system.membus.trans_dist::ReadResp 224876 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649721 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649721 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22924928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649725 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649725 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22925056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22925056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358202 # Request fanout histogram +system.membus.snoop_fanout::samples 358204 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 358204 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 667013500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 358204 # Request fanout histogram +system.membus.reqLayer0.occupancy 732288500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1552224500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1552393250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index f250ad066..5b9278fb0 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.545048 # Number of seconds simulated -sim_ticks 545048444500 # Number of ticks simulated -final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541773 # Number of seconds simulated +sim_ticks 541773299500 # Number of ticks simulated +final_tick 541773299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177094 # Simulator instruction rate (inst/s) -host_op_rate 218026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 150665678 # Simulator tick rate (ticks/s) +host_inst_rate 180126 # Simulator instruction rate (inst/s) +host_op_rate 221759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152324877 # Simulator tick rate (ticks/s) host_mem_usage 323140 # Number of bytes of host memory used -host_seconds 3617.60 # Real time elapsed on the host +host_seconds 3556.70 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18429312 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429120 # Number of bytes read from this memory +system.physmem.bytes_read::total 18593920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164800 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287958 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2575 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287955 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290530 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 301889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33812246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34114135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 301889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 301889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7761277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7761277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7761277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 301889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33812246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41875412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290529 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 304186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34016294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34320481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 304186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 304186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7808196 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7808196 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7808196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 304186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34016294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42128676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290530 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290530 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18574272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18593920 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18284 # Per bank write bursts -system.physmem.perBankRdBursts::1 18137 # Per bank write bursts +system.physmem.perBankRdBursts::0 18288 # Per bank write bursts +system.physmem.perBankRdBursts::1 18136 # Per bank write bursts system.physmem.perBankRdBursts::2 18223 # Per bank write bursts -system.physmem.perBankRdBursts::3 18185 # Per bank write bursts -system.physmem.perBankRdBursts::4 18266 # Per bank write bursts -system.physmem.perBankRdBursts::5 18315 # Per bank write bursts -system.physmem.perBankRdBursts::6 18094 # Per bank write bursts -system.physmem.perBankRdBursts::7 17909 # Per bank write bursts -system.physmem.perBankRdBursts::8 17941 # Per bank write bursts +system.physmem.perBankRdBursts::3 18182 # Per bank write bursts +system.physmem.perBankRdBursts::4 18272 # Per bank write bursts +system.physmem.perBankRdBursts::5 18313 # Per bank write bursts +system.physmem.perBankRdBursts::6 18098 # Per bank write bursts +system.physmem.perBankRdBursts::7 17913 # Per bank write bursts +system.physmem.perBankRdBursts::8 17942 # Per bank write bursts system.physmem.perBankRdBursts::9 17963 # Per bank write bursts -system.physmem.perBankRdBursts::10 18019 # Per bank write bursts -system.physmem.perBankRdBursts::11 18118 # Per bank write bursts -system.physmem.perBankRdBursts::12 18147 # Per bank write bursts -system.physmem.perBankRdBursts::13 18275 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18266 # Per bank write bursts +system.physmem.perBankRdBursts::10 18020 # Per bank write bursts +system.physmem.perBankRdBursts::11 18117 # Per bank write bursts +system.physmem.perBankRdBursts::12 18146 # Per bank write bursts +system.physmem.perBankRdBursts::13 18271 # Per bank write bursts +system.physmem.perBankRdBursts::14 18079 # Per bank write bursts +system.physmem.perBankRdBursts::15 18260 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts system.physmem.perBankWrBursts::3 4147 # Per bank write bursts -system.physmem.perBankWrBursts::4 4226 # Per bank write bursts +system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4095 # Per bank write bursts -system.physmem.perBankWrBursts::9 4090 # Per bank write bursts -system.physmem.perBankWrBursts::10 4090 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::9 4092 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::11 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 545048350000 # Total gap between requests +system.physmem.totGap 541773205000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290529 # Read request sizes (log2) +system.physmem.readPktSize::6 290530 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,19 +144,19 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see @@ -193,97 +193,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 112309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 203.026151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.211216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 254.422571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47277 42.10% 42.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43772 38.97% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8960 7.98% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1911 1.70% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 490 0.44% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 736 0.66% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 729 0.65% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 499 0.44% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7935 7.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 112309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 112123 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.355529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.415015 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.574164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47170 42.07% 42.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43612 38.90% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9039 8.06% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1917 1.71% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 483 0.43% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 738 0.66% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 730 0.65% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 502 0.45% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7932 7.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 112123 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 48.524570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.056534 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.518625 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.058155 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.570273 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.482415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.461068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.856030 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3042 75.88% 75.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 75.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 965 24.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.480918 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.459590 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855706 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3046 75.98% 75.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 961 23.97% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads -system.physmem.totQLat 2724193250 # Total ticks spent queuing -system.physmem.totMemAccLat 8165799500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451095000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9386.68 # Average queueing delay per DRAM burst +system.physmem.totQLat 2883248250 # Total ticks spent queuing +system.physmem.totMemAccLat 8324929500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9934.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28136.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28684.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing -system.physmem.readRowHits 193908 # Number of row buffer hits during reads -system.physmem.writeRowHits 50072 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes -system.physmem.avgGap 1528342.92 # Average gap between requests -system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 423889200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 231288750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1134182400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 106422668235 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 233674110000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 377701475625 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.972318 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 388027097500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18200260000 # Time in different power states +system.physmem.avgWrQLen 25.18 # Average write queue length when enqueuing +system.physmem.readRowHits 194064 # Number of row buffer hits during reads +system.physmem.writeRowHits 50094 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes +system.physmem.avgGap 1519154.99 # Average gap between requests +system.physmem.pageHitRate 68.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 423874080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 231280500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134198000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215622000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 107588305125 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 230684814750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375663699255 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.403859 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 383052702750 # Time in different power states +system.physmem_0.memoryStateTime::REF 18090800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 138818528500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 140624192250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 425113920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231957000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1129245000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212556960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 106328346345 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 233756848500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 377683776285 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.939845 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 388162097500 # Time in different power states -system.physmem_1.memoryStateTime::REF 18200260000 # Time in different power states +system.physmem_1.actEnergy 423692640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231181500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129104600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212524560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 107075040930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 231135046500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 375592195530 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.271876 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 383804077000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18090800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 138683202500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 139874284500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 155052076 # Number of BP lookups -system.cpu.branchPred.condPredicted 105344550 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12879569 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90401009 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82966187 # Number of BTB hits +system.cpu.branchPred.lookups 156119313 # Number of BP lookups +system.cpu.branchPred.condPredicted 106151666 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12881666 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90098747 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82494804 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.775731 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19284792 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.560434 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19276925 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1327 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,69 +401,69 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1090096889 # number of cpu cycles simulated +system.cpu.numCycles 1083546599 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 22623818 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23911488 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.701535 # CPI: cycles per instruction -system.cpu.ipc 0.587705 # IPC: instructions per cycle -system.cpu.tickCycles 1030366439 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59730450 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778156 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.460333 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378456871 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782252 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.804287 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460333 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy +system.cpu.cpi 1.691310 # CPI: cycles per instruction +system.cpu.ipc 0.591258 # IPC: instructions per cycle +system.cpu.tickCycles 1025165387 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58381212 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778275 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.437677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378454072 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782371 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.727122 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 802618250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.437677 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999130 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1345 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1586 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759399046 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759399046 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249628143 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249628143 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 759393811 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759393811 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249625343 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249625343 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378441908 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378441908 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378445393 # number of overall hits -system.cpu.dcache.overall_hits::total 378445393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713673 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713673 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 378439109 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378439109 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378442594 # number of overall hits +system.cpu.dcache.overall_hits::total 378442594 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713796 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713796 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 851385 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851385 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851526 # number of overall misses -system.cpu.dcache.overall_misses::total 851526 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24678796218 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24678796218 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10203720250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10203720250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34882516468 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34882516468 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34882516468 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34882516468 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250341816 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250341816 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 851507 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851507 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851648 # number of overall misses +system.cpu.dcache.overall_misses::total 851648 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24839025218 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24839025218 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10202615750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10202615750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35041640968 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35041640968 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35041640968 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35041640968 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250339139 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250339139 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) @@ -473,10 +472,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379293293 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379293293 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379296919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379296919 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379290616 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379290616 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379294242 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379294242 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -487,14 +486,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34579.977410 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34579.977410 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74094.634091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74094.634091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40971.495232 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40971.495232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.710964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40964.710964 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34798.493152 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34798.493152 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74087.151716 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74087.151716 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41152.499002 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41152.499002 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41145.685739 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41145.685739 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,107 +504,107 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 882 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 882 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712791 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712791 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 886 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 886 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69275 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69275 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69275 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69275 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712910 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712910 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782113 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782113 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782252 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782252 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23523501277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23523501277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5052240750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5052240750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782232 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782232 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782371 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782371 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23683196777 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23683196777 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5051765250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5051765250 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28575742027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28575742027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28577461027 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28577461027 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28734962027 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28734962027 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28736681027 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28736681027 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038334 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038334 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33001.961693 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33001.961693 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72880.770174 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72880.770174 # average WriteReq mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33220.458090 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33220.458090 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72873.910880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72873.910880 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36536.590016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36536.590016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36532.295254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36532.295254 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36734.577500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36734.577500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36730.248216 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36730.248216 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23595 # number of replacements -system.cpu.icache.tags.tagsinuse 1710.136306 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 292011682 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11521.925584 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23596 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.059457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 290105857 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11445.372510 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1710.136306 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835027 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835027 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.059457 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835967 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835967 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1601 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854004 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 584099398 # Number of tag accesses -system.cpu.icache.tags.data_accesses 584099398 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 292011682 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 292011682 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 292011682 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 292011682 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 292011682 # number of overall hits -system.cpu.icache.overall_hits::total 292011682 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25345 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78471.218707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75831.102057 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78471.218707 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101823 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368089 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359733 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101823 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368089 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359733 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76066.156528 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80285.553492 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80237.038473 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74874.275620 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74874.275620 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76066.156528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79043.681550 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79017.232924 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76066.156528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79043.681550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79017.232924 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -750,103 +749,103 @@ system.cpu.l2cache.demand_mshr_hits::total 32 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2572 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221867 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221864 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287958 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287958 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 162876000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14878894250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15041770250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4120650250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4120650250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 162876000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18999544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19162420500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 162876000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18999544500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19162420500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304005 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2576 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287955 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290531 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2576 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287955 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290531 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163738000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15037461500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15201199500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4120172250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4120172250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163738000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19157633750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19321371750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163738000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19157633750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19321371750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311148 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303956 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359746 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359746 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63326.594090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67062.223089 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67019.413961 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62348.129851 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62348.129851 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359693 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359693 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63562.888199 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67777.834619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67729.457762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62340.897399 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62340.897399 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738274 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 738397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738396 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50689 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655924 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55915008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656162 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706857 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55922624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57544832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 899139 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 899139 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 899139 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 540989500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38568245 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38573245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224009973 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224491973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224438 # Transaction distribution -system.membus.trans_dist::ReadResp 224438 # Transaction distribution +system.membus.trans_dist::ReadReq 224439 # Transaction distribution +system.membus.trans_dist::ReadResp 224439 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647158 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824192 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356627 # Request fanout histogram +system.membus.snoop_fanout::samples 356628 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 356628 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356627 # Request fanout histogram -system.membus.reqLayer0.occupancy 732101500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 356628 # Request fanout histogram +system.membus.reqLayer0.occupancy 731800000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551130500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1550863750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index acacb719c..bd4df05db 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059745 # Number of seconds simulated -sim_ticks 59744560000 # Number of ticks simulated -final_tick 59744560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059732 # Number of seconds simulated +sim_ticks 59731559000 # Number of ticks simulated +final_tick 59731559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 336953 # Simulator instruction rate (inst/s) -host_op_rate 336953 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 227629544 # Simulator tick rate (ticks/s) -host_mem_usage 304552 # Number of bytes of host memory used -host_seconds 262.46 # Real time elapsed on the host +host_inst_rate 330143 # Simulator instruction rate (inst/s) +host_op_rate 330143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 222980587 # Simulator tick rate (ticks/s) +host_mem_usage 304704 # Number of bytes of host memory used +host_seconds 267.88 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 517248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory -system.physmem.bytes_read::total 10665024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 517248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 517248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166641 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8657659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169852720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178510378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8657659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8657659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122170253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122170253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122170253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8657659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169852720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 300680631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166641 # Number of read requests accepted -system.physmem.writeReqs 114047 # Number of write requests accepted -system.physmem.readBursts 166641 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10664448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10665024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 516416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10147392 # Number of bytes read from this memory +system.physmem.bytes_read::total 10663808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 516416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 516416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7298880 # Number of bytes written to this memory +system.physmem.bytes_written::total 7298880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158553 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166622 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114045 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114045 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8645614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169883261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178528874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8645614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8645614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122194701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122194701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122194701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8645614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169883261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 300723576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166622 # Number of read requests accepted +system.physmem.writeReqs 114045 # Number of write requests accepted +system.physmem.readBursts 166622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114045 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10663168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10663808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7298880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10464 # Per bank write bursts -system.physmem.perBankRdBursts::1 10514 # Per bank write bursts -system.physmem.perBankRdBursts::2 10315 # Per bank write bursts -system.physmem.perBankRdBursts::3 10095 # Per bank write bursts -system.physmem.perBankRdBursts::4 10432 # Per bank write bursts -system.physmem.perBankRdBursts::5 10431 # Per bank write bursts -system.physmem.perBankRdBursts::6 9850 # Per bank write bursts -system.physmem.perBankRdBursts::7 10303 # Per bank write bursts -system.physmem.perBankRdBursts::8 10594 # Per bank write bursts -system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10596 # Per bank write bursts -system.physmem.perBankRdBursts::11 10260 # Per bank write bursts +system.physmem.perBankRdBursts::0 10463 # Per bank write bursts +system.physmem.perBankRdBursts::1 10512 # Per bank write bursts +system.physmem.perBankRdBursts::2 10314 # Per bank write bursts +system.physmem.perBankRdBursts::3 10093 # Per bank write bursts +system.physmem.perBankRdBursts::4 10430 # Per bank write bursts +system.physmem.perBankRdBursts::5 10428 # Per bank write bursts +system.physmem.perBankRdBursts::6 9849 # Per bank write bursts +system.physmem.perBankRdBursts::7 10305 # Per bank write bursts +system.physmem.perBankRdBursts::8 10593 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10591 # Per bank write bursts +system.physmem.perBankRdBursts::11 10259 # Per bank write bursts system.physmem.perBankRdBursts::12 10303 # Per bank write bursts -system.physmem.perBankRdBursts::13 10654 # Per bank write bursts +system.physmem.perBankRdBursts::13 10653 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts system.physmem.perBankRdBursts::15 10649 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts -system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7178 # Per bank write bursts +system.physmem.perBankWrBursts::4 7125 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7080 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6940 # Per bank write bursts -system.physmem.perBankWrBursts::10 7097 # Per bank write bursts -system.physmem.perBankWrBursts::11 6990 # Per bank write bursts -system.physmem.perBankWrBursts::12 6967 # Per bank write bursts +system.physmem.perBankWrBursts::7 7091 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7094 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 6965 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7283 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59744533000 # Total gap between requests +system.physmem.totGap 59731532000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166641 # Read request sizes (log2) +system.physmem.readPktSize::6 166622 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114047 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114045 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6196 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7041 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -193,121 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.521940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.158907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.861003 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19447 35.57% 35.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11824 21.63% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5661 10.35% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3636 6.65% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2772 5.07% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2160 3.95% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1686 3.08% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1520 2.78% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5967 10.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54673 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.740134 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.174119 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54759 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.975602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.612520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.469121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19499 35.61% 35.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11959 21.84% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5687 10.39% 67.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3574 6.53% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2717 4.96% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2083 3.80% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1679 3.07% 86.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1528 2.79% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6033 11.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54759 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.742625 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.245058 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7015 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.245939 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.230597 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.737975 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 17 0.24% 89.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 574 8.18% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 144 2.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 20 0.28% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.249109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.233383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.749815 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6248 89.04% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.26% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 569 8.11% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 155 2.21% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 21 0.30% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads -system.physmem.totQLat 1983100250 # Total ticks spent queuing -system.physmem.totMemAccLat 5107450250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11901.08 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7017 # Writes before turning the bus around for reads +system.physmem.totQLat 1993187750 # Total ticks spent queuing +system.physmem.totMemAccLat 5117162750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11963.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30651.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30713.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.35 # Data bus utilization in percentage system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing -system.physmem.readRowHits 144723 # Number of row buffer hits during reads -system.physmem.writeRowHits 81251 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes -system.physmem.avgGap 212850.33 # Average gap between requests -system.physmem.pageHitRate 80.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199115280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108644250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 642735600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367778880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12699594585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24706498500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42626547975 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.484810 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40950314500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1994980000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.13 # Average write queue length when enqueuing +system.physmem.readRowHits 144646 # Number of row buffer hits during reads +system.physmem.writeRowHits 81220 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.22 # Row buffer hit rate for writes +system.physmem.avgGap 212819.93 # Average gap between requests +system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199621800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108920625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 642564000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367681680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12761553015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24642806250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42624311130 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.633365 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40844346250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1994460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16799112000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16889792000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214197480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116873625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 656962800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371031840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13192492680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24274131750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42727871055 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.180760 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40226086750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1994980000 # Time in different power states +system.physmem_1.actEnergy 214235280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116894250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 656728800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370960560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13264546950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24201582750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42726112350 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.337777 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40104532750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1994460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17523103250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17629849250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14679718 # Number of BP lookups -system.cpu.branchPred.condPredicted 9498983 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 392764 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10434122 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6393495 # Number of BTB hits +system.cpu.branchPred.lookups 14669488 # Number of BP lookups +system.cpu.branchPred.condPredicted 9491497 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 392361 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10408467 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6389552 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.274873 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1709689 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85822 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.388022 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708748 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85394 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20566953 # DTB read hits -system.cpu.dtb.read_misses 96874 # DTB read misses -system.cpu.dtb.read_acv 11 # DTB read access violations -system.cpu.dtb.read_accesses 20663827 # DTB read accesses -system.cpu.dtb.write_hits 14666692 # DTB write hits -system.cpu.dtb.write_misses 9419 # DTB write misses +system.cpu.dtb.read_hits 20569996 # DTB read hits +system.cpu.dtb.read_misses 97344 # DTB read misses +system.cpu.dtb.read_acv 10 # DTB read access violations +system.cpu.dtb.read_accesses 20667340 # DTB read accesses +system.cpu.dtb.write_hits 14665866 # DTB write hits +system.cpu.dtb.write_misses 9405 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14676111 # DTB write accesses -system.cpu.dtb.data_hits 35233645 # DTB hits -system.cpu.dtb.data_misses 106293 # DTB misses -system.cpu.dtb.data_acv 11 # DTB access violations -system.cpu.dtb.data_accesses 35339938 # DTB accesses -system.cpu.itb.fetch_hits 25640132 # ITB hits -system.cpu.itb.fetch_misses 5244 # ITB misses +system.cpu.dtb.write_accesses 14675271 # DTB write accesses +system.cpu.dtb.data_hits 35235862 # DTB hits +system.cpu.dtb.data_misses 106749 # DTB misses +system.cpu.dtb.data_acv 10 # DTB access violations +system.cpu.dtb.data_accesses 35342611 # DTB accesses +system.cpu.itb.fetch_hits 25629903 # ITB hits +system.cpu.itb.fetch_misses 5247 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25645376 # ITB accesses +system.cpu.itb.fetch_accesses 25635150 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,81 +321,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119489120 # number of cpu cycles simulated +system.cpu.numCycles 119463118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1100288 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1109771 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.351105 # CPI: cycles per instruction -system.cpu.ipc 0.740135 # IPC: instructions per cycle -system.cpu.tickCycles 91601603 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27887517 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200784 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.582702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34615842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204880 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.956667 # Average number of references to valid blocks. +system.cpu.cpi 1.350811 # CPI: cycles per instruction +system.cpu.ipc 0.740296 # IPC: instructions per cycle +system.cpu.tickCycles 91541167 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27921951 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200768 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.577182 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616116 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204864 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.971200 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.582702 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993795 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.577182 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993793 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 679 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3369 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70175650 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70175650 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282569 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282569 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333273 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333273 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34615842 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34615842 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34615842 # number of overall hits -system.cpu.dcache.overall_hits::total 34615842 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89439 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89439 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280104 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280104 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369543 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369543 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369543 # number of overall misses -system.cpu.dcache.overall_misses::total 369543 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4793461000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4793461000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21859170750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21859170750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26652631750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26652631750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26652631750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26652631750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70176158 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176158 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616116 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616116 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616116 # number of overall hits +system.cpu.dcache.overall_hits::total 34616116 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89415 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89415 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses +system.cpu.dcache.overall_misses::total 369531 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4791422750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4791422750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21873540250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21873540250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26664963000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26664963000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26664963000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26664963000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372270 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372270 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985385 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985385 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985385 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985385 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 34985647 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985647 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985647 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985647 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53594.751730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53594.751730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78039.480871 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78039.480871 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72123.221790 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72123.221790 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53586.341777 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53586.341777 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78087.436098 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78087.436098 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72158.933892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72158.933892 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,102 +404,102 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168547 # number of writebacks -system.cpu.dcache.writebacks::total 168547 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28118 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136545 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61321 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61321 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143559 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143559 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204880 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204880 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204880 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204880 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2650982250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2650982250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10919810750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10919810750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13570793000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13570793000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13570793000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13570793000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 168537 # number of writebacks +system.cpu.dcache.writebacks::total 168537 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136551 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136551 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164667 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164667 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164667 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164667 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61299 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61299 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143565 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143565 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204864 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204864 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204864 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204864 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2648121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2648121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10930365250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10930365250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13578486750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13578486750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13578486750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13578486750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 25474875 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155027 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.325408 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42450985250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.259039 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51436170 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51436170 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25484225 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25484225 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25484225 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25484225 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25484225 # number of overall hits -system.cpu.icache.overall_hits::total 25484225 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155907 # 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miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16580.645782 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16580.645782 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16580.645782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16580.645782 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51414833 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51414833 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25474875 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25474875 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25474875 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25474875 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68774.383014 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68681.847644 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66863.785626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68774.383014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68681.847644 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 217227 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 217226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143560 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578307 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9977984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33877312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 216326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143566 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310055 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 888320 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9921728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33819392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 529334 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 528429 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 529334 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 528429 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 529334 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 433214000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 528429 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 432751500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 235419242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234095242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343262500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343202250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35759 # Transaction distribution -system.membus.trans_dist::ReadResp 35759 # Transaction distribution -system.membus.trans_dist::Writeback 114047 # Transaction distribution +system.membus.trans_dist::ReadReq 35740 # Transaction distribution +system.membus.trans_dist::ReadResp 35740 # Transaction distribution +system.membus.trans_dist::Writeback 114045 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447329 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447329 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17964032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17964032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447289 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17962688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280688 # Request fanout histogram +system.membus.snoop_fanout::samples 280667 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280667 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280688 # Request fanout histogram -system.membus.reqLayer0.occupancy 817068000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 280667 # Request fanout histogram +system.membus.reqLayer0.occupancy 816993000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 879892750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 879772000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 12a478a63..c3c27d986 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057717 # Number of seconds simulated -sim_ticks 57716694500 # Number of ticks simulated -final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057148 # Number of seconds simulated +sim_ticks 57147901500 # Number of ticks simulated +final_tick 57147901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194770 # Simulator instruction rate (inst/s) -host_op_rate 249082 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158520150 # Simulator tick rate (ticks/s) -host_mem_usage 322420 # Number of bytes of host memory used -host_seconds 364.10 # Real time elapsed on the host +host_inst_rate 198372 # Simulator instruction rate (inst/s) +host_op_rate 253689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159860838 # Simulator tick rate (ticks/s) +host_mem_usage 323444 # Number of bytes of host memory used +host_seconds 357.49 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128867 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5615290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137280765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142896056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5615290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5615290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 93092511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 93092511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 93092511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5615290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137280765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235988567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128867 # Number of read requests accepted -system.physmem.writeReqs 83953 # Number of write requests accepted -system.physmem.readBursts 128867 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247488 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 324160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923136 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123799 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5672299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138642641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144314940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5672299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5672299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94015701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94015701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94015701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5672299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138642641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 238330641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128864 # Number of read requests accepted +system.physmem.writeReqs 83950 # Number of write requests accepted +system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5370816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8373 # Per bank write bursts -system.physmem.perBankRdBursts::2 8230 # Per bank write bursts +system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::1 8375 # Per bank write bursts +system.physmem.perBankRdBursts::2 8229 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8318 # Per bank write bursts -system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::4 8317 # Per bank write bursts +system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8089 # Per bank write bursts -system.physmem.perBankRdBursts::7 7972 # Per bank write bursts -system.physmem.perBankRdBursts::8 8072 # Per bank write bursts +system.physmem.perBankRdBursts::7 7970 # Per bank write bursts +system.physmem.perBankRdBursts::8 8070 # Per bank write bursts system.physmem.perBankRdBursts::9 7639 # Per bank write bursts system.physmem.perBankRdBursts::10 7818 # Per bank write bursts -system.physmem.perBankRdBursts::11 7829 # Per bank write bursts +system.physmem.perBankRdBursts::11 7830 # Per bank write bursts system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7878 # Per bank write bursts -system.physmem.perBankRdBursts::14 7976 # Per bank write bursts -system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5185 # Per bank write bursts -system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankRdBursts::13 7879 # Per bank write bursts +system.physmem.perBankRdBursts::14 7978 # Per bank write bursts +system.physmem.perBankRdBursts::15 8005 # Per bank write bursts +system.physmem.perBankWrBursts::0 5181 # Per bank write bursts +system.physmem.perBankWrBursts::1 5374 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts -system.physmem.perBankWrBursts::5 5518 # Per bank write bursts -system.physmem.perBankWrBursts::6 5200 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::5 5517 # Per bank write bursts +system.physmem.perBankWrBursts::6 5197 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5254 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5225 # Per bank write bursts +system.physmem.perBankWrBursts::15 5224 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57716659500 # Total gap between requests +system.physmem.totGap 57147867000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128867 # Read request sizes (log2) +system.physmem.readPktSize::6 128864 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83953 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83950 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5188 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.703274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.932875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.531195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12049 31.39% 31.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8167 21.27% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4156 10.83% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2841 7.40% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2531 6.59% 77.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1630 4.25% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1300 3.39% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1165 3.03% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4550 11.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38389 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.991854 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.399783 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38410 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.471023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.710692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.512328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12078 31.44% 31.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8121 21.14% 52.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4196 10.92% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2833 7.38% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2487 6.47% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 4.39% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1308 3.41% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1147 2.99% 88.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4553 11.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38410 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.969750 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.703721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5155 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.278898 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.261929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.774840 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4519 87.65% 87.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 495 9.60% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 111 2.15% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 19 0.37% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads -system.physmem.totQLat 1645819000 # Total ticks spent queuing -system.physmem.totMemAccLat 4061944000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12772.15 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.272833 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.766988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4532 87.88% 87.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 8 0.16% 88.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 487 9.44% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 109 2.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 13 0.25% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.08% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1657207000 # Total ticks spent queuing +system.physmem.totMemAccLat 4073313250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12860.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31522.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 93.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31610.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 93.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 94.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.84 # Data bus utilization in percentage -system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.86 # Data bus utilization in percentage +system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing -system.physmem.readRowHits 112172 # Number of row buffer hits during reads -system.physmem.writeRowHits 62224 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes -system.physmem.avgGap 271199.41 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 151063920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82425750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512577000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272309040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11829284955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24250601250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40867708635 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.132582 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40213391000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing +system.physmem.readRowHits 112198 # Number of row buffer hits during reads +system.physmem.writeRowHits 62160 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes +system.physmem.avgGap 268534.34 # Average gap between requests +system.physmem.pageHitRate 81.93 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 150580080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82161750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512592600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11751586830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23977725000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40479283620 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.378781 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39762160500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1908140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15571447750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15473270000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139058640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75875250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492008400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 139769280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76263000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492016200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11209873365 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24793944750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40751686725 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.122220 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41121510500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11244014370 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24422958750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40378823040 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.620851 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40500942500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1908140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14663764500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14734649500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14827145 # Number of BP lookups -system.cpu.branchPred.condPredicted 9920468 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 395132 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9565987 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6746821 # Number of BTB hits +system.cpu.branchPred.lookups 14823153 # Number of BP lookups +system.cpu.branchPred.condPredicted 9921447 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 393425 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9508830 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6745421 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.529272 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1718856 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.938496 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1716328 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,97 +404,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115433389 # number of cpu cycles simulated +system.cpu.numCycles 114295803 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1146778 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1165738 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.627768 # CPI: cycles per instruction -system.cpu.ipc 0.614338 # IPC: instructions per cycle -system.cpu.tickCycles 96895866 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18537523 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156436 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.344190 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42626825 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.534753 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 829717250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.344190 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993004 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993004 # Average percentage of cache occupancy +system.cpu.cpi 1.611727 # CPI: cycles per instruction +system.cpu.ipc 0.620453 # IPC: instructions per cycle +system.cpu.tickCycles 95732462 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18563341 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156421 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.059654 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42628242 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160517 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.568395 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 829804250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.059654 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992934 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992934 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2911 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2909 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86020072 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86020072 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22868301 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22868301 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84507 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86023319 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86023319 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22869697 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22869697 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642191 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642191 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84516 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84516 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42510480 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42510480 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42594987 # number of overall hits -system.cpu.dcache.overall_hits::total 42594987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 43690 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 43690 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 302945 # number of overall misses -system.cpu.dcache.overall_misses::total 302945 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1474342937 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1474342937 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16908501000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16908501000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18382843937 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18382843937 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18382843937 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18382843937 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22919834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22919834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42511888 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42511888 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42596404 # number of overall hits +system.cpu.dcache.overall_hits::total 42596404 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51738 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51738 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207710 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 43711 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 43711 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259448 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259448 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303159 # number of overall misses +system.cpu.dcache.overall_misses::total 303159 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1479377187 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1479377187 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16921529000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16921529000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18400906187 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18400906187 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18400906187 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18400906187 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22921435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22921435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128197 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128197 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128227 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128227 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42769735 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42769735 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42897932 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42897932 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340804 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.340804 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28609.685774 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28609.685774 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81399.663974 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81399.663974 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70906.420077 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70906.420077 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60680.466543 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60680.466543 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42771336 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42771336 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42899563 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42899563 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002257 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002257 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340888 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.340888 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007067 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007067 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28593.629189 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28593.629189 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81467.088729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81467.088729 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70923.291708 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70923.291708 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60697.212311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60697.212311 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,110 +503,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks -system.cpu.dcache.writebacks::total 128445 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22036 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22036 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100688 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100688 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122724 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122724 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122724 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29497 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29497 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24001 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 24001 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136531 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136531 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558577313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 558577313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8440191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8440191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682073500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682073500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8998768313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8998768313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10680841813 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10680841813 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128425 # number of writebacks +system.cpu.dcache.writebacks::total 128425 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22255 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22255 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100680 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100680 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122935 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122935 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122935 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122935 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29483 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29483 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24004 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24004 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136513 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136513 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160517 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160517 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 559151063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 559151063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8446390250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8446390250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1684744250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1684744250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9005541313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9005541313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10690285563 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10690285563 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187220 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187220 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187199 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187199 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18936.749941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18936.749941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78855.232917 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78855.232917 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70083.475689 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70083.475689 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65910.073998 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65910.073998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66534.035663 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66534.035663 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18965.202422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18965.202422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78916.100626 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78916.100626 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70185.979420 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70185.979420 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65968.378931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65968.378931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66599.086471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66599.086471 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42847 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.482229 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25082964 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44889 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 558.777518 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42924 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.595671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24987535 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.698417 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1854.482229 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.905509 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.905509 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.595671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904588 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904588 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 916 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50300597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50300597 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25082964 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25082964 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25082964 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25082964 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25082964 # number of overall hits -system.cpu.icache.overall_hits::total 25082964 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44890 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44890 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44890 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44890 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44890 # number of overall misses -system.cpu.icache.overall_misses::total 44890 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 936252739 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 936252739 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 936252739 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 936252739 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 936252739 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 936252739 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25127854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25127854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25127854 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25127854 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25127854 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25127854 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001786 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001786 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001786 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001786 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001786 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001786 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20856.599220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20856.599220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20856.599220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20856.599220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20856.599220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20856.599220 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50109970 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50109970 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24987535 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24987535 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24987535 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24987535 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24987535 # number of overall hits +system.cpu.icache.overall_hits::total 24987535 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44967 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,114 +740,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83953 # number of writebacks -system.cpu.l2cache.writebacks::total 83953 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks +system.cpu.l2cache.writebacks::total 83950 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5065 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26588 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5065 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5065 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339808000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1578466750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1918274750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7004628000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7004628000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339808000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8583094750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8922902750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339808000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8583094750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8922902750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402314 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270236 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627333 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627333 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67089.437315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73338.602890 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72148.140138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68484.825968 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68484.825968 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5066 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26587 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102278 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102278 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5066 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123799 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5066 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123799 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342787750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1580541000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923328750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7010820250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7010820250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342787750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8591361250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8934149000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342787750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8591361250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8934149000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402359 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270045 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627129 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627129 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67664.380182 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73441.801032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72340.946703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68546.708481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68546.708481 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98388 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98387 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449509 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 539288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2872896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98453 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89933 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2877824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21370112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333909 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 333867 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 333909 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333909 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295379500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68292739 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68407488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268237687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268248937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26587 # Transaction distribution -system.membus.trans_dist::ReadResp 26587 # Transaction distribution -system.membus.trans_dist::Writeback 83953 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 26586 # Transaction distribution +system.membus.trans_dist::ReadResp 26586 # Transaction distribution +system.membus.trans_dist::Writeback 83950 # Transaction distribution +system.membus.trans_dist::ReadExReq 102278 # Transaction distribution +system.membus.trans_dist::ReadExResp 102278 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341678 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212820 # Request fanout histogram +system.membus.snoop_fanout::samples 212814 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212820 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212814 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212820 # Request fanout histogram -system.membus.reqLayer0.occupancy 578469000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212814 # Request fanout histogram +system.membus.reqLayer0.occupancy 578378500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 680054250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 680081000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 520a2b090..959bae132 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.211624 # Number of seconds simulated -sim_ticks 1211624479500 # Number of ticks simulated -final_tick 1211624479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.211096 # Number of seconds simulated +sim_ticks 1211096219500 # Number of ticks simulated +final_tick 1211096219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333436 # Simulator instruction rate (inst/s) -host_op_rate 333436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 221202175 # Simulator tick rate (ticks/s) -host_mem_usage 295444 # Number of bytes of host memory used -host_seconds 5477.45 # Real time elapsed on the host +host_inst_rate 325701 # Simulator instruction rate (inst/s) +host_op_rate 325701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215976885 # Simulator tick rate (ticks/s) +host_mem_usage 296636 # Number of bytes of host memory used +host_seconds 5607.53 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125444544 # Number of bytes read from this memory -system.physmem.bytes_read::total 125505792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65167616 # Number of bytes written to this memory -system.physmem.bytes_written::total 65167616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018244 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018244 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103534178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103584728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 53785325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 53785325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 53785325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103534178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157370053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961028 # Number of read requests accepted -system.physmem.writeReqs 1018244 # Number of write requests accepted -system.physmem.readBursts 1961028 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018244 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125424064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81728 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125505792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65167616 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1277 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125445568 # Number of bytes read from this memory +system.physmem.bytes_read::total 125506880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65168832 # Number of bytes written to this memory +system.physmem.bytes_written::total 65168832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960087 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961045 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018263 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018263 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103580183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103630808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 53809789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 53809789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 53809789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103580183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157440597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961045 # Number of read requests accepted +system.physmem.writeReqs 1018263 # Number of write requests accepted +system.physmem.readBursts 1961045 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018263 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125425280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81600 # Total number of bytes read from write queue +system.physmem.bytesWritten 65167232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125506880 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65168832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1275 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118746 # Per bank write bursts -system.physmem.perBankRdBursts::1 114093 # Per bank write bursts -system.physmem.perBankRdBursts::2 116238 # Per bank write bursts -system.physmem.perBankRdBursts::3 117765 # Per bank write bursts -system.physmem.perBankRdBursts::4 117832 # Per bank write bursts -system.physmem.perBankRdBursts::5 117522 # Per bank write bursts -system.physmem.perBankRdBursts::6 119888 # Per bank write bursts -system.physmem.perBankRdBursts::7 124523 # Per bank write bursts +system.physmem.perBankRdBursts::0 118758 # Per bank write bursts +system.physmem.perBankRdBursts::1 114090 # Per bank write bursts +system.physmem.perBankRdBursts::2 116233 # Per bank write bursts +system.physmem.perBankRdBursts::3 117775 # Per bank write bursts +system.physmem.perBankRdBursts::4 117826 # Per bank write bursts +system.physmem.perBankRdBursts::5 117520 # Per bank write bursts +system.physmem.perBankRdBursts::6 119879 # Per bank write bursts +system.physmem.perBankRdBursts::7 124540 # Per bank write bursts system.physmem.perBankRdBursts::8 126979 # Per bank write bursts -system.physmem.perBankRdBursts::9 130092 # Per bank write bursts -system.physmem.perBankRdBursts::10 128645 # Per bank write bursts -system.physmem.perBankRdBursts::11 130343 # Per bank write bursts -system.physmem.perBankRdBursts::12 126054 # Per bank write bursts -system.physmem.perBankRdBursts::13 125251 # Per bank write bursts -system.physmem.perBankRdBursts::14 122593 # Per bank write bursts -system.physmem.perBankRdBursts::15 123187 # Per bank write bursts -system.physmem.perBankWrBursts::0 61219 # Per bank write bursts -system.physmem.perBankWrBursts::1 61484 # Per bank write bursts -system.physmem.perBankWrBursts::2 60571 # Per bank write bursts -system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61659 # Per bank write bursts +system.physmem.perBankRdBursts::9 130098 # Per bank write bursts +system.physmem.perBankRdBursts::10 128644 # Per bank write bursts +system.physmem.perBankRdBursts::11 130342 # Per bank write bursts +system.physmem.perBankRdBursts::12 126070 # Per bank write bursts +system.physmem.perBankRdBursts::13 125249 # Per bank write bursts +system.physmem.perBankRdBursts::14 122589 # Per bank write bursts +system.physmem.perBankRdBursts::15 123178 # Per bank write bursts +system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankWrBursts::1 61482 # Per bank write bursts +system.physmem.perBankWrBursts::2 60569 # Per bank write bursts +system.physmem.perBankWrBursts::3 61241 # Per bank write bursts +system.physmem.perBankWrBursts::4 61665 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts -system.physmem.perBankWrBursts::6 64152 # Per bank write bursts -system.physmem.perBankWrBursts::7 65616 # Per bank write bursts -system.physmem.perBankWrBursts::8 65335 # Per bank write bursts -system.physmem.perBankWrBursts::9 65774 # Per bank write bursts -system.physmem.perBankWrBursts::10 65298 # Per bank write bursts -system.physmem.perBankWrBursts::11 65641 # Per bank write bursts -system.physmem.perBankWrBursts::12 64170 # Per bank write bursts -system.physmem.perBankWrBursts::13 64210 # Per bank write bursts -system.physmem.perBankWrBursts::14 64569 # Per bank write bursts -system.physmem.perBankWrBursts::15 64187 # Per bank write bursts +system.physmem.perBankWrBursts::6 64149 # Per bank write bursts +system.physmem.perBankWrBursts::7 65619 # Per bank write bursts +system.physmem.perBankWrBursts::8 65334 # Per bank write bursts +system.physmem.perBankWrBursts::9 65779 # Per bank write bursts +system.physmem.perBankWrBursts::10 65299 # Per bank write bursts +system.physmem.perBankWrBursts::11 65645 # Per bank write bursts +system.physmem.perBankWrBursts::12 64166 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64570 # Per bank write bursts +system.physmem.perBankWrBursts::15 64186 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1211624362000 # Total gap between requests +system.physmem.totGap 1211096102000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961028 # Read request sizes (log2) +system.physmem.readPktSize::6 1961045 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018244 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1838105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121629 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018263 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1837965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59990 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 59955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 59992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -193,130 +193,129 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1839318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.618163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.033976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.636069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1460921 79.43% 79.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261839 14.24% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49211 2.68% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20654 1.12% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12987 0.71% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7330 0.40% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5324 0.29% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4553 0.25% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16499 0.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1839318 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59419 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.981269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 162.030420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59379 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1839625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.602019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.031630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.543213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1461173 79.43% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261967 14.24% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48998 2.66% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20657 1.12% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13124 0.71% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7476 0.41% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5272 0.29% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4494 0.24% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16464 0.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1839625 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59444 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.966456 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 164.214090 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59406 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59419 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59419 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.136337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.100269 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.116106 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27590 46.43% 46.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1250 2.10% 48.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26098 43.92% 92.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3967 6.68% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 431 0.73% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 63 0.11% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 13 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59419 # Writes before turning the bus around for reads -system.physmem.totQLat 36831870500 # Total ticks spent queuing -system.physmem.totMemAccLat 73577201750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18794.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59444 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.129365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.093444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.113658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27743 46.67% 46.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1259 2.12% 48.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26068 43.85% 92.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3874 6.52% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 419 0.70% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 52 0.09% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 24 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59444 # Writes before turning the bus around for reads +system.physmem.totQLat 36839321750 # Total ticks spent queuing +system.physmem.totMemAccLat 73585009250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18797.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37544.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 53.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 53.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37547.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 53.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 53.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 725319 # Number of row buffer hits during reads -system.physmem.writeRowHits 413326 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing +system.physmem.readRowHits 725244 # Number of row buffer hits during reads +system.physmem.writeRowHits 413130 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.59 # Row buffer hit rate for writes -system.physmem.avgGap 406684.71 # Average gap between requests -system.physmem.pageHitRate 38.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6747405840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3681620250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7383487800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416124660195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361949541750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 878257471275 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.862968 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 599359370250 # Time in different power states -system.physmem_0.memoryStateTime::REF 40458600000 # Time in different power states +system.physmem.writeRowHitRate 40.57 # Row buffer hit rate for writes +system.physmem.avgGap 406502.48 # Average gap between requests +system.physmem.pageHitRate 38.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6747186600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3681500625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383597000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3233831040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416789244855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361048893750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 877986693390 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.956282 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 597858043000 # Time in different power states +system.physmem_0.memoryStateTime::REF 40440920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 571802499750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 572793401000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7157785320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3905537625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7902000600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3364254000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 427714080030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 351783384000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 880964063175 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.096833 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 582370760250 # Time in different power states -system.physmem_1.memoryStateTime::REF 40458600000 # Time in different power states +system.physmem_1.actEnergy 7160348160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3906936000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7901891400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364351200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 428401624860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 350862595500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 880700186640 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.196822 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 580834507250 # Time in different power states +system.physmem_1.memoryStateTime::REF 40440920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 588789276000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 589813744000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246245862 # Number of BP lookups -system.cpu.branchPred.condPredicted 186459693 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15680292 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167860438 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165233261 # Number of BTB hits +system.cpu.branchPred.lookups 246195404 # Number of BP lookups +system.cpu.branchPred.condPredicted 186411563 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15682149 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167682775 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165241760 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.434904 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18428492 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104737 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.544266 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18427120 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104306 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452534136 # DTB read hits -system.cpu.dtb.read_misses 4979812 # DTB read misses +system.cpu.dtb.read_hits 452923392 # DTB read hits +system.cpu.dtb.read_misses 4979932 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457513948 # DTB read accesses -system.cpu.dtb.write_hits 161377662 # DTB write hits -system.cpu.dtb.write_misses 1710258 # DTB write misses +system.cpu.dtb.read_accesses 457903324 # DTB read accesses +system.cpu.dtb.write_hits 161377581 # DTB write hits +system.cpu.dtb.write_misses 1710142 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163087920 # DTB write accesses -system.cpu.dtb.data_hits 613911798 # DTB hits -system.cpu.dtb.data_misses 6690070 # DTB misses +system.cpu.dtb.write_accesses 163087723 # DTB write accesses +system.cpu.dtb.data_hits 614300973 # DTB hits +system.cpu.dtb.data_misses 6690074 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601868 # DTB accesses -system.cpu.itb.fetch_hits 598519306 # ITB hits +system.cpu.dtb.data_accesses 620991047 # DTB accesses +system.cpu.itb.fetch_hits 598257344 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598519325 # ITB accesses +system.cpu.itb.fetch_accesses 598257363 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -330,82 +329,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2423248959 # number of cpu cycles simulated +system.cpu.numCycles 2422192439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52407440 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52052944 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.326805 # CPI: cycles per instruction -system.cpu.ipc 0.753690 # IPC: instructions per cycle -system.cpu.tickCycles 2077336659 # Number of cycles that the object actually ticked -system.cpu.idleCycles 345912300 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9122013 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.749026 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601822613 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126109 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945148 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16826930000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.749026 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996277 # Average percentage of cache occupancy +system.cpu.cpi 1.326227 # CPI: cycles per instruction +system.cpu.ipc 0.754019 # IPC: instructions per cycle +system.cpu.tickCycles 2076133627 # Number of cycles that the object actually ticked +system.cpu.idleCycles 346058812 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121955 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.744039 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601604629 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.921682 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16824784000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.744039 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996275 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996275 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1544 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2417 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231838683 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231838683 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443338219 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443338219 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158484394 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158484394 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601822613 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601822613 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601822613 # number of overall hits -system.cpu.dcache.overall_hits::total 601822613 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289566 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289566 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2244108 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2244108 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9533674 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9533674 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9533674 # number of overall misses -system.cpu.dcache.overall_misses::total 9533674 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 186798880750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 186798880750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108940864000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108940864000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 295739744750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 295739744750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 295739744750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 295739744750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450627785 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450627785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231402079 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231402079 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443119981 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443119981 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158484648 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158484648 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601604629 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601604629 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601604629 # number of overall hits +system.cpu.dcache.overall_hits::total 601604629 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289531 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289531 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2243854 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2243854 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9533385 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9533385 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9533385 # number of overall misses +system.cpu.dcache.overall_misses::total 9533385 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 186817706000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 186817706000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108924057250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108924057250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 295741763250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 295741763250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 295741763250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 295741763250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450409512 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450409512 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611356287 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356287 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611356287 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356287 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013962 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013962 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015594 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015594 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.514708 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.514708 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48545.285699 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48545.285699 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31020.543051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31020.543051 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 611138014 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611138014 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611138014 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611138014 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016184 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013961 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013961 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015599 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015599 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015599 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015599 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25628.220252 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25628.220252 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48543.290807 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48543.290807 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31021.695153 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31021.695153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31021.695153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31021.695153 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,100 +413,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700625 # number of writebacks -system.cpu.dcache.writebacks::total 3700625 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50791 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50791 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 356774 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 356774 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 407565 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 407565 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 407565 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 407565 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887334 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887334 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126109 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126109 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126109 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126109 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174334776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 174334776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82397045250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82397045250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256731821250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 256731821250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256731821250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 256731821250 # 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miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80983.542320 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80983.542320 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80983.542320 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80983.542320 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80142.484342 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80142.484342 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80142.484342 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80142.484342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80142.484342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80142.484342 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,120 +516,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75665250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75665250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75665250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75665250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75665250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75665250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # 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number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79065.047022 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79065.047022 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79065.047022 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79065.047022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79065.047022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79065.047022 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78223.903967 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78223.903967 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78223.903967 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78223.903967 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78223.903967 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78223.903967 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1928293 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30768.859371 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981732 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958097 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.586970 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89233172750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14926.329939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.856216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15799.673216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455515 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1928309 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30768.375630 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981612 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65538.923720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74998.570670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74990.908995 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75649.873372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75649.873372 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64698.329854 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75014.366052 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75006.002212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75648.367929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75648.367929 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64698.329854 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64698.329854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887334 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952843 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954757 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820910976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820972224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887318 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887318 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952665 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954581 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820903296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820964608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827572 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827691 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827572 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827691 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114470500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827572 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114349000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1635750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1637500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14015207750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14015266250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181580 # Transaction distribution -system.membus.trans_dist::ReadResp 1181580 # Transaction distribution -system.membus.trans_dist::Writeback 1018244 # Transaction distribution -system.membus.trans_dist::ReadExReq 779448 # Transaction distribution -system.membus.trans_dist::ReadExResp 779448 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940300 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673408 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1181606 # Transaction distribution +system.membus.trans_dist::ReadResp 1181606 # Transaction distribution +system.membus.trans_dist::Writeback 1018263 # Transaction distribution +system.membus.trans_dist::ReadExReq 779439 # Transaction distribution +system.membus.trans_dist::ReadExResp 779439 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940353 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940353 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190675712 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979272 # Request fanout histogram +system.membus.snoop_fanout::samples 2979308 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979308 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979272 # Request fanout histogram -system.membus.reqLayer0.occupancy 7744840000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2979308 # Request fanout histogram +system.membus.reqLayer0.occupancy 7754390500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 10727612750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10727987500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index fd03f6311..fd798006f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.121265 # Number of seconds simulated -sim_ticks 1121265462500 # Number of ticks simulated -final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.119236 # Number of seconds simulated +sim_ticks 1119236001500 # Number of ticks simulated +final_tick 1119236001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238084 # Simulator instruction rate (inst/s) -host_op_rate 256500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172835636 # Simulator tick rate (ticks/s) -host_mem_usage 314372 # Number of bytes of host memory used -host_seconds 6487.47 # Real time elapsed on the host +host_inst_rate 240571 # Simulator instruction rate (inst/s) +host_op_rate 259178 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174324523 # Simulator tick rate (ticks/s) +host_mem_usage 314620 # Number of bytes of host memory used +host_seconds 6420.42 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 131531264 # Number of bytes read from this memory -system.physmem.bytes_read::total 131582080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66976320 # Number of bytes written to this memory -system.physmem.bytes_written::total 66976320 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2055176 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055970 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046505 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046505 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117306087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117351407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 59732795 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59732795 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59732795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117306087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177084202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055970 # Number of read requests accepted -system.physmem.writeReqs 1046505 # Number of write requests accepted -system.physmem.readBursts 2055970 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046505 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131497344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84736 # Total number of bytes read from write queue -system.physmem.bytesWritten 66974720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131582080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66976320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1324 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131457472 # Number of bytes read from this memory +system.physmem.bytes_read::total 131507904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66959680 # Number of bytes written to this memory +system.physmem.bytes_written::total 66959680 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 788 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2054023 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2054811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046245 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046245 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117452862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117497922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45059 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45059 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 59826239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59826239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59826239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117452862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177324160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2054811 # Number of read requests accepted +system.physmem.writeReqs 1046245 # Number of write requests accepted +system.physmem.readBursts 2054811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046245 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131422592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 85312 # Total number of bytes read from write queue +system.physmem.bytesWritten 66958080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131507904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66959680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1333 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128088 # Per bank write bursts -system.physmem.perBankRdBursts::1 125235 # Per bank write bursts -system.physmem.perBankRdBursts::2 122283 # Per bank write bursts -system.physmem.perBankRdBursts::3 124122 # Per bank write bursts -system.physmem.perBankRdBursts::4 123237 # Per bank write bursts -system.physmem.perBankRdBursts::5 123404 # Per bank write bursts -system.physmem.perBankRdBursts::6 123754 # Per bank write bursts -system.physmem.perBankRdBursts::7 124260 # Per bank write bursts -system.physmem.perBankRdBursts::8 132002 # Per bank write bursts -system.physmem.perBankRdBursts::9 134077 # Per bank write bursts -system.physmem.perBankRdBursts::10 132455 # Per bank write bursts -system.physmem.perBankRdBursts::11 133729 # Per bank write bursts -system.physmem.perBankRdBursts::12 133726 # Per bank write bursts -system.physmem.perBankRdBursts::13 133924 # Per bank write bursts -system.physmem.perBankRdBursts::14 129890 # Per bank write bursts -system.physmem.perBankRdBursts::15 130460 # Per bank write bursts -system.physmem.perBankWrBursts::0 65849 # Per bank write bursts -system.physmem.perBankWrBursts::1 64148 # Per bank write bursts -system.physmem.perBankWrBursts::2 62390 # Per bank write bursts -system.physmem.perBankWrBursts::3 62849 # Per bank write bursts -system.physmem.perBankWrBursts::4 62818 # Per bank write bursts -system.physmem.perBankWrBursts::5 62997 # Per bank write bursts -system.physmem.perBankWrBursts::6 64238 # Per bank write bursts -system.physmem.perBankWrBursts::7 65252 # Per bank write bursts -system.physmem.perBankWrBursts::8 67098 # Per bank write bursts -system.physmem.perBankWrBursts::9 67598 # Per bank write bursts -system.physmem.perBankWrBursts::10 67270 # Per bank write bursts -system.physmem.perBankWrBursts::11 67670 # Per bank write bursts -system.physmem.perBankWrBursts::12 67009 # Per bank write bursts -system.physmem.perBankWrBursts::13 67470 # Per bank write bursts -system.physmem.perBankWrBursts::14 66159 # Per bank write bursts -system.physmem.perBankWrBursts::15 65665 # Per bank write bursts +system.physmem.perBankRdBursts::0 127863 # Per bank write bursts +system.physmem.perBankRdBursts::1 125217 # Per bank write bursts +system.physmem.perBankRdBursts::2 122173 # Per bank write bursts +system.physmem.perBankRdBursts::3 124176 # Per bank write bursts +system.physmem.perBankRdBursts::4 123271 # Per bank write bursts +system.physmem.perBankRdBursts::5 123280 # Per bank write bursts +system.physmem.perBankRdBursts::6 123668 # Per bank write bursts +system.physmem.perBankRdBursts::7 124134 # Per bank write bursts +system.physmem.perBankRdBursts::8 131770 # Per bank write bursts +system.physmem.perBankRdBursts::9 134069 # Per bank write bursts +system.physmem.perBankRdBursts::10 132400 # Per bank write bursts +system.physmem.perBankRdBursts::11 133571 # Per bank write bursts +system.physmem.perBankRdBursts::12 133882 # Per bank write bursts +system.physmem.perBankRdBursts::13 133894 # Per bank write bursts +system.physmem.perBankRdBursts::14 129882 # Per bank write bursts +system.physmem.perBankRdBursts::15 130228 # Per bank write bursts +system.physmem.perBankWrBursts::0 65769 # Per bank write bursts +system.physmem.perBankWrBursts::1 64155 # Per bank write bursts +system.physmem.perBankWrBursts::2 62373 # Per bank write bursts +system.physmem.perBankWrBursts::3 62858 # Per bank write bursts +system.physmem.perBankWrBursts::4 62829 # Per bank write bursts +system.physmem.perBankWrBursts::5 62965 # Per bank write bursts +system.physmem.perBankWrBursts::6 64230 # Per bank write bursts +system.physmem.perBankWrBursts::7 65234 # Per bank write bursts +system.physmem.perBankWrBursts::8 67002 # Per bank write bursts +system.physmem.perBankWrBursts::9 67576 # Per bank write bursts +system.physmem.perBankWrBursts::10 67286 # Per bank write bursts +system.physmem.perBankWrBursts::11 67640 # Per bank write bursts +system.physmem.perBankWrBursts::12 67022 # Per bank write bursts +system.physmem.perBankWrBursts::13 67467 # Per bank write bursts +system.physmem.perBankWrBursts::14 66208 # Per bank write bursts +system.physmem.perBankWrBursts::15 65606 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1121265368000 # Total gap between requests +system.physmem.totGap 1119235907000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055970 # Read request sizes (log2) +system.physmem.readPktSize::6 2054811 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046505 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1926795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1925781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61214 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 60967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,105 +193,108 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1920747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.329698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.701744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 124.647307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1495902 77.88% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305625 15.91% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52698 2.74% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21305 1.11% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13173 0.69% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7131 0.37% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5450 0.28% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5094 0.27% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14369 0.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1920747 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60965 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.654375 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.846066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60925 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1918760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.389572 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.724365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 124.748032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1494097 77.87% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305195 15.91% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52958 2.76% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21140 1.10% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13031 0.68% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7420 0.39% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5500 0.29% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5087 0.27% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14332 0.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1918760 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60963 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.636353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.963797 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60925 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60965 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.165259 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.130353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.096188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27136 44.51% 44.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1324 2.17% 46.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28285 46.40% 93.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3807 6.24% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 355 0.58% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 47 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60963 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60963 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.161557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.126473 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.099462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27343 44.85% 44.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1128 1.85% 46.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28298 46.42% 93.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3779 6.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 354 0.58% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60965 # Writes before turning the bus around for reads -system.physmem.totQLat 38466601000 # Total ticks spent queuing -system.physmem.totMemAccLat 76991213500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10273230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18721.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60963 # Writes before turning the bus around for reads +system.physmem.totQLat 38392697500 # Total ticks spent queuing +system.physmem.totMemAccLat 76895410000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10267390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18696.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37471.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 117.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37446.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 59.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.38 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.95 # Average write queue length when enqueuing -system.physmem.readRowHits 774547 # Number of row buffer hits during reads -system.physmem.writeRowHits 405822 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.78 # Row buffer hit rate for writes -system.physmem.avgGap 361409.96 # Average gap between requests -system.physmem.pageHitRate 38.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7084922040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3865780875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7755875400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3308305680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 422966689965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301732094250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 819948851010 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.275041 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 499232206000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37441300000 # Time in different power states +system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing +system.physmem.readRowHits 774740 # Number of row buffer hits during reads +system.physmem.writeRowHits 406194 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.82 # Row buffer hit rate for writes +system.physmem.avgGap 360920.90 # Average gap between requests +system.physmem.pageHitRate 38.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7079751000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3862959375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7751413800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3307476240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 422173404720 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301213311750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 818491274085 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.295434 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498371051250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37373700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 584588629000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583490028750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7435910160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4057292250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8269996800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3472884720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 431711081055 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 294061575750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 822243923535 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.321912 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 486423236500 # Time in different power states -system.physmem_1.memoryStateTime::REF 37441300000 # Time in different power states +system.physmem_1.actEnergy 7426074600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4051925625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8265605400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3472029360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 430406880300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293990964750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 820716437235 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.283545 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 486308465000 # Time in different power states +system.physmem_1.memoryStateTime::REF 37373700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 597397500000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 595553667000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240144458 # Number of BP lookups -system.cpu.branchPred.condPredicted 186748856 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14594265 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132793559 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122289853 # Number of BTB hits +system.cpu.branchPred.lookups 239764270 # Number of BP lookups +system.cpu.branchPred.condPredicted 186476421 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14595676 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130796554 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122091083 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.090199 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15658823 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 93.344266 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15654091 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -411,68 +414,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2242530925 # number of cpu cycles simulated +system.cpu.numCycles 2238472003 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40067412 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41626992 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.451887 # CPI: cycles per instruction -system.cpu.ipc 0.688759 # IPC: instructions per cycle -system.cpu.tickCycles 1838970368 # Number of cycles that the object actually ticked -system.cpu.idleCycles 403560557 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9223420 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.640559 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624065637 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9227516 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.630946 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9814734000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.640559 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy +system.cpu.cpi 1.449259 # CPI: cycles per instruction +system.cpu.ipc 0.690008 # IPC: instructions per cycle +system.cpu.tickCycles 1834950604 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403521399 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9221835 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.627405 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624240644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9225931 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.661534 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9809256250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.627405 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997468 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997468 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1219 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1227 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276541490 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276541490 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453733959 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453733959 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331555 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331555 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276887063 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276887063 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453909121 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453909121 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331400 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331400 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624065514 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624065514 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624065515 # number of overall hits -system.cpu.dcache.overall_hits::total 624065515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7336856 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7336856 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254492 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254492 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624240521 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624240521 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624240522 # number of overall hits +system.cpu.dcache.overall_hits::total 624240522 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7335273 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7335273 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9591348 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9591348 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9591350 # number of overall misses -system.cpu.dcache.overall_misses::total 9591350 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192473949996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192473949996 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109728776250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109728776250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 302202726246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 302202726246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 302202726246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 302202726246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461070815 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461070815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589920 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589920 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589922 # number of overall misses +system.cpu.dcache.overall_misses::total 9589922 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192354012246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192354012246 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109627439500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109627439500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 301981451746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 301981451746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 301981451746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 301981451746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461244394 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461244394 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -481,28 +484,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633656862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633656862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633656865 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633656865 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 633830441 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633830441 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633830444 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633830444 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015903 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015903 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013064 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015137 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015137 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015137 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015137 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26233.845941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26233.845941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48671.175702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48671.175702 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31507.847098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31507.847098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31507.840528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31507.840528 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26223.156554 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26223.156554 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48622.883981 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48622.883981 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31489.465162 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31489.465162 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31489.458595 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31489.458595 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,109 +514,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700612 # number of writebacks -system.cpu.dcache.writebacks::total 3700612 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 212 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 363621 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 363833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 363833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 363833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 363833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336644 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336644 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890871 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890871 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3700642 # number of writebacks +system.cpu.dcache.writebacks::total 3700642 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363775 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 363775 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 363990 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 363990 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 363990 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 363990 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7335058 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7335058 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890872 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227515 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227515 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9227516 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227516 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181052332504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 181052332504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83984263000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83984263000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9225930 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9225930 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9225931 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9225931 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180934230004 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180934230004 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83925664500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83925664500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265036595504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 265036595504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265036669254 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 265036669254 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264859894504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264859894504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264859968254 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264859968254 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015903 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24677.813521 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24677.813521 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44415.649190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44415.649190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014556 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014556 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24667.048305 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24667.048305 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44384.635502 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44384.635502 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28722.423697 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28722.423697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28722.428577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28722.428577 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28708.205515 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28708.205515 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28708.210397 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28708.210397 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 35 # number of replacements -system.cpu.icache.tags.tagsinuse 662.614734 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466141021 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 562972.247585 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29 # number of replacements +system.cpu.icache.tags.tagsinuse 662.446494 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465464024 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 821 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 566947.654080 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 662.614734 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.323542 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.323542 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 793 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 662.446494 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.323460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.323460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.387207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932284526 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932284526 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466141021 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466141021 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466141021 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466141021 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466141021 # number of overall hits -system.cpu.icache.overall_hits::total 466141021 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 828 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 828 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 828 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 828 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 828 # number of overall misses -system.cpu.icache.overall_misses::total 828 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63773749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63773749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63773749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63773749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63773749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63773749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466141849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466141849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466141849 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466141849 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87756.490119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76398.288973 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87760.853071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87756.490119 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,8 +750,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046505 # number of writebacks -system.cpu.l2cache.writebacks::total 1046505 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1046245 # number of writebacks +system.cpu.l2cache.writebacks::total 1046245 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits @@ -758,103 +761,103 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 794 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1255064 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255858 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60466755500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60466755500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154451794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 154502863500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51069250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154451794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 154502863500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171068 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423145 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423145 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222723 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222789 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222723 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64318.954660 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74884.658272 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74877.978243 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75572.864174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75572.864174 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75148.403673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75148.403673 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 788 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254070 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1254858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 799953 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 799953 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 788 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2054023 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2054811 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 788 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2054023 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2054811 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50399250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93887019000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 93937418250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60414024000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60414024000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50399250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154301043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154351442250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50399250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154301043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154351442250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.170969 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171058 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222701 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222701 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63958.439086 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74865.851986 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74859.002572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75521.966916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75521.966916 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7337473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890871 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22157300 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827400192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7335880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890872 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1642 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22152504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22154146 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827300672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827353216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12927394 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12928956 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12927394 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12927394 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10164339000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1409749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1397749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14190252246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14187903746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1255858 # Transaction distribution -system.membus.trans_dist::ReadResp 1255858 # Transaction distribution -system.membus.trans_dist::Writeback 1046505 # Transaction distribution -system.membus.trans_dist::ReadExReq 800112 # Transaction distribution -system.membus.trans_dist::ReadExResp 800112 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5158445 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198558400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198558400 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1254858 # Transaction distribution +system.membus.trans_dist::ReadResp 1254858 # Transaction distribution +system.membus.trans_dist::Writeback 1046245 # Transaction distribution +system.membus.trans_dist::ReadExReq 799953 # Transaction distribution +system.membus.trans_dist::ReadExResp 799953 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5155867 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5155867 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198467584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198467584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3102475 # Request fanout histogram +system.membus.snoop_fanout::samples 3101056 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3102475 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3101056 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3102475 # Request fanout histogram -system.membus.reqLayer0.occupancy 7945005500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3101056 # Request fanout histogram +system.membus.reqLayer0.occupancy 7929911000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 11244435500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11237799750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index e483ad3f0..874972c77 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052202 # Number of seconds simulated -sim_ticks 52201532500 # Number of ticks simulated -final_tick 52201532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052048 # Number of seconds simulated +sim_ticks 52048460500 # Number of ticks simulated +final_tick 52048460500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357575 # Simulator instruction rate (inst/s) -host_op_rate 357575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 203104604 # Simulator tick rate (ticks/s) -host_mem_usage 300132 # Number of bytes of host memory used -host_seconds 257.02 # Real time elapsed on the host +host_inst_rate 350030 # Simulator instruction rate (inst/s) +host_op_rate 350030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 198236020 # Simulator tick rate (ticks/s) +host_mem_usage 300292 # Number of bytes of host memory used +host_seconds 262.56 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 202688 # Nu system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3882798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2637164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6519962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3882798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3882798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3882798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2637164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6519962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3894217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2644920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6539137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3894217 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3894217 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3894217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2644920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6539137 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52201444000 # Total gap between requests +system.physmem.totGap 52048372000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.912513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.979760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.521018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 325 33.06% 33.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 203 20.65% 53.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 9.16% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 89 9.05% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 77 7.83% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 32 3.26% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 2.85% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 23 2.34% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 116 11.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 983 # Bytes accessed per row activation -system.physmem.totQLat 33415750 # Total ticks spent queuing -system.physmem.totMemAccLat 133128250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.672131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.149483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.651264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 303 31.05% 31.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 210 21.52% 52.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 100 10.25% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 92 9.43% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 7.27% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 4.00% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 3.07% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 1.95% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 112 11.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 976 # Bytes accessed per row activation +system.physmem.totQLat 32254250 # Total ticks spent queuing +system.physmem.totMemAccLat 131966750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6283.52 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6065.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25033.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24815.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4336 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9815991.73 # Average gap between requests -system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3500280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1909875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19975800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9787207.97 # Average gap between requests +system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19851000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1770933285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29766117750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34971823230 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.967540 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49515286750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1743040000 # Time in different power states +system.physmem_0.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1773582930 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29670358500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34868440995 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.985765 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49355972750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1737840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 940967000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 949756000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3908520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2132625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21301800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1804216725 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29736921750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34977867660 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.083336 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49466733750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1743040000 # Time in different power states +system.physmem_1.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1774901340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29669193750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34870438740 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.024328 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49353927250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1737840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 989849750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 951967750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11476351 # Number of BP lookups -system.cpu.branchPred.condPredicted 8235351 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672655 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5371510 # Number of BTB hits +system.cpu.branchPred.lookups 11467285 # Number of BP lookups +system.cpu.branchPred.condPredicted 8228909 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 787075 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6498554 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5367359 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.500341 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176738 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 82.593128 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1175694 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20396755 # DTB read hits -system.cpu.dtb.read_misses 47141 # DTB read misses +system.cpu.dtb.read_hits 20428735 # DTB read hits +system.cpu.dtb.read_misses 47112 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20443896 # DTB read accesses -system.cpu.dtb.write_hits 6580249 # DTB write hits -system.cpu.dtb.write_misses 266 # DTB write misses +system.cpu.dtb.read_accesses 20475847 # DTB read accesses +system.cpu.dtb.write_hits 6580361 # DTB write hits +system.cpu.dtb.write_misses 271 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580515 # DTB write accesses -system.cpu.dtb.data_hits 26977004 # DTB hits -system.cpu.dtb.data_misses 47407 # DTB misses +system.cpu.dtb.write_accesses 6580632 # DTB write accesses +system.cpu.dtb.data_hits 27009096 # DTB hits +system.cpu.dtb.data_misses 47383 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068140 # ITB hits +system.cpu.dtb.data_accesses 27056479 # DTB accesses +system.cpu.itb.fetch_hits 23055300 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068228 # ITB accesses +system.cpu.itb.fetch_accesses 23055388 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104403065 # number of cpu cycles simulated +system.cpu.numCycles 104096921 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2232007 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.136013 # CPI: cycles per instruction -system.cpu.ipc 0.880272 # IPC: instructions per cycle -system.cpu.tickCycles 102681380 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1721685 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.132681 # CPI: cycles per instruction +system.cpu.ipc 0.882861 # IPC: instructions per cycle +system.cpu.tickCycles 102361178 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1735743 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.443915 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26568135 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.464460 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26584631 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11913.961883 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11921.359193 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.443915 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353624 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.464460 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353629 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353629 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,56 +320,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53145360 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53145360 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20069943 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20069943 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26568135 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26568135 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26568135 # number of overall hits -system.cpu.dcache.overall_hits::total 26568135 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2911 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses -system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40365000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 216719250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 216719250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 257084250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 257084250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 257084250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 257084250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20070462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20070462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 53178348 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53178348 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20086436 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20086436 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26584631 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26584631 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26584631 # number of overall hits +system.cpu.dcache.overall_hits::total 26584631 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 520 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3428 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3428 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3428 # number of overall misses +system.cpu.dcache.overall_misses::total 3428 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41644750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41644750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214147250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214147250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 255792000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 255792000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 255792000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 255792000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20086956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20086956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26571565 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26571565 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26571565 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26571565 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26588059 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26588059 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26588059 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26588059 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77774.566474 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77774.566474 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74448.385435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74448.385435 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74951.676385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74951.676385 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80086.057692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 80086.057692 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73640.732462 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73640.732462 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74618.436406 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74618.436406 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,14 +380,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1166 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1166 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1198 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1198 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1198 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1198 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37010250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37010250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130741250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 130741250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 167751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167751500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 167751500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38003250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38003250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129542250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 129542250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167545500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 167545500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,24 +412,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76309.793814 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76309.793814 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74923.352436 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74923.352436 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78357.216495 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78357.216495 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74236.246418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74236.246418 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.396029 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052304 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.781749 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13853 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.586076 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23039482 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15817 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1456.627806 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.396029 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800975 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.586076 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801067 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801067 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -437,44 +437,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152115 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152115 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052304 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052304 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052304 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052304 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052304 # number of overall hits -system.cpu.icache.overall_hits::total 23052304 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses -system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409644000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409644000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409644000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409644000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409644000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409644000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068140 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068140 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068140 # 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number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15818 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15818 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15818 # number of overall misses +system.cpu.icache.overall_misses::total 15818 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 408417500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 408417500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 408417500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 408417500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 408417500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 408417500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23055300 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23055300 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23055300 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23055300 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23055300 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23055300 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25867.895933 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25867.895933 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25867.895933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25867.895933 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25819.793906 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25819.793906 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25819.793906 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25819.793906 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25819.793906 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25819.793906 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,44 +483,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15836 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15836 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15836 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15818 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15818 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 383318000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 383318000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 383318000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 383318000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 383318000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 383318000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24281.226320 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24281.226320 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24233.025667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24233.025667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24233.025667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24233.025667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24233.025667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24233.025667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.394298 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2479.864899 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12717 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.469850 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.779390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.640552 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 360.974356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.782834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.110753 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 360.971312 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064106 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064121 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011016 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075665 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id @@ -528,21 +528,21 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 182 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111847 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 150786 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 150786 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12668 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 150642 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 150642 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 12650 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 12721 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 12703 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12668 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 12650 # 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number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 235668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35962750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 271630750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128723250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 128723250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 235668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 164686000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 400354000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 235668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 164686000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 400354000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234675500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36955750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 271631250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 127524250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 127524250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234675500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 399155500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234675500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164480000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 399155500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15817 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 16302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15835 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15817 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 18065 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15835 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 18047 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15817 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 18065 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 18047 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200228 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890722 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.220527 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.220770 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200228 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.294675 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200228 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74413.640669 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83247.106481 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75473.951098 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.635253 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.635253 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75282.813088 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75282.813088 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.294675 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74100.252605 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85545.717593 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75474.090025 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74185.136707 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74185.136707 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74100.252605 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76466.759647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75057.446408 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74100.252605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76466.759647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75057.446408 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,68 +619,68 @@ system.cpu.l2cache.demand_mshr_misses::total 5318 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196043000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30551250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226594250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107188750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107188750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137740000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 333783000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137740000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 333783000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195052500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31544750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226597250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 106089750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 106089750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195052500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137634500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 332687000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195052500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137634500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 332687000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220770 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294675 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61901.799811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.486111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62960.336205 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62355.293775 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62355.293775 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294675 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61589.043259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73020.254630 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62961.169769 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61715.968586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61715.968586 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 16302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16302 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31670 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31634 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 36237 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 36201 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1163008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1161856 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 18154 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18172 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18154 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 18154 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9184000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24439500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24412500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3770500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3745500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -701,9 +701,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6453000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6399500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28232500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28155000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index da5e39914..d21841628 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131767 # Number of seconds simulated -sim_ticks 131767151500 # Number of ticks simulated -final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131586 # Number of seconds simulated +sim_ticks 131586268500 # Number of ticks simulated +final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 244794 # Simulator instruction rate (inst/s) -host_op_rate 258052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187187675 # Simulator tick rate (ticks/s) -host_mem_usage 317932 # Number of bytes of host memory used -host_seconds 703.93 # Real time elapsed on the host +host_inst_rate 246297 # Simulator instruction rate (inst/s) +host_op_rate 259636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188078312 # Simulator tick rate (ticks/s) +host_mem_usage 317920 # Number of bytes of host memory used +host_seconds 699.64 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138368 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138368 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3869 # Number of read requests accepted +system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3870 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247680 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247680 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe system.physmem.perBankRdBursts::1 217 # Per bank write bursts system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts -system.physmem.perBankRdBursts::4 307 # Per bank write bursts +system.physmem.perBankRdBursts::4 308 # Per bank write bursts system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 200 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 205 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131767057000 # Total gap between requests +system.physmem.totGap 131586174000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3869 # Read request sizes (log2) +system.physmem.readPktSize::6 3870 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation -system.physmem.totQLat 28218000 # Total ticks spent queuing -system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation +system.physmem.totQLat 26462250 # Total ticks spent queuing +system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2961 # Number of row buffer hits during reads +system.physmem.readRowHits 2963 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34057135.44 # Average gap between requests -system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34001595.35 # Average gap between requests +system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.827838 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states +system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.824061 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states +system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.799395 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states +system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.792204 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states +system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49934214 # Number of BP lookups -system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits +system.cpu.branchPred.lookups 49889699 # Number of BP lookups +system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263534303 # number of cpu cycles simulated +system.cpu.numCycles 263172537 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529350 # CPI: cycles per instruction -system.cpu.ipc 0.653872 # IPC: instructions per cycle -system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.527251 # CPI: cycles per instruction +system.cpu.ipc 0.654771 # IPC: instructions per cycle +system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -404,10 +404,10 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81594514 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits @@ -416,30 +416,30 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits -system.cpu.dcache.overall_hits::total 40719565 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 40748634 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40748634 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40749098 # number of overall hits +system.cpu.dcache.overall_hits::total 40749098 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2438 # number of overall misses -system.cpu.dcache.overall_misses::total 2438 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59434234 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127677000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 187111234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28357251 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2439 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2440 # number of overall misses +system.cpu.dcache.overall_misses::total 2440 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57815734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126489000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184304734 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184304734 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40722003 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40751073 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40751073 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40751538 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40751538 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 628 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 628 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52911264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52911264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85210500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85210500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51168764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51168764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84319000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84319000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138121764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138121764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138191264 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 135487764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 135487764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 135557264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74418.092827 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2892 # number of replacements -system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4690 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2889 # number of replacements +system.cpu.icache.tags.tagsinuse 1425.913177 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71538503 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15263.175379 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1425.992142 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.696285 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.696285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1425.913177 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.696247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.696247 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143211246 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143211246 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71598587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71598587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71598587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71598587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71598587 # number of overall hits -system.cpu.icache.overall_hits::total 71598587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4691 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4691 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4691 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4691 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4691 # number of overall misses -system.cpu.icache.overall_misses::total 4691 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200040248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200040248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200040248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200040248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200040248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200040248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71603278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71603278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71603278 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71603278 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71603278 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71603278 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 143091069 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143091069 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71538503 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71538503 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71538503 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,111 +716,111 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2163 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2781 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3871 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 133664500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42488500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176153000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70398000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70398000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 133664500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112886500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 246551000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 133664500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112886500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 246551000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 3871 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134379750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40985000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175364750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69507000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69507000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134379750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110492000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 244871750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134379750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110492000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 244871750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514529 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.595293 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.595293 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13017 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2779 # Transaction distribution -system.membus.trans_dist::ReadResp 2779 # Transaction distribution +system.membus.trans_dist::ReadReq 2780 # Transaction distribution +system.membus.trans_dist::ReadResp 2780 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247680 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3869 # Request fanout histogram +system.membus.snoop_fanout::samples 3870 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3869 # Request fanout histogram -system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870 # Request fanout histogram +system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |