diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
| commit | 80cd107e51ceb5aac262ec7dd82870e48d345b43 (patch) | |
| tree | 4bb545ae29522161963a8028f34ca850c98a3403 /tests/long/se | |
| parent | 2847d5f5177304236dcdbab112a0369f0bd96aea (diff) | |
| download | gem5-80cd107e51ceb5aac262ec7dd82870e48d345b43.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long/se')
30 files changed, 1465 insertions, 1523 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 4eaa033e0..b7910ff50 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061594 # Nu sim_ticks 61594138500 # Number of ticks simulated final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196979 # Simulator instruction rate (inst/s) -host_op_rate 197960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133911114 # Simulator tick rate (ticks/s) -host_mem_usage 438496 # Number of bytes of host memory used -host_seconds 459.96 # Real time elapsed on the host +host_inst_rate 265976 # Simulator instruction rate (inst/s) +host_op_rate 267300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 180817037 # Simulator tick rate (ticks/s) +host_mem_usage 446692 # Number of bytes of host memory used +host_seconds 340.64 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -779,17 +779,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1894252 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a297b8e5d..cb0d7cfc4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.058203 # Nu sim_ticks 58203290500 # Number of ticks simulated final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98982 # Simulator instruction rate (inst/s) -host_op_rate 99475 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63595388 # Simulator tick rate (ticks/s) -host_mem_usage 438244 # Number of bytes of host memory used -host_seconds 915.21 # Real time elapsed on the host +host_inst_rate 131910 # Simulator instruction rate (inst/s) +host_op_rate 132567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84750962 # Simulator tick rate (ticks/s) +host_mem_usage 445160 # Number of bytes of host memory used +host_seconds 686.76 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1154,17 +1154,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 22116 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002023 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.002023 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10908954 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 22114 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10908954 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 22114 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 4697b1e09..1d5681a17 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.062108 # Nu sim_ticks 62108139000 # Number of ticks simulated final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88749 # Simulator instruction rate (inst/s) -host_op_rate 156272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34888646 # Simulator tick rate (ticks/s) -host_mem_usage 448856 # Number of bytes of host memory used -host_seconds 1780.18 # Real time elapsed on the host +host_inst_rate 114338 # Simulator instruction rate (inst/s) +host_op_rate 201331 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44948395 # Simulator tick rate (ticks/s) +host_mem_usage 455560 # Number of bytes of host memory used +host_seconds 1381.77 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -946,17 +946,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4144289 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4144289 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 05a346173..02993075a 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065500 # Number of ticks simulated final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 638452 # Simulator instruction rate (inst/s) -host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1479007835 # Simulator tick rate (ticks/s) -host_mem_usage 450980 # Number of bytes of host memory used -host_seconds 247.46 # Real time elapsed on the host +host_inst_rate 678113 # Simulator instruction rate (inst/s) +host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1570885616 # Simulator tick rate (ticks/s) +host_mem_usage 451452 # Number of bytes of host memory used +host_seconds 232.98 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -452,17 +452,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index e29c8c27b..a54a6c0d4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.366340 # Nu sim_ticks 366339500500 # Number of ticks simulated final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174606 # Simulator instruction rate (inst/s) -host_op_rate 189122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126268215 # Simulator tick rate (ticks/s) -host_mem_usage 309684 # Number of bytes of host memory used -host_seconds 2901.28 # Real time elapsed on the host +host_inst_rate 237525 # Simulator instruction rate (inst/s) +host_op_rate 257271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171768388 # Simulator tick rate (ticks/s) +host_mem_usage 317860 # Number of bytes of host memory used +host_seconds 2132.75 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -824,17 +824,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 2232032 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2232032 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index f6e4f2ecd..12498d68b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.233457 # Nu sim_ticks 233457400500 # Number of ticks simulated final_tick 233457400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105147 # Simulator instruction rate (inst/s) -host_op_rate 113911 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48585649 # Simulator tick rate (ticks/s) -host_mem_usage 312624 # Number of bytes of host memory used -host_seconds 4805.07 # Real time elapsed on the host +host_inst_rate 140578 # Simulator instruction rate (inst/s) +host_op_rate 152296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64957541 # Simulator tick rate (ticks/s) +host_mem_usage 319412 # Number of bytes of host memory used +host_seconds 3594.00 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1159,17 +1159,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 335917632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 317126 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5565869 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.056971 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.056971 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.231787 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5248777 94.30% 94.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 317092 5.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5248777 94.30% 94.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 317092 5.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5565869 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4977148500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 7518311dc..04541cf46 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362298000 # Number of ticks simulated final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1382525 # Simulator instruction rate (inst/s) -host_op_rate 1497457 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 762414599 # Simulator tick rate (ticks/s) -host_mem_usage 298924 # Number of bytes of host memory used -host_seconds 366.42 # Real time elapsed on the host +host_inst_rate 1944100 # Simulator instruction rate (inst/s) +host_op_rate 2105717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1072104103 # Simulator tick rate (ticks/s) +host_mem_usage 306580 # Number of bytes of host memory used +host_seconds 260.57 # Real time elapsed on the host sim_insts 506581608 # Number of instructions simulated sim_ops 548694829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 687930750 # Request fanout histogram -system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram +system.membus.snoop_fanout::mean 0.750964 # Request fanout histogram system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::3 516611376 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::1 516611376 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 687930750 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 93937d49d..5ab6bd474 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -593,17 +593,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 5165f82f6..3384a1591 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417785 # Number of seconds simulated -sim_ticks 417784645500 # Number of ticks simulated -final_tick 417784645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417996 # Number of seconds simulated +sim_ticks 417996021500 # Number of ticks simulated +final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77548 # Simulator instruction rate (inst/s) -host_op_rate 143396 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39181823 # Simulator tick rate (ticks/s) -host_mem_usage 423644 # Number of bytes of host memory used -host_seconds 10662.72 # Real time elapsed on the host +host_inst_rate 98610 # Simulator instruction rate (inst/s) +host_op_rate 182341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49848381 # Simulator tick rate (ticks/s) +host_mem_usage 430328 # Number of bytes of host memory used +host_seconds 8385.35 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 225536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24761856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 225536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 225536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18818176 # Number of bytes written to this memory -system.physmem.bytes_written::total 18818176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3524 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory +system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386904 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294034 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 539838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58729588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59269426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 539838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 539838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45042766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45042766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45042766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 539838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58729588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104312192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386904 # Number of read requests accepted -system.physmem.writeReqs 294034 # Number of write requests accepted -system.physmem.readBursts 386904 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294034 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24739840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue -system.physmem.bytesWritten 18816320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24761856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18818176 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386930 # Number of read requests accepted +system.physmem.writeReqs 294035 # Number of write requests accepted +system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue +system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 194832 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24113 # Per bank write bursts -system.physmem.perBankRdBursts::1 26506 # Per bank write bursts -system.physmem.perBankRdBursts::2 24704 # Per bank write bursts -system.physmem.perBankRdBursts::3 24585 # Per bank write bursts -system.physmem.perBankRdBursts::4 23284 # Per bank write bursts -system.physmem.perBankRdBursts::5 23758 # Per bank write bursts -system.physmem.perBankRdBursts::6 24455 # Per bank write bursts -system.physmem.perBankRdBursts::7 24304 # Per bank write bursts -system.physmem.perBankRdBursts::8 23622 # Per bank write bursts -system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24786 # Per bank write bursts -system.physmem.perBankRdBursts::11 24077 # Per bank write bursts -system.physmem.perBankRdBursts::12 23364 # Per bank write bursts -system.physmem.perBankRdBursts::13 22990 # Per bank write bursts -system.physmem.perBankRdBursts::14 24090 # Per bank write bursts -system.physmem.perBankRdBursts::15 23971 # Per bank write bursts -system.physmem.perBankWrBursts::0 18545 # Per bank write bursts -system.physmem.perBankWrBursts::1 19845 # Per bank write bursts -system.physmem.perBankWrBursts::2 18943 # Per bank write bursts -system.physmem.perBankWrBursts::3 18938 # Per bank write bursts -system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18456 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24110 # Per bank write bursts +system.physmem.perBankRdBursts::1 26511 # Per bank write bursts +system.physmem.perBankRdBursts::2 24689 # Per bank write bursts +system.physmem.perBankRdBursts::3 24586 # Per bank write bursts +system.physmem.perBankRdBursts::4 23301 # Per bank write bursts +system.physmem.perBankRdBursts::5 23773 # Per bank write bursts +system.physmem.perBankRdBursts::6 24463 # Per bank write bursts +system.physmem.perBankRdBursts::7 24300 # Per bank write bursts +system.physmem.perBankRdBursts::8 23625 # Per bank write bursts +system.physmem.perBankRdBursts::9 23952 # Per bank write bursts +system.physmem.perBankRdBursts::10 24787 # Per bank write bursts +system.physmem.perBankRdBursts::11 24070 # Per bank write bursts +system.physmem.perBankRdBursts::12 23353 # Per bank write bursts +system.physmem.perBankRdBursts::13 22981 # Per bank write bursts +system.physmem.perBankRdBursts::14 24097 # Per bank write bursts +system.physmem.perBankRdBursts::15 23979 # Per bank write bursts +system.physmem.perBankWrBursts::0 18543 # Per bank write bursts +system.physmem.perBankWrBursts::1 19847 # Per bank write bursts +system.physmem.perBankWrBursts::2 18947 # Per bank write bursts +system.physmem.perBankWrBursts::3 18939 # Per bank write bursts +system.physmem.perBankWrBursts::4 18047 # Per bank write bursts +system.physmem.perBankWrBursts::5 18457 # Per bank write bursts system.physmem.perBankWrBursts::6 18996 # Per bank write bursts -system.physmem.perBankWrBursts::7 18987 # Per bank write bursts -system.physmem.perBankWrBursts::8 18549 # Per bank write bursts -system.physmem.perBankWrBursts::9 18172 # Per bank write bursts -system.physmem.perBankWrBursts::10 18834 # Per bank write bursts -system.physmem.perBankWrBursts::11 17732 # Per bank write bursts -system.physmem.perBankWrBursts::12 17374 # Per bank write bursts -system.physmem.perBankWrBursts::13 16972 # Per bank write bursts +system.physmem.perBankWrBursts::7 18981 # Per bank write bursts +system.physmem.perBankWrBursts::8 18548 # Per bank write bursts +system.physmem.perBankWrBursts::9 18168 # Per bank write bursts +system.physmem.perBankWrBursts::10 18839 # Per bank write bursts +system.physmem.perBankWrBursts::11 17728 # Per bank write bursts +system.physmem.perBankWrBursts::12 17372 # Per bank write bursts +system.physmem.perBankWrBursts::13 16973 # Per bank write bursts system.physmem.perBankWrBursts::14 17820 # Per bank write bursts -system.physmem.perBankWrBursts::15 17802 # Per bank write bursts +system.physmem.perBankWrBursts::15 17811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417784619000 # Total gap between requests +system.physmem.totGap 417995980500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386904 # Read request sizes (log2) +system.physmem.readPktSize::6 386930 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294034 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294035 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see @@ -193,37 +193,37 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.518428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.412890 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.590500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54886 37.24% 37.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39792 27.00% 64.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13719 9.31% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7560 5.13% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5573 3.78% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3862 2.62% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3103 2.11% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2674 1.81% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16215 11.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147384 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17444 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.159252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.918601 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17431 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17444 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.854219 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.780353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.660093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17244 98.85% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 141 0.81% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.15% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 11 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads @@ -237,202 +237,202 @@ system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17444 # Writes before turning the bus around for reads -system.physmem.totQLat 4274781750 # Total ticks spent queuing -system.physmem.totMemAccLat 11522781750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11058.52 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads +system.physmem.totQLat 4282714250 # Total ticks spent queuing +system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29808.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.29 # Average write queue length when enqueuing -system.physmem.readRowHits 318043 # Number of row buffer hits during reads -system.physmem.writeRowHits 215127 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes -system.physmem.avgGap 613542.82 # Average gap between requests -system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567476280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309634875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526389800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976691520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63728995635 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194764938000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 289161421470 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.139218 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 323446024000 # Time in different power states -system.physmem_0.memoryStateTime::REF 13950560000 # Time in different power states +system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing +system.physmem.readRowHits 318033 # Number of row buffer hits during reads +system.physmem.writeRowHits 215097 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 613828.88 # Average gap between requests +system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.167087 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80384174500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 546399000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298134375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1488177600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928104480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61807042845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196450861500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288806015160 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.288514 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 326265955250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13950560000 # Time in different power states +system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.276862 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states +system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77563900250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 230228501 # Number of BP lookups -system.cpu.branchPred.condPredicted 230228501 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9739021 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131459692 # Number of BTB lookups -system.cpu.branchPred.BTBHits 128773186 # Number of BTB hits +system.cpu.branchPred.lookups 230262495 # Number of BP lookups +system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups +system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.956403 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27739164 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1472550 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 835569292 # number of cpu cycles simulated +system.cpu.numCycles 835992044 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 185184379 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1269166320 # Number of instructions fetch has processed -system.cpu.fetch.Branches 230228501 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156512350 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 639147953 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20213743 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 511 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 99253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 822297 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1772 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179484418 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2740851 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed +system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 835363066 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.826562 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.382493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 427868247 51.22% 51.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33702021 4.03% 55.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32929710 3.94% 59.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33265996 3.98% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27012416 3.23% 66.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27748723 3.32% 69.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36992796 4.43% 74.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33648824 4.03% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182194333 21.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 835363066 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275535 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.518924 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127510375 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 375947418 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240571925 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81226477 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10106871 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2225382694 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10106871 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159640008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 160513488 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 42854 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285557624 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219502221 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2175351414 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 185986 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 136028392 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24255750 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 49096014 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2279465980 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5501874168 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3499442561 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 66867 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 665425126 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3167 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2999 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 415602419 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528341229 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 209838821 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 239501304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72157646 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2101036293 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25395 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1826926557 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 429463 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 572072987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 974001425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24843 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 835363066 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.186985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.073368 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 255962202 30.64% 30.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 125607638 15.04% 45.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118770145 14.22% 59.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111086257 13.30% 73.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 92824001 11.11% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61460839 7.36% 91.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43056890 5.15% 96.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19182433 2.30% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7412661 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 835363066 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11317596 42.46% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12272214 46.05% 88.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3062486 11.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719434 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211207278 66.30% 66.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 389699 0.02% 66.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880989 0.21% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 135 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 39 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued @@ -454,84 +454,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435021653 23.81% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173706920 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1826926557 # Type of FU issued -system.cpu.iq.rate 2.186445 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26652296 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014589 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4516265766 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2673396604 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1796798251 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32173 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70520 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7153 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1850844448 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14971 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185549711 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued +system.cpu.iq.rate 2.185458 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144242393 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 210251 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 386532 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 60678635 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19153 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1029 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10106871 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 107291908 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6438859 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2101061688 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 392799 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528344550 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 209838821 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7385 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1906737 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3653179 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 386532 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5738958 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4581595 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10320553 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805492449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 428838978 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21434108 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 598981338 # number of memory reference insts executed -system.cpu.iew.exec_branches 171787473 # Number of branches executed -system.cpu.iew.exec_stores 170142360 # Number of stores executed -system.cpu.iew.exec_rate 2.160793 # Inst execution rate -system.cpu.iew.wb_sent 1802094257 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1796805404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1368063103 # num instructions producing a value -system.cpu.iew.wb_consumers 2090238527 # num instructions consuming a value +system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed +system.cpu.iew.exec_branches 171793179 # Number of branches executed +system.cpu.iew.exec_stores 170131277 # Number of stores executed +system.cpu.iew.exec_rate 2.159821 # Inst execution rate +system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1367992688 # num instructions producing a value +system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.150397 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654501 # average fanout of values written-back +system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572152437 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9826757 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757699482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.017936 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.547497 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 289066041 38.15% 38.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175144894 23.12% 61.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57411271 7.58% 68.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86235215 11.38% 80.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27150149 3.58% 83.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27136057 3.58% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9784065 1.29% 88.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8843971 1.17% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76927819 10.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757699482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,338 +577,338 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76927819 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2781912801 # The number of ROB reads -system.cpu.rob.rob_writes 4280130406 # The number of ROB writes -system.cpu.timesIdled 2299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 206226 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2782646702 # The number of ROB reads +system.cpu.rob.rob_writes 4280772798 # The number of ROB writes +system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.010512 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.010512 # CPI: Total CPI of All Threads -system.cpu.ipc 0.989597 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.989597 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2761971319 # number of integer regfile reads -system.cpu.int_regfile_writes 1465030124 # number of integer regfile writes -system.cpu.fp_regfile_reads 7481 # number of floating regfile reads -system.cpu.fp_regfile_writes 493 # number of floating regfile writes -system.cpu.cc_regfile_reads 600902917 # number of cc regfile reads -system.cpu.cc_regfile_writes 409659635 # number of cc regfile writes -system.cpu.misc_regfile_reads 990136590 # number of misc regfile reads +system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads +system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads +system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes +system.cpu.fp_regfile_reads 7563 # number of floating regfile reads +system.cpu.fp_regfile_writes 476 # number of floating regfile writes +system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads +system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes +system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534249 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.994933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 387820460 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538345 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 152.784771 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2534281 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.994933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998046 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998046 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 784768509 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 784768509 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 239165062 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 239165062 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173846 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 387338908 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 387338908 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 387338908 # number of overall hits -system.cpu.dcache.overall_hits::total 387338908 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2789818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2789818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986356 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3776174 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3776174 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3776174 # number of overall misses -system.cpu.dcache.overall_misses::total 3776174 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 60126724251 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 60126724251 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31294703774 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31294703774 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91421428025 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91421428025 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91421428025 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91421428025 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 241954880 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 241954880 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits +system.cpu.dcache.overall_hits::total 387196758 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses +system.cpu.dcache.overall_misses::total 3775006 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 391115082 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 391115082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 391115082 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 391115082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21552.203137 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21552.203137 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31727.595081 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31727.595081 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24210.067657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24210.067657 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10621 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 71 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1078 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.852505 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332976 # number of writebacks -system.cpu.dcache.writebacks::total 2332976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1022764 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1022764 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18373 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18373 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1041137 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1041137 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1041137 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1041137 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks +system.cpu.dcache.writebacks::total 2332980 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967983 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 967983 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2735037 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2735037 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2735037 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2735037 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779636252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779636252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29507402723 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29507402723 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62287038975 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62287038975 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62287038975 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62287038975 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007303 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007303 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006993 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.443989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.443989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30483.389401 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30483.389401 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 7023 # number of replacements -system.cpu.icache.tags.tagsinuse 1053.963479 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 179273130 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20797.346868 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 7107 # number of replacements +system.cpu.icache.tags.tagsinuse 1054.726418 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 179314504 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8709 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20589.562981 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1053.963479 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.514631 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.514631 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1597 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1155 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.779785 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 359174294 # Number of tag accesses -system.cpu.icache.tags.data_accesses 359174294 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 179276307 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179276307 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179276307 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179276307 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179276307 # number of overall hits -system.cpu.icache.overall_hits::total 179276307 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 208110 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 208110 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 208110 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 208110 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 208110 # number of overall misses -system.cpu.icache.overall_misses::total 208110 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1327923993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1327923993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1327923993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1327923993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1327923993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1327923993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179484417 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179484417 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179484417 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179484417 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179484417 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179484417 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001159 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001159 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001159 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001159 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001159 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.875465 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6380.875465 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6380.875465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6380.875465 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1054.726418 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.515003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.515003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1602 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 330 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1149 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 359258778 # Number of tag accesses +system.cpu.icache.tags.data_accesses 359258778 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 179317997 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179317997 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179317997 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179317997 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179317997 # number of overall hits +system.cpu.icache.overall_hits::total 179317997 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 208472 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 208472 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 208472 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 208472 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 208472 # number of overall misses +system.cpu.icache.overall_misses::total 208472 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1336227738 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1336227738 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1336227738 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1336227738 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1336227738 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179526469 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179526469 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179526469 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179526469 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179526469 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179526469 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001161 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001161 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001161 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001161 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001161 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001161 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6409.626895 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6409.626895 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6409.626895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6409.626895 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.916667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2649 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2649 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2649 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2649 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2649 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2649 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205461 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205461 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205461 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205461 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205461 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205461 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 892683754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 892683754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 892683754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 892683754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 892683754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 892683754 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001145 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001145 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001145 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4344.784431 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4344.784431 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2630 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2630 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2630 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2630 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2630 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2630 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205842 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 205842 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 205842 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 205842 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 205842 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 205842 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 900667759 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 900667759 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 900667759 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 900667759 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 900667759 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 900667759 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001147 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001147 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001147 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4375.529576 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4375.529576 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354223 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29619.061304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3704244 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386583 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.582015 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 354249 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29619.496841 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3704141 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 386604 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.581228 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21085.370146 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.812049 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8281.879109 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.643474 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007685 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.252743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903902 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151922 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69310.425532 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68410.505357 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68428.135160 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18056.615369 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18056.615369 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66849.513502 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66849.513502 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3551 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179951 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195096 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 195096 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207017 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207017 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3551 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383417 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3551 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383417 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386968 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250130000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068381000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12318511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3521803787 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3521803787 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13841306537 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13841306537 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25909687537 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26159817537 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25909687537 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26159817537 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990451 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990451 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268322 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268322 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151924 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151924 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1972322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1972321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2332976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771484 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771484 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803050 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8017155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311764544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312317760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 196816 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5273474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 197098 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5273474 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5273474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4998709391 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 308726995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3988953025 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179934 # Transaction distribution -system.membus.trans_dist::ReadResp 179934 # Transaction distribution -system.membus.trans_dist::Writeback 294034 # Transaction distribution -system.membus.trans_dist::UpgradeReq 194832 # Transaction distribution -system.membus.trans_dist::UpgradeResp 194832 # Transaction distribution -system.membus.trans_dist::ReadExReq 206970 # Transaction distribution -system.membus.trans_dist::ReadExResp 206970 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1457506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1457506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1457506 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43580032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43580032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43580032 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 179950 # Transaction distribution +system.membus.trans_dist::ReadResp 179949 # Transaction distribution +system.membus.trans_dist::Writeback 294035 # Transaction distribution +system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution +system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution +system.membus.trans_dist::ReadExReq 206980 # Transaction distribution +system.membus.trans_dist::ReadExResp 206980 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 875770 # Request fanout histogram +system.membus.snoop_fanout::samples 876098 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 875770 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 875770 # Request fanout histogram -system.membus.reqLayer0.occupancy 2246779030 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 876098 # Request fanout histogram +system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2437213959 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 9a6a9e0dc..1702837e8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1229934 # Simulator instruction rate (inst/s) -host_op_rate 2274285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1316729165 # Simulator tick rate (ticks/s) -host_mem_usage 308776 # Number of bytes of host memory used -host_seconds 672.29 # Real time elapsed on the host +host_inst_rate 1361574 # Simulator instruction rate (inst/s) +host_op_rate 2517703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1457659146 # Simulator tick rate (ticks/s) +host_mem_usage 313840 # Number of bytes of host memory used +host_seconds 607.30 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 1120443517 # Wr system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution -system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution -system.membus.trans_dist::WriteReq 149160202 # Transaction distribution -system.membus.trans_dist::WriteResp 149160202 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram -system.membus.snoop_fanout::mean 2.667046 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 533262388 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::3 1068347065 66.70% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 1601609453 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction +system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution +system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution +system.membus.trans_dist::WriteReq 149160202 # Transaction distribution +system.membus.trans_dist::WriteResp 149160202 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram +system.membus.snoop_fanout::mean 0.667046 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 533262388 33.30% 33.30% # Request fanout histogram +system.membus.snoop_fanout::1 1068347065 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1601609453 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 43971ad10..d2da1780a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872738500 # Number of ticks simulated final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 730118 # Simulator instruction rate (inst/s) -host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1455043701 # Simulator tick rate (ticks/s) -host_mem_usage 323120 # Number of bytes of host memory used -host_seconds 1132.52 # Real time elapsed on the host +host_inst_rate 720688 # Simulator instruction rate (inst/s) +host_op_rate 1332632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1436248802 # Simulator tick rate (ticks/s) +host_mem_usage 323576 # Number of bytes of host memory used +host_seconds 1147.35 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -454,17 +454,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4844795 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4844795 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 5070249ec..592625271 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.216744 # Nu sim_ticks 216744260000 # Number of ticks simulated final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123383 # Simulator instruction rate (inst/s) -host_op_rate 148134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 97944157 # Simulator tick rate (ticks/s) -host_mem_usage 314844 # Number of bytes of host memory used -host_seconds 2212.94 # Real time elapsed on the host +host_inst_rate 172626 # Simulator instruction rate (inst/s) +host_op_rate 207257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137034779 # Simulator tick rate (ticks/s) +host_mem_usage 322768 # Number of bytes of host memory used +host_seconds 1581.67 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -783,17 +783,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 44377 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 4230ac10b..94f7097ff 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.112557 # Nu sim_ticks 112556618500 # Number of ticks simulated final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95501 # Simulator instruction rate (inst/s) -host_op_rate 114659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39369115 # Simulator tick rate (ticks/s) -host_mem_usage 319836 # Number of bytes of host memory used -host_seconds 2859.01 # Real time elapsed on the host +host_inst_rate 125639 # Simulator instruction rate (inst/s) +host_op_rate 150843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51793233 # Simulator tick rate (ticks/s) +host_mem_usage 327772 # Number of bytes of host memory used +host_seconds 2173.19 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1134,17 +1134,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 32515 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.009730 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3216936 99.03% 99.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 31609 0.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 08c45e0cd..e3d32f84d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 854590 # Simulator instruction rate (inst/s) -host_op_rate 1026030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 631341281 # Simulator tick rate (ticks/s) -host_mem_usage 304088 # Number of bytes of host memory used -host_seconds 319.51 # Real time elapsed on the host +host_inst_rate 1265309 # Simulator instruction rate (inst/s) +host_op_rate 1519144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 934796791 # Simulator tick rate (ticks/s) +host_mem_usage 311752 # Number of bytes of host memory used +host_seconds 215.79 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 517024352 # Request fanout histogram -system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram +system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::3 348660274 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 517024352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index eb13035d6..cfbe2044c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -591,17 +591,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 5cc3f8bc2..f250ad066 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.545048 # Nu sim_ticks 545048444500 # Number of ticks simulated final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131789 # Simulator instruction rate (inst/s) -host_op_rate 162250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112122004 # Simulator tick rate (ticks/s) -host_mem_usage 314432 # Number of bytes of host memory used -host_seconds 4861.21 # Real time elapsed on the host +host_inst_rate 177094 # Simulator instruction rate (inst/s) +host_op_rate 218026 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 150665678 # Simulator tick rate (ticks/s) +host_mem_usage 323140 # Number of bytes of host memory used +host_seconds 3617.60 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -808,17 +808,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 899017 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index d04be0b82..bdaafd38c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.409388 # Number of seconds simulated -sim_ticks 409388341000 # Number of ticks simulated -final_tick 409388341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 409388416000 # Number of ticks simulated +final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75979 # Simulator instruction rate (inst/s) -host_op_rate 93540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48552243 # Simulator tick rate (ticks/s) -host_mem_usage 312124 # Number of bytes of host memory used -host_seconds 8431.91 # Real time elapsed on the host +host_inst_rate 93306 # Simulator instruction rate (inst/s) +host_op_rate 114872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59624294 # Simulator tick rate (ticks/s) +host_mem_usage 320320 # Number of bytes of host memory used +host_seconds 6866.13 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 226496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 20189120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17157303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31604769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49315327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10371297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10371297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10371297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17157303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31604769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59686624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315455 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315456 # Number of read requests accepted system.physmem.writeReqs 66342 # Number of write requests accepted -system.physmem.readBursts 315455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20169536 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20189120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 19899 # Per bank write bursts system.physmem.perBankRdBursts::1 19575 # Per bank write bursts system.physmem.perBankRdBursts::2 19715 # Per bank write bursts @@ -67,7 +67,7 @@ system.physmem.perBankRdBursts::11 19765 # Pe system.physmem.perBankRdBursts::12 19604 # Per bank write bursts system.physmem.perBankRdBursts::13 19959 # Per bank write bursts system.physmem.perBankRdBursts::14 19457 # Per bank write bursts -system.physmem.perBankRdBursts::15 19977 # Per bank write bursts +system.physmem.perBankRdBursts::15 19978 # Per bank write bursts system.physmem.perBankWrBursts::0 4260 # Per bank write bursts system.physmem.perBankWrBursts::1 4107 # Per bank write bursts system.physmem.perBankWrBursts::2 4142 # Per bank write bursts @@ -86,14 +86,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4150 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409388286500 # Total gap between requests +system.physmem.totGap 409388361500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315455 # Read request sizes (log2) +system.physmem.readPktSize::6 315456 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -101,7 +101,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66342 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see @@ -197,20 +197,20 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136711 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.525503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.653130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.190580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57416 42.00% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14736 10.78% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes @@ -248,12 +248,12 @@ system.physmem.wrPerTurnAround::27 2 0.05% 99.93% # Wr system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads -system.physmem.totQLat 9474891317 # Total ticks spent queuing -system.physmem.totMemAccLat 15383935067 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1575745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30064.80 # Average queueing delay per DRAM burst +system.physmem.totQLat 9474850817 # Total ticks spent queuing +system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48814.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s @@ -264,11 +264,11 @@ system.physmem.busUtilRead 0.38 # Da system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 218193 # Number of row buffer hits during reads +system.physmem.readRowHits 218195 # Number of row buffer hits during reads system.physmem.writeRowHits 26465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.23 # Row buffer hit rate for reads +system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes -system.physmem.avgGap 1072266.90 # Average gap between requests +system.physmem.avgGap 1072264.29 # Average gap between requests system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ) @@ -279,32 +279,32 @@ system.physmem_0.actBackEnergy 96374211480 # En system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ) system.physmem_0.averagePower 699.719632 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267357168520 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514715040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280846500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 286420773645 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.635490 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 267598080337 # Time in different power states +system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.635519 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233960254 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822373 # Number of conditional branches predicted +system.cpu.branchPred.lookups 233960267 # Number of BP lookups +system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121575796 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108259792 # Number of BTB hits +system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.047159 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -425,84 +425,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 818776683 # number of cpu cycles simulated +system.cpu.numCycles 818776833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84080283 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200690611 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233960254 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133296622 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718833631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3279 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370702181 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 818451212 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.833527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136785734 16.71% 16.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223134622 27.26% 43.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075130 11.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360455726 44.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 818451212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.466445 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119992571 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159648210 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662538 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38629741 # Number of cycles decode is unblocking +system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181026 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248127712 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967189 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 177000170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78888622 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464955823 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81877741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190635480 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25549977 # Number of squashed instructions processed by rename +system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1694220 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225376851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812387634 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358166964 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350598621 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108139964 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366113107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095924 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168545112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017136895 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18518107 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379832511 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032101117 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 818451212 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.242758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 260801504 31.87% 31.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227738074 27.83% 59.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216482418 26.45% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97282888 11.89% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16146319 1.97% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -510,7 +510,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 818451212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available @@ -541,12 +541,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155540663 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116678902 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370981 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued @@ -575,40 +575,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 11478993 1.13% 47.13% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322128329 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215587412 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017136895 # Type of FU issued +system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued system.cpu.iq.rate 1.242264 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337386313 # FU busy when requested +system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3146752380 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504842501 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934271178 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320712858 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113872169 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107115428 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35325435 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168563023 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366113107 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095924 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall @@ -616,43 +616,43 @@ system.cpu.iew.memOrderViolationEvents 18393 # Nu system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751162 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297617 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42385733 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5554 # number of nop insts executed -system.cpu.iew.exec_refs 497765227 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613464 # Number of branches executed -system.cpu.iew.exec_stores 194467610 # Number of stores executed +system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613469 # Number of branches executed +system.cpu.iew.exec_stores 194467616 # Number of stores executed system.cpu.iew.exec_rate 1.190497 # Inst execution rate -system.cpu.iew.wb_sent 963723916 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960423621 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536680580 # num instructions producing a value -system.cpu.iew.wb_consumers 893282190 # num instructions consuming a value +system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536680583 # num instructions producing a value +system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357407190 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 767630958 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.027486 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 430922921 56.14% 56.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172477665 22.47% 78.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31624091 4.12% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14250533 1.86% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360346 2.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 767630958 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 767631497 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,30 +698,30 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360346 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1891399121 # The number of ROB reads -system.cpu.rob.rob_writes 2343098694 # The number of ROB writes -system.cpu.timesIdled 647342 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 325471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360345 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1891399680 # The number of ROB reads +system.cpu.rob.rob_writes 2343098733 # The number of ROB writes +system.cpu.timesIdled 647345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 325081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995806500 # number of integer regfile reads -system.cpu.int_regfile_writes 567906149 # number of integer regfile writes +system.cpu.int_regfile_reads 995806519 # number of integer regfile reads +system.cpu.int_regfile_writes 567906159 # number of integer regfile writes system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794435390 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898944 # number of cc regfile writes -system.cpu.misc_regfile_reads 715817585 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794435468 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898950 # number of cc regfile writes +system.cpu.misc_regfile_reads 715817595 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes system.cpu.dcache.tags.replacements 2756184 # number of replacements system.cpu.dcache.tags.tagsinuse 511.932971 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414226707 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 414226712 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.262019 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.262021 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.932971 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy @@ -732,10 +732,10 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 224 system.cpu.dcache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839343974 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839343974 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286295255 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286295255 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 839343984 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839343984 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286295259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286295259 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 127916705 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 127916705 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3174 # number of SoftPFReq hits @@ -744,34 +744,34 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414211960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414211960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414215134 # number of overall hits -system.cpu.dcache.overall_hits::total 414215134 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031607 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031607 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 414211964 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414211964 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414215138 # number of overall hits +system.cpu.dcache.overall_hits::total 414215138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031608 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031608 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1034772 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1034772 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4066379 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4066379 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4067026 # number of overall misses -system.cpu.dcache.overall_misses::total 4067026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35304231919 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35304231919 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981686625 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9981686625 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4066380 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4066380 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4067027 # number of overall misses +system.cpu.dcache.overall_misses::total 4067027 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35305181420 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35305181420 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981703626 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9981703626 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45285918544 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45285918544 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45285918544 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45285918544 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289326862 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289326862 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 45286885046 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45286885046 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45286885046 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45286885046 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289326867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289326867 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3821 # number of SoftPFReq accesses(hits+misses) @@ -780,10 +780,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418278339 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418278339 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418282160 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418282160 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418278344 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418278344 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418282165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418282165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses @@ -796,16 +796,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.385407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.385407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.266641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.266641 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.283071 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.283071 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.669392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11136.669392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11134.897722 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11134.897722 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11136.904334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11135.132628 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 343566 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,16 +816,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 735673 # number of writebacks system.cpu.dcache.writebacks::total 735673 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996398 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 996398 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996399 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 996399 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313907 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 313907 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1310305 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1310305 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1310305 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1310305 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1310306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1310306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1310306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1310306 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720865 # number of WriteReq MSHR misses @@ -836,16 +836,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23117834450 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23117834450 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596502782 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596502782 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23118028700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23118028700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596519781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596519781 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5770003 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5770003 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714337232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28714337232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720107235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28720107235 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714548481 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28714548481 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720318484 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28720318484 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses @@ -856,108 +856,108 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11358.948614 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11358.948614 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.593436 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.593436 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.617017 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.617017 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9001.564743 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9001.564743 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.565406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.565406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.235920 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.235920 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169973 # number of replacements +system.cpu.icache.tags.replacements 5169974 # number of replacements system.cpu.icache.tags.tagsinuse 511.005918 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 365527993 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5170483 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.695135 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 365528009 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5170484 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.695124 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 247768250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.005918 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 746574800 # Number of tag accesses -system.cpu.icache.tags.data_accesses 746574800 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 365528016 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 365528016 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 365528016 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 365528016 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 365528016 # number of overall hits -system.cpu.icache.overall_hits::total 365528016 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174133 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174133 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174133 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174133 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174133 # number of overall misses -system.cpu.icache.overall_misses::total 5174133 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647669446 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41647669446 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41647669446 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41647669446 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41647669446 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41647669446 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370702149 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370702149 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370702149 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370702149 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370702149 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370702149 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 746574831 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746574831 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365528032 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365528032 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365528032 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 365528032 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 365528032 # number of overall hits +system.cpu.icache.overall_hits::total 365528032 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174132 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174132 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174132 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174132 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174132 # number of overall misses +system.cpu.icache.overall_misses::total 5174132 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647443196 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41647443196 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41647443196 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41647443196 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41647443196 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41647443196 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370702164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370702164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370702164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370702164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370702164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370702164 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013958 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.207364 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8049.207364 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8049.207364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8049.207364 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 75182 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.165193 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8049.165193 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8049.165193 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8049.165193 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75254 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3130 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.019808 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.042812 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3630 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3630 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3630 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3630 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3630 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3630 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170503 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170503 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170503 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170503 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170503 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170503 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431563436 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36431563436 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431563436 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36431563436 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431563436 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36431563436 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3628 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3628 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3628 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3628 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3628 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3628 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170504 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5170504 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5170504 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5170504 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5170504 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5170504 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431387686 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36431387686 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431387686 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36431387686 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431387686 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36431387686 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013948 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013948 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013948 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.038545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.038545 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.003192 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.003192 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 1347095 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 1354943 # number of prefetch candidates identified @@ -965,43 +965,41 @@ system.cpu.l2cache.prefetcher.pfBufferHit 6866 # n system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4789921 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 299164 # number of replacements +system.cpu.l2cache.tags.replacements 299165 # number of replacements system.cpu.l2cache.tags.tagsinuse 16361.556320 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7824806 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 315528 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.799086 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 315529 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.799007 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 13406100000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 743.987058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512594 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474196 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 743.986923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582614 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474164 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.045409 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.535375 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410063 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6518 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9846 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6520 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 9844 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1451 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1454 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4880 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2089 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7268 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397827 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600952 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139642343 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139642343 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2085 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7271 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397949 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600830 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139642360 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139642360 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 5166932 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1926211 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7093143 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 735673 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 735673 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 717988 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 717988 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 5166932 # number of demand (read+write) hits @@ -1010,50 +1008,52 @@ system.cpu.l2cache.demand_hits::total 7811131 # nu system.cpu.l2cache.overall_hits::cpu.inst 5166932 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2644199 # number of overall hits system.cpu.l2cache.overall_hits::total 7811131 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3553 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3554 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 109639 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 113192 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 113193 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2858 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2858 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3553 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3554 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 112497 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 116050 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3553 # number of overall misses +system.cpu.l2cache.demand_misses::total 116051 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3554 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 112497 # number of overall misses -system.cpu.l2cache.overall_misses::total 116050 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 261165964 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561744931 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8822910895 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::total 116051 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260989714 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561938681 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8822928395 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 205223699 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 205223699 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 261165964 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8766968630 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9028134594 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 261165964 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8766968630 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9028134594 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170485 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 260989714 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8767162380 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9028152094 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 260989714 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8767162380 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9028152094 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7206335 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7206336 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 735673 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 735673 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5170485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5170486 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2756696 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7927181 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5170485 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7927182 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5170486 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2756696 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7927181 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7927182 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000687 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053854 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015707 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003965 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.003965 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000687 # miss rate for demand accesses @@ -1062,17 +1062,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.014640 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000687 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.040809 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73505.759640 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78090.323069 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77946.417547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.485087 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.090232 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77945.883535 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1236.789474 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1236.789474 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71806.752624 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71806.752624 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77795.214080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77795.214080 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77794.694522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77794.694522 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,130 +1096,128 @@ system.cpu.l2cache.demand_mshr_hits::total 2761 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 2747 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 2761 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3540 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108352 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 111891 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111892 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202242 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 202242 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839648036 # number of ReadReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17078829649 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 248018 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 248018 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 262019 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 262019 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114010508 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114010508 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230067036 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723581508 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7953648544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230067036 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723581508 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229882786 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723775758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7953658544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229882786 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723775758 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25032478193 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 25032488193 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053222 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583 # average ReadReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.715074 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7206353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7206352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340989 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16590090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330910976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330911040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554422592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 248905 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8911778 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.027928 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 8662891 97.21% 97.21% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 248887 2.79% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8911778 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5067118500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756291499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4138722865 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 314057 # Transaction distribution -system.membus.trans_dist::ReadResp 314057 # Transaction distribution +system.membus.trans_dist::ReadReq 314058 # Transaction distribution +system.membus.trans_dist::ReadResp 314058 # Transaction distribution system.membus.trans_dist::Writeback 66342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 18 # Transaction distribution -system.membus.trans_dist::UpgradeResp 18 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19 # Transaction distribution +system.membus.trans_dist::UpgradeResp 19 # Transaction distribution system.membus.trans_dist::ReadExReq 1398 # Transaction distribution system.membus.trans_dist::ReadExResp 1398 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24435008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381815 # Request fanout histogram +system.membus.snoop_fanout::samples 381817 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381815 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381815 # Request fanout histogram -system.membus.reqLayer0.occupancy 746604866 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381817 # Request fanout histogram +system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648190996 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 790f4a782..f8c904908 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1109777 # Simulator instruction rate (inst/s) -host_op_rate 1366282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 685499869 # Simulator tick rate (ticks/s) -host_mem_usage 303676 # Number of bytes of host memory used -host_seconds 577.28 # Real time elapsed on the host +host_inst_rate 1575908 # Simulator instruction rate (inst/s) +host_op_rate 1940150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 973424664 # Simulator tick rate (ticks/s) +host_mem_usage 311080 # Number of bytes of host memory used +host_seconds 406.53 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram +system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::3 643377899 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 1022670353 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e0c0a3846..4a7e6f230 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -598,17 +598,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 22befaf24..12a478a63 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.057717 # Nu sim_ticks 57716694500 # Number of ticks simulated final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141604 # Simulator instruction rate (inst/s) -host_op_rate 181090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115249030 # Simulator tick rate (ticks/s) -host_mem_usage 314220 # Number of bytes of host memory used -host_seconds 500.80 # Real time elapsed on the host +host_inst_rate 194770 # Simulator instruction rate (inst/s) +host_op_rate 249082 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158520150 # Simulator tick rate (ticks/s) +host_mem_usage 322420 # Number of bytes of host memory used +host_seconds 364.10 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -809,17 +809,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 333867 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 333867 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index e0d8233d1..3b7597919 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.033331 # Nu sim_ticks 33330913000 # Number of ticks simulated final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93420 # Simulator instruction rate (inst/s) -host_op_rate 119473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43913176 # Simulator tick rate (ticks/s) -host_mem_usage 317168 # Number of bytes of host memory used -host_seconds 759.02 # Real time elapsed on the host +host_inst_rate 123947 # Simulator instruction rate (inst/s) +host_op_rate 158514 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58262578 # Simulator tick rate (ticks/s) +host_mem_usage 323704 # Number of bytes of host memory used +host_seconds 572.08 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1158,17 +1158,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 151304 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.123542 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.123542 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1073332 87.65% 87.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 151292 12.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1073332 87.65% 87.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 151292 12.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index abad5bc99..fd03f6311 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.121265 # Nu sim_ticks 1121265462500 # Number of ticks simulated final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175724 # Simulator instruction rate (inst/s) -host_op_rate 189316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127565822 # Simulator tick rate (ticks/s) -host_mem_usage 306448 # Number of bytes of host memory used -host_seconds 8789.70 # Real time elapsed on the host +host_inst_rate 238084 # Simulator instruction rate (inst/s) +host_op_rate 256500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172835636 # Simulator tick rate (ticks/s) +host_mem_usage 314372 # Number of bytes of host memory used +host_seconds 6487.47 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -816,17 +816,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 12928956 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12928956 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ddc6d4e58..d2f403426 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.771725 # Nu sim_ticks 771725169000 # Number of ticks simulated final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109963 # Simulator instruction rate (inst/s) -host_op_rate 118469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54942138 # Simulator tick rate (ticks/s) -host_mem_usage 305172 # Number of bytes of host memory used -host_seconds 14046.14 # Real time elapsed on the host +host_inst_rate 137392 # Simulator instruction rate (inst/s) +host_op_rate 148019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68646343 # Simulator tick rate (ticks/s) +host_mem_usage 311812 # Number of bytes of host memory used +host_seconds 11242.04 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1153,17 +1153,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1298291 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.056115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 21838103 94.39% 94.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 1298291 5.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 93ba57c1e..39b8c8798 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1379227 # Simulator instruction rate (inst/s) -host_op_rate 1485908 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 742955189 # Simulator tick rate (ticks/s) -host_mem_usage 295688 # Number of bytes of host memory used -host_seconds 1119.88 # Real time elapsed on the host +host_inst_rate 1936914 # Simulator instruction rate (inst/s) +host_op_rate 2086731 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1043366913 # Simulator tick rate (ticks/s) +host_mem_usage 303348 # Number of bytes of host memory used +host_seconds 797.44 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram -system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram +system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::3 1544565590 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 2172060895 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 15b1ad4ad..144026919 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -590,17 +590,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12813292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 566338996..08e41bb17 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1299561 # Simulator instruction rate (inst/s) -host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1229541445 # Simulator tick rate (ticks/s) -host_mem_usage 299440 # Number of bytes of host memory used -host_seconds 2314.69 # Real time elapsed on the host +host_inst_rate 1464727 # Simulator instruction rate (inst/s) +host_op_rate 2282177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1385807923 # Simulator tick rate (ticks/s) +host_mem_usage 304512 # Number of bytes of host memory used +host_seconds 2053.68 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution -system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution -system.membus.trans_dist::WriteReq 438528338 # Transaction distribution -system.membus.trans_dist::WriteResp 438528338 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram -system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram -system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 5690945966 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution +system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution +system.membus.trans_dist::WriteReq 438528338 # Transaction distribution +system.membus.trans_dist::WriteResp 438528338 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram +system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram +system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 5690945966 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 9a9ddb0f1..b101e64c0 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882580 # Nu sim_ticks 5882580398500 # Number of ticks simulated final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 733187 # Simulator instruction rate (inst/s) -host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1433815394 # Simulator tick rate (ticks/s) -host_mem_usage 313792 # Number of bytes of host memory used -host_seconds 4102.75 # Real time elapsed on the host +host_inst_rate 739516 # Simulator instruction rate (inst/s) +host_op_rate 1152234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1446192754 # Simulator tick rate (ticks/s) +host_mem_usage 314252 # Number of bytes of host memory used +host_seconds 4067.63 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,17 +449,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12811308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index fc0b314ed..da5e39914 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131767 # Nu sim_ticks 131767151500 # Number of ticks simulated final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176753 # Simulator instruction rate (inst/s) -host_op_rate 186327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135158895 # Simulator tick rate (ticks/s) -host_mem_usage 309748 # Number of bytes of host memory used -host_seconds 974.91 # Real time elapsed on the host +host_inst_rate 244794 # Simulator instruction rate (inst/s) +host_op_rate 258052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187187675 # Simulator tick rate (ticks/s) +host_mem_usage 317932 # Number of bytes of host memory used +host_seconds 703.93 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -783,17 +783,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6517 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e84c7e623..a8c1caea2 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.085032 # Nu sim_ticks 85032044000 # Number of ticks simulated final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98638 # Simulator instruction rate (inst/s) -host_op_rate 103981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48678127 # Simulator tick rate (ticks/s) -host_mem_usage 307440 # Number of bytes of host memory used -host_seconds 1746.82 # Real time elapsed on the host +host_inst_rate 135904 # Simulator instruction rate (inst/s) +host_op_rate 143266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67069129 # Simulator tick rate (ticks/s) +host_mem_usage 314096 # Number of bytes of host memory used +host_seconds 1267.83 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1113,17 +1113,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 2153 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011018 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011018 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 193263 98.90% 98.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 2153 1.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 193263 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2153 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 00f8f6a2f..1d32cdbce 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.081225 # Nu sim_ticks 81224844500 # Number of ticks simulated final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72712 # Simulator instruction rate (inst/s) -host_op_rate 121872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44718419 # Simulator tick rate (ticks/s) -host_mem_usage 340792 # Number of bytes of host memory used -host_seconds 1816.36 # Real time elapsed on the host +host_inst_rate 91947 # Simulator instruction rate (inst/s) +host_op_rate 154111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56548085 # Simulator tick rate (ticks/s) +host_mem_usage 347388 # Number of bytes of host memory used +host_seconds 1436.39 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -944,17 +944,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 299 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10459 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10459 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |